JP3543953B2 - Labeled packet transfer processing method and communication device therefor - Google Patents

Labeled packet transfer processing method and communication device therefor Download PDF

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Publication number
JP3543953B2
JP3543953B2 JP2000245841A JP2000245841A JP3543953B2 JP 3543953 B2 JP3543953 B2 JP 3543953B2 JP 2000245841 A JP2000245841 A JP 2000245841A JP 2000245841 A JP2000245841 A JP 2000245841A JP 3543953 B2 JP3543953 B2 JP 3543953B2
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packet
labeled
ip
transfer
destination
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JP2002064542A (en
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道雄 升田
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日本電気株式会社
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Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a labeled packet transfer processing method for processing an IP packet of an IP network of a network layer of an ISO reference model having seven layers and a labeled packet in which a multilayer class is identified and labeled, and a communication device therefor.
[0002]
[Prior art]
With the tremendous growth of data communications, carriers must reinforce their core networks to cope with Internet Protocol (IP) traffic. At the same time, there is a need to lower costs and maximize return on network investment.
[0003]
Recently, it is necessary to guarantee QOS (Quality of Service) in an IP (Internet Protocol) network, and the discussion and specification of QOS control technology are being advanced in IETF (Internet Engineering Task Force) and the like. Among them, a multi-protocol label switching (MPLS), which has been discussed for realizing a path control technology using QOS information and a traffic engineering technology for the purpose of improving network use efficiency, has become a technical trend.
[0004]
This MPLS introduces the concept of label swap represented by ATM into the network layer routing. By using explicit route specification, traffic flowing in the network is forcibly reduced. The control for turning to a proper path (Constraint Path) can be easily realized.
[0005]
The advantages of the MultiProtocol Label Switching (MPLS) scheme over the existing IP over ATM include the following.
[0006]
(1) By unifying routing management, control can be simplified and speeded up.
[0007]
(2) Scalability can be ensured by establishing a physical Neighbor relationship.
[0008]
On the other hand, in the IP over ATM Overlay Model, a huge number of adjacencies are established between routers because the adjacency is established by all network connections (Mesh Connections) between the Edge Routers in which the communication source and the communication destination are directly connected. There was a problem.
[0009]
FIG. 10 shows a transfer mechanism in the MPLS network for transmitting a plurality of types of packets such as IP packets, ATM cells, and Ethernet cells.
[0010]
In the MPLS domain, a virtual path called a Label Switching Path (LSP: 10e) is set for a group of packets having the same transfer rule. At the lowest entry router (Ingress Boundary Router: 10a) of the MPLS domain in FIG. 10, a router (Label Switching Router: LSR) that performs a label switch is a set having the same transfer rule, FEC (Forwarding). Equivalency Class). The same "short fixed length label" (short fixed-length label: 10e) is added to the packet group mapped to the same FEC (the above processing is referred to as Label push).
[0011]
The packet to which the label is added is called a labeled packet (Labeled Packet: 10f), and in the Interior LSR (10b) in the MPLS domain (10d), packet forwarding is performed by the label attached to the packet (the processing described on the left is performed). The label is stripped off at an egress router (Egress Boundary Router: 10c) of the MPLS domain (the process described on the left is called a Label pop). This results in the same packet as the packet group input to the ingress router. Here, as shown in the lowermost stage of FIG. 10, the ingress router and the egress router conduct to the IP layer, have an LSR function, and other routers that merely conduct conduct to the MPLS layer. Also, as shown in the middle part of FIG. 10, a label is added as a label push at the ingress router, the labeled packet group sequentially passes through the router, passes as a label swap, the label is peeled off at the egress router, and the label is removed. Popped.
[0012]
According to FIG. 11, an MPLS domain (11c) composed of an edge (11a) between an ingress router and an egress router and a core node (11b) passing through an intermediate router is formed as a network configuration. All transfer in the MPLS-DiffServ domain (11c) is basically performed by MPLS, and when input as an IP packet at an ingress router, a label is added as an MPLS packet, the intermediate router passes as an MPLS packet, and an egress router. The IP packet is mixed with the MPLS packet when the LSP (label switch path) (11d) is being set up or the LSP is not enabled due to the configuration, etc. It can be. Also, LSP setup messages and routing packets are basically transferred as IP packets.
[0013]
In the ingress router, the traffic control (Traffic Conditioning Functions) in the network edge node (11a) manages each IP flow (11e) to which the user contracts, and assigns an MPLS label (11g) according to the above. .
[0014]
The network core node (11b) performs processing in units of class flows (DS-PHB: 11f) configured by aggregating (aggregating) individual IP flows, and performs MPLS label replacement (11h). The validity of this model is as follows.
[0015]
(1) The problem of complicated management depends on the number of target flows, and a huge number of IP flows are mixed in a network core node. Therefore, IP flow management in a core node increases costs.
[0016]
(2) Since the link interface of the network edge node is low-speed and becomes higher as the link interface of the network core node becomes higher, it is difficult to realize the same function as the edge node in the core node.
[0017]
(3) The packet transfer delay time and CDV time in the high-speed link interface are smaller than the delay time and CDV time in the low-speed link interface. That is, from the viewpoint of the whole network, the complexity of fine priority control in the low-speed link interface is dominant, and simple priority control is sufficient for the high-speed link interface (core node).
[0018]
The elemental technologies for realizing the above network model are as follows. [Process at Edge]: MF Classifier & Label push / swap / pop & Diffserv edge function, which is a method that proposes a management process of the Internet to be differentiated over a wide area for an Intserv effective for a small area.
[Process in Core]: BA Classifier & Label swap / PH-pop & Diffserv Core Function
[Multi-Field Classifier (MF)]: A method of determining a traffic class based on a combination of a plurality of fields of an IP header and a layer 4 header (Classifier).
[Behavior Aggregate Classifier (BA)]: A method of determining a traffic class by referring only to the TOS field of the IP header.
[0019]
Here, the architecture of a conventional router will be described as a conventional technique. As a device that connects a plurality of networks, particularly LANs, and relays packet data, an Open Systems Interconnection (OSI) defined by the International Organization for Standard (ISO) is known. In the reference model, devices such as a "bridge" for making a connection in a data link layer of Layer 2 (particularly, a media access sub-layer) and a "router" for making a connection in a network layer which is an upper layer thereof are known. .
[0020]
FIG. 1 shows an example of a basic architecture in a conventional (IP over ATM) router device.
[0021]
A Line Card (line card) (1a) having a main signal input / output unit such as a dedicated packet processing hardware circuit, a Forwarding Engine (FE) card (1b) having a route search processing unit, and an N × N crossbar system And a switch fabric (1d).
[0022]
IP packet forwarding (transfer) processing is aimed at improving overall throughput performance and preventing packet discarding, and is required to have high speed at first. On the other hand, in routing processing, it is important to provide various services using various routing protocols rather than high speed. If the forwarding process and the routing process are performed by the same CPU or the like, both processes interfere with each other, and it is difficult to exhibit the highest performance as an apparatus system. For this reason, the conventional router separates the forwarding function and the routing function, and performs the forwarding function (FE) and the network processor (NP), respectively. This function separation is remarkably applied to high-speed routers, and generally, the forwarding processing unit is implemented by hardware (ASIC) to increase the speed.
[0023]
The forwarding engine (FE) includes a high-speed processor, and realizes high-speed transfer processing at a dedicated hardware level under the control of an assembler program. Therefore, it is possible to flexibly cope with a change in the packet filtering function, a change in the header format, and the like. Further, if the processor having a higher clock frequency appears in the future, there is an advantage that it can contribute to the improvement of the processing performance of the FE.
[0024]
Basic IP packet forwarding processing is performed between the line card and the FE card. Only the layer 3 (for example, IP) header portion is transferred from the line card to the FE, and the FE performs an address search to determine an output port. The FE updates the TTL (Time To Live) and the checksum of the IP header and returns the IP header and the output port information to the line card. The information at this time is called an Updated Header (UH). The line card receiving the UH replaces the received IP header with the UH, and transfers the entire packet to the output port via the crossbar switch.
[0025]
Line Card (LC) and Forwarding Engine (FE) cards can be mounted on a common slot chassis as a Function Card. That is, a plurality of FEs can be mounted, the load can be distributed on a card-by-card basis, and the throughput performance of the entire apparatus can be expanded.
[0026]
The switch fabric (1d) includes a crossbar switch (Switch Data Path (DP)) (1d1) and a connection arbitration circuit (Switch Allocator (SA)) (1d2). DP (1d1) is a switch having an N input port × N output port configuration by a crossbar system. The SA (1d2) connects an N × N switching port to the DP (1d1) based on a switch connection request from all function cards (maximum N cards) or a packet reception rejection notice for each unit switch cycle. Has the function of determining
[0027]
The connection pattern of the switch is switched in fixed cycle units. This operation unit is called an epoch. The connection arbitration circuit also operates in a pipeline in epoch units. The connection pattern is determined based on the state of the bid signal (each N-bit mask signal for requesting connection) and the Inhibit signal (each N-bit mask signal for requesting reception inhibition) of each card. A plurality of levels of priority can be set in the connection arbitration circuit, and the Bid signal from the FE card is processed with higher priority than the Bid signal of the line card. When a collision of a bid request signal occurs, priority is added, and if the priority is the same, shuffling is performed to ensure fairness.
[0028]
[Problems to be solved by the invention]
However, the conventional router architecture has the following problems.
[0029]
<Issue 1>
Conventionally, a router is specialized in an IP transfer system, and therefore, most of the architecture of the device does not include a transfer unit required for MPLS transfer. In the conventional IP packet transfer in the router, the Route Request Page is temporarily transferred to the FE, and after the destination is resolved, the transfer method is performed to the destination Line Card. However, the above transfer method is used for label switching such as MPLS. Not suitable. This is because a route search is performed by the FE for each packet, and a route-request / updated-header transfer occurs between the FE card and the line card due to the route search. Here, focusing on the transfer direction from the line card to the switch, a page transfer of “the number of pages forming the packet + 1 page of the Route request” occurs per packet transfer, resulting in waste of bandwidth resources of the switch. . The above phenomenon is that when short packets are input at full load, the switch capacity is occupied by the route request and the transfer band of the main signal transfer system, and the band for the update header transfer is clearly lacking, which is a bottleneck point in the transfer performance. obtain.
[0030]
<Issue 2>
Conventionally, routers are assumed to operate using both an IP packet switching function and an ATM cross-connect (so-called cell bridge) function. For an ATM cell having a specific virtual channel (VC) connection, a transfer function that does not pass through the FE is provided. However, the above function is merely a cell switch, and does not have a decellularization (reconstructing a cell into a packet) function. Therefore, there is a drawback that a special hardware circuit for deceleration needs to be added or revised.
[0031]
Therefore, an object of the present invention is to cause a router specialized in an IP transfer system to perform MPLS transfer and perform decelling without adding a special hardware circuit.
[0032]
[Means for Solving the Problems]
The present invention provides a labeled packet communication apparatus having means for controlling a labeled packet mixed with an IP packet in accordance with network quality of service (QOS). MPLS resolution circuit for resolving transfer destination information and class information from a label indicating the above, a flow detection circuit for performing route resolution, label processing, and class resolution, and FE (Forwarding) only unresolvable packets or special packets (Optional Header). (Engine) to avoid the problem of throughput degradation due to the FE transfer.
[0033]
The present invention also relates to a labeled packet transfer processing method having means for controlling a labeled packet mixed with an IP packet in accordance with a network quality of service (QOS), wherein the labeled packet is transferred from a label indicating a destination. The destination information and the class information are resolved by the MPLS resolution circuit, the route resolution, the label processing, and the class resolution are performed by the flow detection circuit, and only the unresolvable packet or the special packet (Optional Header) is transferred to the FE (Forwarding Engine). Thus, the problem of throughput degradation due to the FE transfer is avoided.
[0034]
Further, the present invention provides a packet communication apparatus for processing an IP packet of an IP network and a labeled packet which identifies and labels a multi-layer class, a line card for transmitting / receiving a plurality of packets, and a line card connected to the line card. A switching device for switching to a destination; and a forwarding engine card connected to the switching device. The IP packet is stored in a memory in the line card, and then a header portion of the IP packet is passed through the switching device. A route is set by a route search processing unit in the forwarding engine card, and the set route information is obtained by converting the set route information from the forwarding engine card via the switch device into a header portion of the IP packet. Output to the destination line card Is the labeled packet is output to the label per the said forwarding engine card through the switch device to cut-through of the destination line card after it has been stored in the memory in the line card.
[0035]
Further, the present invention is an apparatus having means for controlling a labeled packet mixed with an IP (Internet Protocol) packet in accordance with network service quality (Quality of Service: QOS). In accordance with the function architecture of a conventional router having a connect function, when a conventional router is extended to a LSR (Label Switching Router) at a low cost, a flexible transition is possible (seamless), and a packet having excellent versatility is provided. Provided are a transfer processing method and a communication device.
[0036]
Further, the present invention is a hardware circuit for resolving transfer destination information and class information from a label indicating a destination in packet communication such as an IP network, and has means for realizing the following functions.
(1) Even if the labeled packet is cut-through transferred in the device and the IP packet is transferred via the FE, a function to reassemble the packet in the virtual input queue (VIQ) unit works. To do.
(2) The flow detection circuit performs path resolution, label processing, and class resolution, and transfers only unresolvable packets and special packets (Optional Header) to FE (Forwarding Engine), thereby deteriorating throughput due to FE transfer. Avoid problems.
[0037]
In the conventional example, in order to resolve the transfer destination information from the destination IP address, all the data is transferred to the FE via the switch. However, in the present invention, the labeled packet and the IP packet are identified, and the labeled packet is stored in the line card. Has a distributing means for performing route resolution by the dedicated engine of, and transferring the IP packet by FE.
[0038]
In the conventional example, an ATM cell having a specific VC (Virtual Connection) has a cell bridge function for performing transfer without passing through the FE. However, the function is a simple cell switch, and a decellularization ( It does not have the function of reconstructing cells into packets. For this reason, there is a drawback that a special hardware circuit for FE deceleration needs to be added or revised. However, in the present invention, the current deceleration circuit can be used even in a cut-through transfer system that does not go through FE. It has means to make it.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram showing an apparatus configuration to which the present invention is applied.
[0040]
The device according to the present embodiment is a configuration that inherits the conventional high-speed router architecture, and is, for example, a high-speed, high-bandwidth core router that is supposed to be placed on the backbone, and has a main signal such as a dedicated packet processing hardware circuit. It is composed of a line card (Linea) (1a) having an input / output unit, a Forwarding Engine (FE) card (1b) having a route search processing unit, and a switch fabric (1d) using an N × N crossbar system.
[0041]
The switch fabric (1d) includes a crossbar switch (Switch Data Path (DP)) (1d1) and a connection arbitration circuit (Switch Allocator (SA)) (1d2).
[0042]
DP (1d1) is a switch having an N input port × N output port configuration by a crossbar system.
[0043]
The connection arbitration circuit SA (1d2) sends N switch switches (1d1) to the crossbar switch DP (1d1) every unit switch cycle based on switch connection requests from all function cards (up to N cards) or packet reception rejection notification. × N The function of determining the connection of the switching port is provided.
[0044]
The function card separates a forwarding processing unit emphasizing high-speed performance from a routing processing unit emphasizing diversity, and performs forwarding processing (so-called route search processing) using a forwarding table to a forwarding engine (FE) (1b). Do it. The network processor card (1c) performs routing processing (routing table creation processing) by using the routing table in the network processor (NP) (1c).
[0045]
The switch interface unit of the function card (FE or line card: 1a, 1b) has a switch interface unit as a common interface with a switch fabric (Switch Data Path (DP) and Switch Allocator (SA)). The switch interface unit calls a block provided for an input interface (to receive a packet from the outside) a TSU (To Switch Unit) (1a2), and a block provided for an output interface (transmits a packet to the outside) FSU (From Switch Unit) ( 1a3).
[0046]
FIG. 2 is a block diagram showing a main configuration of the switch interface unit applied in the present invention. The TSU (1a2) is provided with a virtual output queue (VOQ) for every destination port (To # 1-To # N), and is a HOL (Head of Line) which is a weak point of the conventional crossbar switch. 3.) A non-blocking switch interface that solves the problem of switch efficiency reduction due to the blocking phenomenon and has theoretically 100% switch efficiency.
[0047]
In FIG. 2, a function card (1a) has a route request (RR) for receiving a packet from a main signal input / output processing unit by the TSU and a payload memory temporarily stored in a payload memory, and the destination of the header is To. #N is output from each port to the crossbar switch for route setting. In the function card (1a), the payload portion is temporarily stored in the payload memory from each packet received at each port from the crossbar switch (1d), the destination of the header portion is sequentially set to Fm # n, and the main signal is transmitted. Output to the input / output processing unit (1a1). The update header (UH) is output to the TSU having the route request RR.
[0048]
The transfer unit in each switch cycle is a fixed length (this unit is called a Page), and switching can be performed efficiently and with low delay regardless of the packet length.
[0049]
The FSU (1a3) also has a virtual input queue (Virtual Input Queueing) for every source port corresponding to the TSU, and has a function of reconstructing the Page defined as the switching unit into the original packet.
[0050]
The concept of virtual output queue management on the TSU side provided for every destination port (To # 1-To # N) will be described with reference to FIG. For each port, each virtual output queue is provided with a dedicated area for each destination card of # 1, # 2,..., #N, counts the number of pages stored in the corresponding queue, and stores page data. Manages a linked list of memory addresses. In the above management, when the page storage area of the corresponding queue reaches the storage capacity threshold, the packet corresponding to the page is discarded as a discard queue.
[0051]
In FIG. 3, High and Low indicate queuing priorities in the VOQ (TSU) unit. In accordance with the priority value contained in the Route Request (RR) object, it is determined whether to put the RR in the High / Low queue of the slot number queue of the designated FE or in the discard queue. Packets stored in the High queue are absolutely controlled in priority over packets stored in the Low queue. Therefore, the processing on the packet stored in the Low queue is permitted only when the packet is not stored in the High queue.
[0052]
As shown in FIG. 5, when the main signal input / output unit (1a1) of the line card (1a) assumes, for example, POS (PPP over SONET) as the interface type, the PHY framer (5a) and the PPP frame termination unit (5b) ), An MPLS engine (reception side) (5c), a TSU control unit (5d), an MPLS engine (transmission side) (5f), and an FSU control unit (5e).
[0053]
The PHY framer (5a) accommodates a SONET / SDH interface of each speed, has a function of terminating a SONET / SDH frame, and a function of terminating an HDLC frame mapped on the SONET / SDH payload.
[0054]
The PPP (Point-to-Point Protocol) frame terminating unit (5b) has a function of terminating the PPP packet mapped to the information field of the HDLC frame as a process on the receiving side. Specifically, it checks the protocol ID of the PPP header, identifies the IP packet, the labeled packet, and other control packets, and transmits the header information of the IP packet and the labeled packet to the MPLS engine unit (5c). The control packet other than the packet and the labeling packet is transferred to, for example, a CPU (not shown) mounted on the card, and performs processing required by each protocol type. As processing on the transmitting side, a control packet is transmitted to the opposing device side according to the state of the PPP link and the use state of the link in addition to the IP packet and the labeled packet. If a sufficient buffer can be implemented in this block, a function of page-dividing the variable-length packet may be provided.
[0055]
In the MPLS engine (5c) on the receiving side, before being stored in the memory of the TSU (1a2), a packet header specifying destination and communication quality [in the case of an IPv4 packet, an IPv4 header (20 bytes) and its upper layer protocol An arbitrary combination of headers and, in the case of a labeled packet, a route resolution for obtaining the mounting position number and the physical port number of the transfer destination card by referring to each field of [Shim-Header) including a plurality of pieces of label information; Alternatively, the class code resolution (Classfire) to which the packet belongs and the monitoring process (Policy) are performed as MPLS label processing, and mapped to the overhead portion of the main signal packet or the packet information storage cell (according to FIGS. 9A and 9B). , Which will be described later).
[0056]
Each entry to be solved is registered in the memory, and the contents of the entry include a packet flow identifier, a label identifier, value-added information defined by a network policy, and the like. Thus, the service quality to which the packet belongs and the function card number of the transfer destination are derived.
[0057]
The TSU control unit (5d) performs priority control on the switch based on the page data received from the IP packet receiving unit (1a) and the class code corresponding to the packet resolved by the IP-QOS class determining unit (1e). Do.
[0058]
Thereafter, the page data is transferred to the TSU (1a2) of the VOQ control which is the switch interface unit. The configuration of this block has been described with reference to FIG. The page data received via the crossbar switch is stored in the memory of the FSU (1a3). When the reception of all the page data constituting a packet is completed, the VIQ-controlled FSU generates a fixed-length packet information storage cell called "Object" as a virtual processing unit for each packet.
[0059]
The MPLS engine (5f) on the transmitting side fetches the object generated by the FSU (1a3) and stores it in the memory. The left memory is queue-managed for each class code resolved by the MPLS engine (5c) on the receiving side, and is preferentially read out of the memory from the high-priority class object and passed to the FSU control unit (5e). Priority scheduling is performed.
[0060]
The FSU control unit (5e) reads out data in page units from the memory of the FSU based on the received object, reconstructs it into IP packets, and is further encapsulated in a PPP frame by the PPP frame termination unit (5b).
[0061]
FIG. 6 is an explanatory diagram of a main part of the MPLS engine unit [receiving side]. The receiving side MPLS engine unit (5c) includes a latch circuit (6a) for latching each element of the input data at each head position pulse, and an error determination circuit (6b) for determining whether or not each of the latched elements has an error. ), In the case of a labeled packet, a search circuit (6c) for performing label conversion processing, route determination processing, and class determination processing by searching an external memory, or in the case of a non-labeled packet (for an IP packet), receiving Memory access using the header information of the obtained IP packet (a combination of the layer 3 information represented by the IP header and the layer 4 information represented by the TCP / UDP header corresponding to an upper layer thereof) as a search key, A search circuit (6c) for acquiring a class identifier that becomes A policing circuit (6d) for monitoring the flow of the hicks and discarding a packet of the corresponding class when the capacity exceeds the transferable capacity, or performing control for lowering the transfer priority, retiming each resolved element, and It comprises a retiming circuit (6e) for outputting to the TSU control section (5d), which is a stage block, and a monitoring control circuit (6f) for interfacing with the network processor NP.
[0062]
The search circuit (6c) is connected to a plurality of CAMs (Contents Addressable Memory) and the SRAM, and sets condition information (rule list) on the CAM based on what rule the packet is classified into based on the CAM. Operation information (action list) determined by the rule list is set in the SRAM.
[0063]
The network processor NP has a function of reading the currently operating rule list in the device from the CAM via the monitoring control circuit (6f), a function of reading the currently operating action list from the SRAM, and operating / non-operating the rule list / action list. It has a function to switch operation.
[0064]
An operation example of the embodiment of the present invention will be described. In order to simplify the description, the description will be given along a specific example (FIG. 4: device function explanatory diagram).
[0065]
FIG. 4 is an explanatory diagram showing the functions of the device shown in FIG. 1 to which the present invention is applied, and the procedure for transferring an IP packet in the device will be described with reference to FIG.
[0066]
(1) Receiving phase
The IP packet input from the line of the line card is divided into pages, and the left is stored in the payload memory of the TSU.
[0067]
(2) Route request phase (Route request phase)
In order to resolve the destination of the IP packet stored in the payload memory of the TSU, the line card (Line Card) is used to resolve the destination of the IP packet from the memory of the TSU. Only the above is taken out, and the above is transferred to the Forwarding Engine via a switch as a Route Request Page. The Forwarding Engine saves the Route Request Page received from the Line Card in the payload memory of the FSU.
[0068]
(3) Forwarding phase
The Forwarding Engine reads the Route Request Page from the memory of the FSU, resolves the above in the route search processing unit (Forwarding processing unit), resolves the Line Card that is the destination of the IP packet, and further updates the Updated Request Page in which the Route Request Page is changed. Is created and stored in the memory of the TSU.
[0069]
(4) Updated header phase
The Forwarding Engine retrieves the Updated Header Page from the payload memory of the TSU, and returns the above to the Line Card that transmitted the Route Request Page. After the Line Card temporarily stores the received Updated Header Page in the payload memory of the FSU, the Line Card transfers the Updated Header Page from the memory of the FSU to the memory of the TSU.
[0070]
(5) Page transfer phase
The Line Card transmits all the pages of the IP packet stored in the TSU payload memory to the destination Line Card. At this time, the top page of the IP packet is transferred by replacing it with the updated header page returned from the forwarding engine. The Line Card of the destination that has received the Page temporarily stores this Page in the payload memory of the FSU.
[0071]
(6) Sending phase
The Line Card that has received the entire packet reads the Page from the payload memory of the FSU, changes the packet to a packet corresponding to the line, and transmits the packet.
[0072]
In the transfer procedure described above, the IP packet performs the transfer procedure of (1) ⇒ (2) ⇒ (3) ⇒ (4) ⇒ (5) ⇒ (6), while the labeled packet is (2), (3), and (4), which are transfer phases to the FE, are subjected to transfer processing so as to be cut-through.
[0073]
FIG. 7 is a diagram showing an MPLS resolution entry correspondence for explaining the operation in the search circuit (6c).
[0074]
In order to simplify the explanation, the route solution and the label process are grouped (to be referred to as "collectively"), and the route resolve process and the class solution separate the referenced elements.
[0075]
In the route resolution processing, the route information and the output label value (for example, 20 bits) are resolved from the input label value (for example, 20 bits) or the set information of the input label value and the input port number. The table reference described later can be realized by, for example, a search process for the CAM.
[0076]
The route information to be resolved includes an output label value to be attached to the output labeled packet, an action code for specifying insertion / conversion / deletion of the label, a destination port number required for switching in the device, and a copy destination. Copy information indicating the destination port number is included.
[0077]
The “class information” that defines the quality of service information in the network can be obtained by reading a memory using an EXP (Experimental Use) field contained in the header of the labeled packet as a key (address), and a memory having a very small capacity. It can be realized by deployment.
[0078]
Specifically, the labeled packet is a pair of the MPLS (old) header (32 bits) and the input port number, and the MPLS (old) header is the MPLS (old) label 20 bits and the input port number. As a pair, processing is divided into label processing and path resolution processing, and MPLS (new) 20 bits and an action code are output by the label processing. From the path resolution processing, the packet type, destination port number, copy information, and discard are output. It is divided into information and output. The input port number is a pair of the input port number and the Exp3 bits, one of which performs DS-PHB code resolution processing, outputs class information, and the other has output (Exp) 3 bits. In addition, when Per-Interface-Label-Space is not supported, the information (Port) of the input port number is not required in the label processing and the route resolution processing.
[0079]
FIGS. 12A to 12D show details of a table configuration (Key & Contents) for realizing the correspondence of the MPLS solution entry (receiving unit) shown in FIG. As described above, a plurality of CAMs (Contents Addressable Memory) and SRAMs are connected to the MPLS engine (5c), and condition information (rule list) indicating what rules are used to classify the packets based on the rules is provided. Operation information (action list) set in the CAM and determined by the rule list on the left is set in the SRAM. The hit address obtained by the CAM search is used as an address pointer to the SRAM, and an action (or behavior) list for the packet is finally obtained.
[0080]
The class solution processing may take several forms depending on the operation, and may be uniquely determined only by the EXP information in the packet header, or may be determined by a combination of the label and the EXP. Note that there may be operation modes such as a method of performing the association with the discarding process, a method of performing the class discrimination only with the label, and the method of executing the discarding process only with the EXP. In any case, a small amount of memory may be provided, or a combination of label information and EXP may be registered in advance as a CAM entry.
[0081]
FIG. 8 shows a time chart of the MPLS engine (reception side) section shown in FIG. 6, and this operation will be described in detail. FIG. 8 illustrates clock signals of a latch circuit 6a, a search circuit 6c, a retiming circuit 6e, and the like having each CPU, a head position pulse of a packet, and a timing pulse output from the latch circuit 6a.
[0082]
The latch circuit (6a) latches a header portion of the IP packet or the labeled packet with a head position pulse or a timing pulse generated inside the circuit. [Fig. 8-1]
In the case of a labeled packet, the data to be latched is an input label value, an EXP value, an input port number, and a packet length. The packet length may be reduced by adding the overhead in the device and then normalizing the packet length in page units to simplify the management, thereby reducing the circuit scale. [Fig. 8-2]
The search circuit (6c) gives the latched input label value or a set of the input label value and the input port number to the CAM as search data [FIG. 8-3], performs a search process (of a rule list), and performs the CAM. The hit address is obtained [FIG. 8-4], the SRAM is accessed (read processing) using the obtained hit address as a read address, and an action list is obtained [FIG. 8-5]. The action list includes an output label value, an operation code, an output port number, header update information, filtering information, and the like. [Fig. 8-6]
The class update information after the policing process [FIG. 8-7] and the determination result information (discard / non-discard) [FIG. 8-8] are output as the output information (5c # out) after the retiming process together with the above-mentioned action list. Output to the next-stage TSU controller (5d) together with the output frame pulse. [Fig. 8-9]
9A and 9B show a mapping process in the TSU control unit (5d) that has received the action list information (5c # out) solved by the MPLS engine unit (5c). FIG. 9A is a mapping example of a labeled packet, and FIG. 9B is a mapping example of an IP packet.
[0083]
In the present invention, the MPLS engine receiving side (5c) shown in FIG. 5 is connected to a CAM and an SRAM as an external memory. Condition information is mainly described in the CAM, and action information is described in the SRAM. If the received packet is an IP packet, the MPLS engine receiving side (5c) searches the CAM and the SRAM based on the IP packet, and determines a queue priority, a discard / pass process (filtering) for the IP packet. , SW priority / non-priority processing, Difserv DSCP value assignment, and the like.
[0084]
On the other hand, when the received packet is a labeled packet, the CAM and the SRAM are searched based on the labeled packet, and a processing action (SWAP or POP processing of the label) for the labeled packet is added. As in the case of the IP packet, processes such as queue priority, discard / pass processing (filtering), SW priority / non-priority processing, and Diffserv DSCP value assignment are derived.
[0085]
The action list is a list of action information for an IP packet or a labeled packet resolved by the MSLP engine receiving side (5c). Further, the processing executed by the TSU control block (5d) and actually reflected in the packet is the action map list mapping.
[0086]
In FIG. 9A, for simplicity of description, only label SWAP processing among label processing (PUSH / SWAP / POP) is illustrated, but the same processing is applied to label POP / PUSH processing. In FIG. 9A, the action list output by the receiving side of the MPLS engine unit (5c) is the three lines indicated by Word0-2 in the upper left, and the label code of the packet labeled in Word2 is attached. The mapping processing in the TSU control unit (5d) is converted so as to show an example of the first Page format of the lower left labeled packet (for one sheet). At this time, the arrangement of each code is shifted and formatted so that the conversion destination is indicated by a thin line.
[0087]
In FIG. 9B, as an example of an action list mapping at the time of an IP packet, an IP packet without a labeling code, which is an input packet of the TSU control unit (5d) in the upper part of the figure, is converted into a format shown in the lower left part. In particular, the movement point of Checksum is greatly shifted. Also, the lower right side is a detailed explanatory diagram of 0 to 17 bits, where the number of pages of the packet and the number of octets of the packet are inserted.
[0088]
Only the differences (change points) between FIG. 9A and FIG. 9B are shown below. In addition, the description of each abbreviation and the meaning content is as showing in FIG. For example, Type indicates the type (type) of the object, and includes types such as FE transfer, cut-through transfer, and discard instruction. Er indicates Error, indicates an error, and Route indicates Route.
[0089]
Next, in FIGS. 9A and 9B,
(A) The difference at the time of head page mapping is as follows.
(1) Move Qpri (Qos Priority: class identifier).
(2) Added Length (Packet Length: specifies the data length of the packet).
(3) Change the LCI field to a Dtag number.
(4) Card is changed to the Mcast field. Value is fixed
(B) The difference at the time of mapping in object generation is as follows.
(1) Changed the Type field to 01 ---> 11.
(2) Set route to the slot number of the implementation of the destination Line Card.
(3) count is a fixed value of 0001
As described above, in the TSU control unit (5d), the insertion point differs depending on the type of the input packet.
[0090]
【The invention's effect】
According to the present invention described above, the switch interface unit and the switch fabric follow the architecture of the conventional router, and even if IP packets and labeled packets are mixed, packet identification means that can handle both of them, Since the packet distributing means is provided, the conventional router can be provided with a labeled packet handling function at low cost.
[0091]
In addition, the labeled packet has a means for performing route resolution by a dedicated engine in the line card, and the IP packet has means for sorting the packet to be FE-transferred. Since a means for packet handling (packet transfer) is provided, handling of a labeled packet can be executed at high speed.
[0092]
In addition, since there is provided a means for reducing transfer via a switch (conventionally, transfer of route-request / updated-header occurs between an FE card and a line card) due to a route search, a switch is provided. Bandwidth resources can be used efficiently and transfer performance can be improved.
[0093]
In addition, the present invention is a communication device having means for controlling a labeled packet mixed with an IP packet in accordance with a quality of service (QOS), so that an IP packet switch function and an ATM cross connect function are provided. When the function architecture of the conventional router having the above is followed and the function of the conventional router is extended to an LSR (Label Switching Router), the label can be transferred flexibly (seamless), and realizes packet transfer excellent in versatility. And a communication device.
[Brief description of the drawings]
FIG. 1 is a basic overall configuration diagram of the present invention.
FIG. 2 is an explanatory diagram of a main part of a TSU / FSU of the present invention.
FIG. 3 is a model diagram of virtual output queue management of the present invention.
FIG. 4 is an intra-device transfer flowchart of a main part of the present invention.
FIG. 5 is a configuration diagram of a line card of the present invention.
FIG. 6 is an internal block diagram of an MPLS engine [receiving side] section of the present invention.
FIG. 7 is an explanatory diagram corresponding to a solution entry in the MPLS engine [receiving unit] of the present invention.
8 is a timing chart of the block diagram shown in FIG. 6 of the present invention.
FIG. 9A is a diagram illustrating a mapping in the TSU control unit (5d) of the present invention, in the case of a labeled packet.
FIG. 9B is a diagram illustrating the mapping in the TSU control unit (5d) of the present invention, in the case of an IP packet.
FIG. 10 shows a transfer mechanism in the MPLS domain of the present invention and the conventional example.
FIG. 11 is a network model of the present invention and a conventional MPLS-DiffServ.
FIG. 12A is a table configuration example of an MPLS engine [receiving side] according to the present invention.
FIG. 12B is a table configuration example of an MPLS engine [receiving side] according to the present invention.
FIG. 12C is a table configuration example of an MPLS engine [receiving side] according to the present invention.
FIG. 12D is a table configuration example of an MPLS engine [receiving side] according to the present invention.
FIG. 12E is a table configuration example of an MPLS engine [receiving side] according to the present invention.
FIG. 13A is a table of abbreviations, meanings, and explanations used in the present invention.
FIG. 13B is a table of abbreviations, meanings, and explanations used in the present invention.
[Explanation of symbols]
1a Function card line card
1a1 Main signal input / output unit
1a2 TSU
1a3 FSU
1b Function card forwarding engine card (FE)
1c Network processor card
1c1 Protocol processing unit
1d switch fabric
1d1 N × N crossbar switch
1d2 connection arbitration circuit (allocator)
5a Physical layer (PHY) framer
5b PPP frame termination
5c MPLS engine receiving unit
5d TSU control unit
5e FSU control unit
5f MPLS engine transmission unit
6a Pulser latch circuit
6b Checker error determination circuit
6c Searcher search circuit
6d policer policing circuit
6e Retiming circuit
6f monitoring control circuit
10a Entrance router (edge router)
10b Core router (intermediate router)
10c Exit router (edge router)

Claims (11)

  1. What is claimed is: 1. A communication apparatus having means for controlling a labeled packet mixed with an IP packet according to a quality of service (QOS), and an MPLS solution for resolving transfer destination information and class information from a label indicating a destination. A circuit, a path detection circuit, a flow detection circuit for performing label processing and class resolution, and a problem of throughput degradation due to the FE transfer by transferring only unresolvable packets or special packets (Optional Header) to a FE (Forwarding Engine). A labeling packet communication device comprising means for avoiding the problem.
  2. Means for performing cut-through transfer of the labeled packet in the apparatus, performing transfer of the IP packet via the FE, and reassembling the IP packet and the labeled packet in a virtual input queue (VIQ) unit The labeled packet communication device according to claim 1, comprising:
  3. Check the protocol ID of the input packet header of the IP packet or the labeled packet, identify the IP packet, the labeled packet, and other control packets, the IP packet and the labeled packet are headers of each packet. A dedicated engine unit for receiving information; a control device (CPU) for receiving control packets other than the IP packet and the labeling packet; and a distribution unit for performing processing required by a plurality of protocol types. 3. The labeled packet communication device according to claim 1, wherein
  4. At the stage before being stored in the virtual output queue, referring to each field divided for each block of the packet header specifying the destination and the communication quality, route resolution for obtaining the mounting position number and the physical port number of the transfer destination card, 4. An apparatus according to claim 1, further comprising an overhead section for solving a class code to which the packet belongs and processing a packet including a main signal, and / or means for mapping the packet to a packet information storage cell. A labeled packet communication device as described.
  5. Each entry to be solved is registered in a memory, and the contents of the entry include a packet flow identifier, a label identifier, and value-added information defined by a network policy. 5. The labeled packet communication apparatus according to claim 1, further comprising means for deriving a service quality to which the packet belongs and a transfer destination function card number.
  6. A labeled packet transfer processing method comprising means for controlling a labeled packet mixed with an IP packet in accordance with a network of quality of service (QOS),
    The destination information and the class information are resolved from the label indicating the destination by the MPLS resolution circuit, the route resolution, the label processing and the class resolution are performed by the flow detection circuit, and only the unresolvable packet or special packet (Option Header) is FE ( Forwarding Engine) to avoid the problem of throughput degradation caused by the FE transfer.
  7. The labeled packet is cut-through transferred in the device, the IP packet is transferred via the FE, and reassembled into the IP packet and the labeled packet in a virtual input queue (VIQ) unit. 7. The labeled packet transfer processing method according to claim 6, wherein:
  8. A dedicated engine unit checks a protocol ID of an input packet header of the IP packet or the labeled packet, identifies the IP packet, the labeled packet, and other control packets, and identifies the IP packet and the labeled packet. 8. The labeling method according to claim 6, further comprising: receiving header information of each packet, receiving control packets other than the IP packet and the labeling packet, and performing processing required by a plurality of protocol types. Packet transfer processing method.
  9. Before storing in the virtual output queue, route resolution for obtaining the mounting position number and the physical port number of the transfer destination card by referring to each field divided for each block of the packet header specifying the destination and the communication quality 9. The method according to claim 8, wherein a class code to which the IP packet and the labeled packet belong is solved and mapped to a packet information storage cell.
  10. Each input packet to be solved is registered in the memory, and the contents of the input entry include a packet flow identifier, a label identifier, and value-added information defined by a network policy. 10. The labeled packet transfer processing method according to claim 6, wherein the service quality to which the labeled packet belongs and the transfer destination function card number are derived.
  11. In a packet communication device for processing an IP packet of an IP network and a labeled packet that has been identified and labeled with a multilayer class,
    A line card for transmitting and receiving a plurality of packets, a switch device connected to the line card for switching to a destination, and a forwarding engine card connected to the switch device,
    After the IP packet is stored in the memory in the line card, a route of a header portion of the IP packet is set in the route search processing unit in the forwarding engine card via the switch device, and the set route information is The set path information is converted from the forwarding engine card via the switch device to the header portion of the IP packet and output to the destination line card,
    The packet communication, wherein the labeled packet is stored in a memory in the line card, cuts through the forwarding engine card via the switch device for the label, and is output to the destination line card. apparatus.
JP2000245841A 2000-08-14 2000-08-14 Labeled packet transfer processing method and communication device therefor Expired - Fee Related JP3543953B2 (en)

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