JP3533127B2 - Asynchronous signal detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous signal detection circuit for detecting a reset signal of a computer.

[0002]

2. Description of the Related Art In a system in which a computer is connected to an external host computer and controlled by the host computer, when the host computer sends a reset signal, the computer connected to the host computer resets from the host computer. Detects when a signal becomes active and detects its own CPU
To generate an interrupt and perform the required operation.
An asynchronous signal detection circuit is used to detect such a reset signal, and the asynchronous signal detection circuit detects when the reset signal becomes active for several hundreds ns or more, for example.
The detection signal is output assuming that the reset signal is detected.

FIG. 7 is a circuit diagram showing an example of a conventional asynchronous signal detection circuit of this type, and FIG. 8 is a timing chart for explaining the operation of the asynchronous signal detection circuit shown in FIG. As shown in FIG. 7, the conventional asynchronous signal detection circuit 5
0 is a D flip-flop circuit (DFF) 21 to 30,
And an RS flip-flop circuit (RSFF) 31, and operates in synchronization with the clock signal CLK. The detected signal IN is DFF asynchronously with the clock signal CLK input to each flip-flop circuit.
21 and the detected signal I
As shown in FIG. 8, when N becomes active (high level in this example), it is synchronized by the DFF 21 and the DFF 2
The signal S11 is output from the Q output terminal of 1. Signal S1
1 is supplied to the DFF 22 and the DFF 28.

The signal S11 is re-cut by the clock signal CLK in the DFF 22, taken in from the D input terminal of the DFF 22 at the timing of the clock signal CLK, held, and output from the Q output terminal with a delay of one clock cycle. It is input to the next DFF 23. In the same way, the re-switching by CLK is performed up to the DFF 25, each flip-flop circuit delays by one clock cycle, and the Q of the DFF 25 is delayed.
The signal S12 is output from the output terminal. Although the four stages of DFFs 22 to 25 are connected in series in this example, the number of the flip-flop circuits is increased or decreased according to the duration of the active state of the detected signal IN.

On the other hand, the signal S11 input to the DFF 28
Are re-turned by the clock signal CLK, delayed by one clock period, and input to the D input terminal of the DFF 29. Then, it is re-cut by the clock signal CLK in the DFF 29, further delayed by one clock cycle, and
The signal S13 is output from the Q output terminal of No. 9.

Output signal S12 of DFF25 and DFF29
When both output signals S13 of
The signal S14, which is the output signal of No. 2, becomes active, and as a result, the DFF 26 is activated at the timing of the clock signal CLK.
Is set, and the active signal S is output from its Q output terminal.
15 is output. The signal S15 is re-turned by the clock signal CLK by the DFF 27 to become the signal S16, and the logic circuit 33 generates the detection signal OUT1 based on the signals S15 and S16. Further, when the detection signal OUT1 is output, the RSFF 31 is set, and the RSFF 31 outputs the signal S17 from the Q output terminal.
When the detected signal IN becomes inactive after UT1 is output, the signal S18 becomes active, the DFF 30 is set by the clock signal CLK, and the detection signal OU is set.
T2 is output.

When the signal OUT2 is output, the RSFF31
Is reset, so D is generated by the next clock signal CLK.
The FF 30 is reset, and as a result, the detection signal OUT2
Is a one-shot pulse. Here, the detected signal IN
When the period from when the signal is activated to when the signal is inactive is short and equal to or shorter than a certain time, the active signal input as the detected signal is regarded as noise, and the detection signals OUT1 and OUT2 are detected. Is not output.

[0008]

However, such a conventional asynchronous signal detection circuit 50 has the following problems. The first problem is that it consumes a large amount of power and consumes power even in the standby mode. That is, many computers enter a standby mode to suppress power consumption and stop the operation of each unit when it is not necessary to operate. However, even in the standby mode, it operates by supplying power to necessary parts. For example, when the above-mentioned reset signal is input from an external host computer, it detects it and operates properly. Therefore, the reset signal detection circuit 50 and related circuits are operated even in the standby mode.

Here, the asynchronous signal detection circuit 50 includes 11 flip-flop circuits, and the clock signal CLK is supplied to all of these flip-flop circuits. Therefore, a driver circuit (not shown) having a sufficient current output is used to supply the clock signal CLK, and as a result, even when the computer is in the standby mode, the clock signal CLK for the asynchronous signal detection circuit is used. As a result, a very large amount of power is consumed to supply the electricity.

The second problem is that the detection of the time during which the detected signal IN is active depends on the cycle of the clock signal. That is, the asynchronous signal detection circuit 50
Then, as understood from the above description, the detection signal is output when a predetermined number of clock signals are input during the period in which the detected signal IN is in the active state. Therefore, if the cycle of the clock signal CLK is set to be short due to a design change, for example, the detected signal IN will be detected even if the time during which the clock signal CLK is active is shorter. Therefore, when the cycle of the clock signal CLK changes, the configuration of the asynchronous signal detection circuit 50 also needs to be changed. Further, as another conventional example, it may be considered that the time during which the detected signal is active is detected by using an analog delay circuit, but the analog delay circuit generally has a large occupied area and delay time. There is a drawback that the accuracy of is low.

The present invention has been made to solve such a problem, and an object thereof is to reduce power consumption, detect a signal to be detected without depending on a cycle of a clock signal, and have high accuracy. An object of the present invention is to provide an asynchronous signal detection circuit capable of detecting a detected signal.

[0012]

In order to achieve the above object, the present invention is an asynchronous signal detection circuit which outputs a detection signal when the detection signal is active for a certain period of time or longer, and which comprises: A first pulse generation circuit that outputs a one-shot pulse signal when a detection signal becomes active, a first delay circuit, and an output signal of any one of the first pulse generation circuit and the first delay circuit. A selector circuit for selecting and inputting to the first delay circuit, and a first selector circuit for outputting the pulse signal when the first delay circuit outputs the pulse signal while the detected signal is active.
Of the pulse signals output from the first logic circuit and the first logic circuit, the counting operation signal is output when one or more pulse signals are being counted, and the counting is completed when a predetermined number of pulse signals are counted. An asynchronous binary counter circuit that outputs a signal, stops the output of the counting operation signal, and is reset by a reset signal; and a second pulse that outputs a one-shot pulse signal when the detected signal becomes inactive A generation circuit, a second delay circuit that receives the one-shot pulse signal output by the second pulse generation circuit, and a pulse signal output by the second delay circuit when the detected signal is inactive. And a second logic circuit which outputs the same pulse signal to the asynchronous binary counter circuit as the reset signal when When the asynchronous binary counter circuit outputs the counting operation signal, the selector circuit selects the pulse signal output by the first delay circuit and inputs the pulse signal to the first delay circuit, and the detection signal is , Is generated based on the count completion signal of the asynchronous binary counter circuit.

In the asynchronous signal detection circuit of the present invention, when the detected signal becomes active, the first pulse generation circuit outputs a one-shot pulse signal, and the first delay circuit receives this pulse signal through the selector circuit, Delay and output. Then, since the pulse signal output from the first delay circuit is input again to the first delay circuit through the selector circuit, the pulse signal is continuously input from the first delay circuit at a cycle determined by the delay time in the first delay circuit. A pulse signal is output to. This pulse signal is counted by the asynchronous binary counter circuit, and the asynchronous binary counter circuit outputs a count completion signal when counting a predetermined number of pulse signals, and a detection signal is generated based on this count completion signal.

On the other hand, when the detected signal becomes inactive, the second pulse generation circuit outputs the one-shot pulse signal and supplies it to the second delay circuit, and as a result, the second logic circuit asynchronously outputs the reset signal. Since it outputs to the binary counter circuit, the counter circuit is reset. Therefore, when the detected signal is active for a short period of time and the detected signal becomes inactive and the second logic circuit outputs the reset signal before the asynchronous binary counter circuit outputs the count completion signal, The asynchronous binary counter circuit is reset and does not output the count completion signal. That is, the asynchronous signal detection circuit of the present invention is
Basically, the detection signal is output when the detected signal becomes active for a time longer than the time determined by the delay time of the first delay circuit and the count number of the asynchronous binary counter circuit.

The asynchronous signal detection circuit of the present invention is
Since no clock signal is required for the operation, it is not necessary to provide a driver circuit with large power consumption to supply the clock signal unlike the conventional asynchronous signal detection circuit. Therefore, the power consumption can be significantly reduced.
In addition, the time during which the detected signal is active is determined based on the time basically determined by the delay time of the first delay circuit and the count number of the asynchronous binary counter circuit as described above. The detected signal can be detected independently of the clock signal cycle, and there is no need to change the configuration of the asynchronous signal detection circuit even if the clock signal cycle used in the device incorporating the asynchronous signal detection circuit is changed. .

Further, even if the first and second delay circuits are composed of analog delay circuits, the delay time of each analog delay circuit may be short, so that the occupied area is small and it is advantageous for downsizing of the apparatus. Is. Further, if the first and second delay circuits are configured by the self-propelled FIFO circuit, the accuracy of the delay time can be improved and the delay time is about the duration of the active state of the detected signal as in the conventional case. The detection accuracy can be improved as compared with the case where an analog delay circuit is used.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. 1 is a circuit diagram showing an example of an asynchronous signal detection circuit according to the present invention, FIG. 2 is a circuit diagram showing in detail a self-propelled FIFO circuit constituting the asynchronous signal detection circuit of FIG. 1, and FIG. 3 is an asynchronous signal detection of FIG. FIG. 4 is a circuit diagram showing in detail an asynchronous binary counter circuit that constitutes the circuit.
3 is a timing chart for explaining the operation of the asynchronous signal detection circuit shown in FIG.

As shown in FIG. 1, the asynchronous signal detection circuit 100 of the present embodiment has a first pulse generation circuit 1,
Second pulse generating circuit 5, third pulse generating circuit 7, first free-running FIFO circuit 3, second free-running FIFO circuit 6, asynchronous binary counter circuit 4 (counter circuit 4), selector circuit 2 , The first to third logic circuits 8,
It is configured to include 10 and 12.

The first pulse generation circuit 1 outputs a one-shot pulse signal when the detected signal IN, which is a reset signal of a computer, for example, becomes active (that is, active level). The selector circuit 2 is
Based on the counting operation signal S4 from the counter circuit 4, the first pulse generating circuit 1 and the first self-propelled FI.
One of the output signals of the FO circuit 3 is selected and input to the first self-propelled FIFO circuit 3. Specifically, when the counter circuit 4 outputs the counting operation signal S4, the selector circuit 2 selects the pulse signal output by the first self-propelled FIFO circuit 3 and outputs it to the first self-propelled FIFO circuit 3. input.

The first logic circuit 8 outputs the pulse signal when the first self-propelled FIFO circuit 3 outputs the pulse signal while the detected signal is active. Then, the counter circuit 4 counts the pulse signals output from the first logic circuit 8, outputs the counting operation signal S4 when counting one or more pulse signals, and counts a predetermined number of pulse signals. At this time, the count completion signal S5 is output, the output of the counting operation signal S4 is stopped, and the reset signal S7 resets.

On the other hand, the second pulse generating circuit 5 outputs the one-shot pulse signal S6 when the detected signal becomes inactive, and the second self-propelled FIFO circuit 6 outputs the second pulse generating circuit. The one-shot pulse signal S6 output by the signal 5 is delayed and output. Then, the second logic circuit 10 outputs the pulse signal to the counter circuit 4 as the reset signal S7 when the second self-propelled FIFO circuit 6 outputs the pulse signal when the detected signal is inactive. The third pulse generation circuit 7 detects the detection signal OUT1 when the counter circuit 4 outputs the count completion signal S5.
To output a one-shot pulse signal. Also, the third
The logic circuit 12 outputs the detection signal OUT2 when the second logic circuit 10 outputs the pulse signal while the counter circuit 4 outputs the count completion signal S5.

Here, the first self-propelled FIFO circuit 3 will be described in detail. As shown in FIG. 2, the first self-propelled FIFO circuit 3 includes a FSET cell 5 which is a storage element.
1, FLAG cells 52-54, and FRST cell 5
5 and a delay circuit 56. FSE
When the active pulse signal S2 is input from the selector circuit 2 to the WR input terminal, the T cell 51 takes in and holds the pulse signal S2 and outputs it from the Q output terminal. FSET cell 5
The output signal of 1 is input to the D input terminal of the FLAG cell 52, and the FLAG cell 52 takes in this input signal, holds it, and outputs it from the Q output terminal to the FLAG cell 53 of the next stage. At this time, the FLAG cell 52 simultaneously sends a clear signal from the CLRO output terminal to the CLR of the previous FSET cell 51.
Output to I terminal. When the clear signal is input from the next stage, the FSET cell 51 clears the held signal, and therefore also the signal output from the Q output terminal.

Next, the FLAG cells 53 and 54 are FLAG cells.
It is connected to the cell 52 in series and operates similarly to the FLAG cell 52. It should be noted that in this embodiment, the FLAG having three stages is used.
Although the cells 52 to 54 are used, this number of stages is an example, and the time during which the detected signal IN remains in the active state,
The number may be increased or decreased according to the count number of the counter circuit 4.

As shown in FIG. 2, the signal output from the Q output terminal of the FLAG cell 54 is supplied to the FRST cell 55 and the delay circuit 56, and the delay circuit 56 outputs the output signal of the first self-propelled type. The signal is output as the output signal S3 of the FIFO circuit 3 and simultaneously output to the RD input terminal of the FRST cell 55.

The FRST cell 55 receives CL when an active signal is input to both the D input terminal and the RD input terminal.
A clear signal is output from the RO output terminal, and FLAG of the previous stage is output.
The FLAG cell 5 is supplied to the CLRI input terminal of the cell 54.
Clear 4 Although the delay circuit 56 may not be provided depending on the delay time of the FLAG cell 55, the FLAG cell 5 can be provided by providing the delay circuit 56.
After 4 outputs an active signal, the time until it is cleared becomes long, and an output signal S3 having a sufficient pulse width can be obtained.

The second self-propelled FIFO circuit 6 has basically the same structure as the first self-propelled FIFO circuit 3. In the case of the second self-propelled FIFO circuit, the output signal S6 of the second pulse generation circuit 5 is input to the FSET cell 51 at the first stage, and the output signal of the delay circuit 56 is output to the second logic circuit 10. become.

Next, the counter circuit 4 will be described in detail. As shown in FIG. 3, the counter circuit 4 includes trigger flip-flop circuits 61 to 64 (TFF), an RS flip-flop circuit 65 (RSFF), and a delay circuit 66.

Trigger flip-flop circuits 61-64
Is a flip-flop circuit that inverts the signal output from the Q output terminal each time the signal input to the clock input terminal 14 becomes active. The trigger flip-flop circuit 61 includes a first self-propelled FIFO.
The output signal of the O circuit 3 is input to the clock input terminal 14 as the count signal S3 through the first logic circuit 8, and the output signal from the inverted Q output terminal of the trigger flip-flop circuit 61 is the trigger flip-flop circuit 62 of the next stage. Is supplied to the clock input terminal 14. The trigger flip-flop circuits 63 and 64 are similarly connected in series to the trigger flip-flop circuit 62, and these four flip-flop circuits constitute the asynchronous binary counter 16.

A signal from the Q output terminal of each trigger flip-flop circuit is input to the logic circuit 18, and when one or a plurality of count signals S3 are input and the binary counter 16 is counting, a logic signal is output. The circuit 18 outputs an active signal. This signal is a logic circuit 20
Through the selector circuit 2 as the counting operation signal S4
Is output to.

A signal from the Q output terminal of each trigger flip-flop circuit is also input to the logic circuit 22. In this embodiment, as an example, signals from the Q output terminals of the trigger flip-flop circuits 62 and 63 are input. When only the signal is active, the logic circuit 22 outputs the active signal R
Output to the S flip-flop circuit. At this time, the RS flip-flop circuit 65 is set and outputs the count completion signal S5. Therefore, in the present embodiment, when the six count signals S3 are input from the state where the binary counter 16 is reset, the count completion signal S
5 is output.

Further, the count completion signal S5 is the logic circuit 2
0 is also input, and the logic circuit 20 stops the output of the counting operation signal S4 when the count completion signal S5 is input. Each trigger flip-flop circuit 61, 6
The reset signal S7 from the second logic circuit 10 is input to 2, 63, and 64, and the RS flip-flop circuit 65 is input.
The reset signal S7 is input to the delay circuit 66 via the delay circuit 66. Therefore, when the reset signal S7 is input, each flip-flop circuit is reset, the count completion signal S5 becomes inactive, and the counting operation signal S4 becomes inactive.

The reset signal S7 is supplied to the RS flip-flop circuit 65 through the delay circuit 66.
After some time has passed since the reset signal S7 was input,
This is because the count completion signal S5 is made inactive, and as a result, the detection signal OUT2 having a sufficient width can be obtained as described later. The delay time in the RS flip-flop circuit 65 and the required detection signal OUT
Depending on the width of 2, the delay circuit 66 may be omitted.

In the present embodiment, the counter circuit 4 outputs the count completion signal S5 when the six count signals S3 are input as described above.
The count number in the counter circuit 4 is the first self-propelled F
It may be increased or decreased according to the delay time of the signal in the IFO circuit 3 and the time during which the detected signal IN remains in the active state.

Next, the operation of the asynchronous signal detection circuit 100 thus constructed will be described. As shown in FIG. 4, when the detected signal IN becomes active (high level in this embodiment) at the timing T1, the first pulse generation circuit 1 generates the one-shot pulse signal S1 at this timing. At this stage, the selector circuit 2 selects the pulse signal S1 and outputs it to the first self-propelled FIFO circuit because the counter circuit 4 does not output the active counting operation signal S4 at this stage. First self-propelled FIF
The O circuit 3 takes in this pulse signal, delays it, and outputs it as the first count signal S3 shown in FIG.

At this time, since the detected signal IN is active, the count signal S3 is input to the counter circuit 4 through the first logic circuit 8, and the counter circuit 4 performs the counting operation. As a result, the counter circuit 4 immediately outputs the active counting operation signal S4.
After that, the selector circuit 2 selects the count signal S3 and inputs it to the first free-running FIFO circuit 3 as the signal S2. By this feedback, the first self-propelled FIFO circuit 3
Outputs the count signal S3 delayed by a time corresponding to the delay time one after another as shown in FIG.

Then, the counter circuit 4 counts the count signal S3, outputs the active count completion signal S5 at the timing T2 when the six count signals S3 are counted, and makes the count operation signal S4 inactive. . As described above, since the count completion signal S5 becomes active, the third logic circuit 12 outputs the detection signal OUT1 at the same timing T2. Further, since the counting operation signal S4 becomes inactive, the selector circuit 2 stops the supply of the counting signal S3 to the first free-running FIFO circuit, and therefore,
The supply of the count signal S3 to the counter circuit 4 is also stopped.

After that, when the detected signal becomes inactive at the timing T3, the second pulse generation circuit 5 outputs the pulse signal S6. At this time, since the detected signal is inactive, the second logic circuit 10 Is the pulse signal S
6 is output to the counter circuit 4 as a reset signal S7. As a result, the counter circuit 4 is reset and the count completion signal S5 becomes inactive with a slight delay by the delay time of the delay circuit 66. Then, the third logic circuit 12
Outputs the detection signal OUT2 as shown in FIG.

Next, the operation when the detected signal IN is active for a short time will be described. FIG. 5 shows the detected signal I
6 is a timing chart for explaining the operation of the asynchronous signal detection circuit 100 when N is active for a short period of time. As shown in FIG. 5, when the detected signal becomes active at the timing T1 as in the case described above, the output of the first self-propelled FIFO circuit 3 is fed back, and the counter circuit 4 starts the counting operation. If the detected signal IN becomes inactive at the timing T4 before the counter circuit 4 counts the six count signals S3, at this timing T4,
The second pulse generation circuit 5 outputs a pulse signal S6.
As a result, after the delay time in the second self-propelled FIFO circuit 6, the reset signal S7 is supplied to the counter circuit 4 and the counter circuit 4 is reset.

As a result, the counter circuit 4 inactivates the counting operation signal S4, so that the selector circuit 2 stops the supply of the counting signal S3 to the first free-running FIFO circuit 3. Therefore, the count signal S3 is not supplied to the counter circuit 4, the operation of the counter circuit 4 is stopped, and the count completion signal S5 is not output, so that the detection signals OUT1 and OUTO2 are not generated.

Next, the operation when noise is superimposed on the detected signal IN will be described. FIG. 6 shows the detected signal I
6 is a timing chart illustrating an operation when noise is superimposed on N. As shown in FIG. 6, if the detected signal becomes active at the timing T1 as in the case described above, the output of the first self-propelled FIFO circuit 3 is fed back, and the counter circuit 4 starts the counting operation. To do. Here, at the timing T5 before the counter circuit 4 counts the six count signals S3, the detected signal I
If noise 24 is superimposed on N, this timing T
5, the second pulse generation circuit 5 outputs the pulse signal S6.
Is output.

However, since the width of the noise 24 is short and the detected signal IN returns to the active state after being delayed by the second free-running FIFO circuit 6, the reset signal S7 is output from the second logic circuit 10. Therefore, the counter circuit 4 is not reset. Therefore, the counter circuit 4 continues the counting operation, and the in-counting signal S4 also remains active. Further, when the detected signal IN returns to the active state at the timing when the noise 24 is eliminated, the first pulse generation circuit 1 outputs the pulse signal S1, but the selector circuit 2 remains in the state in which the count signal S3 is selected. Therefore, the counter circuit 4 continues the counting operation without being affected by the pulse signal S1.

When the counter circuit 4 outputs the count completion signal S5, the detection signal OUT1 is output as in the case described above. In addition, the detection signal O
If pulsed noise is superimposed on the detected signal again at the timing T6 before the detected signal IN becomes inactive after the output of UT1, the second pulse generation circuit 5 outputs the pulse signal at this timing. S6 will be output. However, this signal is the second self-propelled FIF.
At the timing after being delayed by the O circuit 6, the detected signal I
Since N has returned to the active state, the reset signal S7 is not output.

Therefore, although the count completion signal S5 is active, the third logic circuit 12 outputs the detection signal OUT.
It never outputs 2. Further, when the noise 2 is eliminated and the detected signal IN returns to active, the first pulse generation circuit 1 outputs the pulse signal S1 and the selector circuit 2
The count signal S3 is supplied to the first self-propelled FIFO circuit 3 through and the count signal S3 is not selected. Therefore, the count completion signal S5 is not affected.

After that, the detected signal IN changes to the timing T3.
When it becomes inactive, the detection signal OUT2 is output from the third logic circuit 12 as described with reference to FIG. As described above, the asynchronous signal detection circuit 100 of the present embodiment does not require any clock signal in its operation, and thus the conventional asynchronous signal detection circuit 50
As described above, it is not necessary to provide a driver circuit with large power consumption to supply a clock signal. Therefore, the power consumption can be significantly reduced, and for example, the power consumption in the standby mode can be effectively reduced in a computer incorporating the asynchronous signal detection circuit 100.

As will be understood from the above description, the duration of the active detected signal is basically determined by the delay time of the first free-running FIFO circuit 3 and the count number of the asynchronous binary counter circuit 4. Since it is determined based on the reference, it does not depend on the cycle of the clock signal as in the conventional case, and even if the cycle of the clock signal used in the device incorporating the asynchronous signal detection circuit 100 is changed, No configuration changes needed.

Since the delay time of the self-propelled FIFO circuit is more accurate than that of the analog delay circuit, an analog delay circuit having a delay time as long as the duration of the active state of the detected signal is used as in the prior art. The detection accuracy can be improved as compared with the case.

Although the first and second self-propelled FIFO circuits 3 and 6 are used in this embodiment, they may be replaced with analog delay circuits. In that case, since each analog delay circuit may have a short delay time, the occupied area does not become large unlike the conventional case.
For example, the active state of the detected signal is about 400 ns
When the detection signal OUT1 is continuously output, when the conventional analog delay circuit having a long delay time is used, the occupied area of the analog delay circuit is about 1.5 times that in the case of the present embodiment. Becomes Further, in the present embodiment, the duration of the detected state IN of the detected signal IN to be detected falls within a variation of about 380 ns to 420 ns. Time is 250ns-700ns
And the detection accuracy is significantly reduced.

[0048]

As described above, in the asynchronous signal detection circuit of the present invention, the first pulse generation circuit outputs the one-shot pulse signal when the detected signal becomes active, and the first delay circuit outputs the pulse. The signal is received through the selector circuit, delayed, and output. The pulse signal output from the first delay circuit is passed through the selector circuit to the first
The pulse signal is continuously input to the delay circuit of the first delay circuit, so that the first delay circuit continuously outputs the pulse signal at a cycle determined by the delay time of the first delay circuit. This pulse signal is counted by the asynchronous binary counter circuit,
The asynchronous binary counter circuit outputs a count completion signal when counting a predetermined number of pulse signals, and a detection signal is generated based on the count completion signal.

On the other hand, when the detected signal becomes inactive, the second pulse generation circuit outputs the one-shot pulse signal and supplies it to the second delay circuit, and as a result, the second logic circuit asynchronously outputs the reset signal. Since it outputs to the binary counter circuit, the counter circuit is reset. Therefore, when the detected signal is active for a short period of time and the detected signal becomes inactive and the second logic circuit outputs the reset signal before the asynchronous binary counter circuit outputs the count completion signal, The asynchronous binary counter circuit is reset and does not output the count completion signal. That is, the asynchronous signal detection circuit of the present invention is
Basically, the detection signal is output when the detected signal becomes active for a time longer than the time determined by the delay time of the first delay circuit and the count number of the asynchronous binary counter circuit.

The asynchronous signal detection circuit of the present invention is
Since no clock signal is required for the operation, it is not necessary to provide a driver circuit with large power consumption to supply the clock signal unlike the conventional asynchronous signal detection circuit. Therefore, the power consumption can be significantly reduced.
In addition, the time during which the detected signal is active is determined based on the time basically determined by the delay time of the first delay circuit and the count number of the asynchronous binary counter circuit as described above. The detected signal can be detected independently of the clock signal cycle, and there is no need to change the configuration of the asynchronous signal detection circuit even if the clock signal cycle used in the device incorporating the asynchronous signal detection circuit is changed. .

Further, even if the first and second delay circuits are composed of analog delay circuits, each analog delay circuit need only have a short delay time, so that the occupied area is small and it is advantageous for downsizing of the apparatus. Is. Further, if the first and second delay circuits are configured by the self-propelled FIFO circuit, the accuracy of the delay time can be improved and the delay time is about the duration of the active state of the detected signal as in the conventional case. The detection accuracy can be improved as compared with the case where an analog delay circuit is used.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of an asynchronous signal detection circuit according to the present invention.

FIG. 2 is a self-propelled F that constitutes the asynchronous signal detection circuit of FIG.
It is a circuit diagram which shows an IFO circuit in detail.

3 is a circuit diagram showing in detail an asynchronous binary counter circuit which constitutes the asynchronous signal detection circuit of FIG.

FIG. 4 is a timing chart for explaining the operation of the asynchronous signal detection circuit shown in FIG.

FIG. 5 is a timing chart for explaining the operation of the asynchronous signal detection circuit when the detected signal IN is active for a short time.

FIG. 6 is a timing chart explaining an operation when noise is superimposed on the detected signal IN.

FIG. 7 is a circuit diagram showing an example of a conventional asynchronous signal detection circuit.

8 is a timing chart for explaining the operation of the asynchronous signal detection circuit shown in FIG.

[Explanation of symbols]

1 ... First pulse generation circuit, 2 ... Selector circuit, 3
...... First self-propelled FIFO circuit, S3 ... Count signal, 4 ... Asynchronous binary counter circuit (counter circuit), 4S ... Counting operation signal, 5 ... Second pulse generation circuit, S5 ... Count complete signal, 6 ... Second self-propelled FIFO circuit, 7 ... Third pulse generation circuit, S
7 ... Reset signal, 8 ... First logic circuit, 10 ...
Second logic circuit, 12 ... Third logic circuit, 14 ... Clock input terminal, 16 ... Binary counter, 18 ...
Logic circuit, 20 ... Logic circuit, 22 ... Logic circuit, 24
…… Noise, 51 …… FSET cell, 52 …… FLAG
Cell, 53 ... FLAG cell, 54 ... FLAG cell,
55 ... FRST cell, 56 ... Delay circuit, 61 ... Trigger flip-flop circuit, 62 ... Trigger flip-flop circuit, 63 ... Trigger flip-flop circuit, 6
4 ... Trigger flip-flop circuit, 65 ... RS flip-flop circuit, 66 ... Delay circuit, 100 ... Asynchronous signal detection circuit.

─────────────────────────────────────────────────── --Continued front page (56) Reference JP-A-6-68280 (JP, A) JP-A-57-99851 (JP, A) JP-A-57-41723 (JP, A) JP-A-9- 284726 (JP, A) JP-A-9-153921 (JP, A) JP-A-11-136109 (JP, A) JP-A-6-149417 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 1/24

Claims (7)

(57) [Claims] 1. A non-synchronous signal detection circuit that outputs a detection signal when a detection signal becomes active for a certain period of time or longer, and outputs a one-shot pulse signal when the detection signal becomes active. A first pulse generating circuit, a first delay circuit, and a selector circuit for selecting an output signal of any one of the first pulse generating circuit and the first delay circuit and inputting the selected output signal to the first delay circuit. A first logic circuit that outputs a pulse signal when the first delay circuit outputs a pulse signal while the detected signal is active; and a pulse signal that the first logic circuit outputs. However, when counting one or more pulse signals, a counting operation signal is output, and when a predetermined number of pulse signals are counted, a count completion signal is output and the count signal is output. An asynchronous binary counter circuit that stops outputting an operating signal and is reset by a reset signal; a second pulse generation circuit that outputs a one-shot pulse signal when the detected signal becomes inactive; A second delay circuit that receives the one-shot pulse signal output from the pulse generation circuit, and the pulse signal when the second delay circuit outputs a pulse signal when the detected signal is inactive. A second logic circuit that outputs a reset signal to the asynchronous binary counter circuit, and the selector circuit outputs the first delay circuit when the asynchronous binary counter circuit outputs the counting operation signal. A pulse signal is selected and input to the first delay circuit, and the detection signal is the asynchronous binary counter. An asynchronous signal detection circuit, which is generated based on the count completion signal of the circuit. 2. The third pulse generation circuit, which outputs a one-shot pulse signal as the detection signal when the asynchronous binary counter circuit outputs the count completion signal. Asynchronous signal detection circuit. 3. A third logic circuit which outputs the detection signal when the second logic circuit outputs a pulse signal in a state where the asynchronous binary counter circuit outputs the count completion signal. Claim 1 characterized by the above.
The asynchronous signal detection circuit described. 4. The asynchronous signal detection circuit according to claim 1, wherein the asynchronous binary counter circuit delays and outputs the count completion signal when the reset signal is input. 5. A self-propelled device in which one or both of the first and second delay circuits have a plurality of storage elements connected in series and an input signal is sequentially propagated to each storage element and output. The asynchronous signal detection circuit according to claim 1, wherein the asynchronous signal detection circuit is configured by a formula FIFO circuit. 6. The asynchronous signal detection circuit according to claim 1, wherein one or both of the first and second delay circuits are configured by an analog delay circuit. 7. The asynchronous signal detection circuit according to claim 1, wherein the detected signal is a reset signal of a computer.