JP3531708B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, a memory cell transistor (hereinafter referred to as a cell transistor) having NAND type and NOR type cell transistors is formed on the same semiconductor substrate. The present invention relates to a mixed semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a mask ROM memory cell system,
Conventionally, NAND type ROM and NOR type ROM are known. In a NAND-type ROM, a plurality of transistor rows in which a plurality of cell transistors are connected in series are configured, and enhancement type transistors and depletion type transistors are arranged in these transistor rows according to ROM data, thereby writing ROM data. Is done.

The NOR type ROM constitutes a plurality of transistor rows in which a plurality of cell transistors are connected in parallel to a bit line, and in these transistor rows, the ROM is formed.
ROM data is written by setting the threshold voltage of the transistor selected according to the data to the power supply voltage or higher.

Generally, a NAND type ROM is excellent in high integration but inferior in high speed operation. On the contrary, NOR type R
OM is excellent in high speed, but inferior in high integration.
The reason why NOR type ROM is inferior in high integration is as follows. In general, NOR type ROM requires a contact hole for connecting wiring at a rate of one for two cell transistors, and a region for forming the contact hole and a mask alignment margin at the time of forming the contact hole. This is because it is difficult to miniaturize the memory cell because it has to be secured.

Therefore, for high integration, NAN is mainly used.
D-type ROM has been widely used. The reason is NAN
Since the D-type ROM has a plurality of cell transistors connected in series to form a plurality of transistor rows, it suffices to form contact holes at both ends of the transistor rows, and the higher the number of transistors connected in series, the higher the degree of integration. This is because it can be realized.

[0006]

However, in recent years, there has been a demand for higher integration of memory cells.
In order to achieve higher integration by using the D-type ROM, it is necessary to reduce the dimensional shift and step difference in the element isolation region.

As a conventional example of a memory cell that meets such a demand, element isolation can be performed without forming an element isolation film, thereby reducing the step in the element isolation region and connecting wiring. A high density NOR type ROM (hereinafter referred to as a first conventional example) having advantages of both a NAND type ROM and a NOR type ROM without forming a contact hole for each memory cell.

According to FIG. 54, a high density NOR of the first conventional example
The type ROM will now be explained a little. In the memory cell formation region on the semiconductor substrate 201, a plurality of high-concentration diffusion layers 202 and 203 to be source / drain regions and bit lines are formed in parallel, and a gate insulating film 204 is formed on the semiconductor substrate 201 with a gate insulating film 204 interposed therebetween. A plurality of gate electrodes (word lines) 205 are arranged so as to be orthogonal to the high-concentration diffusion layers 202 and 203 which will be the bit lines. In addition, the gate electrode 205 and the high concentration diffusion layer 20
An impurity having a conductivity type different from that of the source / drain region 202 is ion-implanted in the region where the regions 2 and 203 are not formed, and this region 206 functions as an element isolation means between the cell transistors. I am letting you. The symbols a and b in the figure indicate the regions of one cell transistor.

In the memory cell having such a structure,
Since the element isolation film such as the LOCOS film is not formed, the surface of the semiconductor substrate 201 is flat. Therefore, the gate electrodes 205 can be arranged at a pitch equal to or less than the normally used processing limit. In addition, since the gate electrode 205 can be used as a mask to perform ion implantation in the element isolation region 206 in a self-aligned manner, it has a great effect on high integration of the memory cell.

However, even in such a high density NOR type ROM, there is still a limit in achieving high integration, as in the conventional NAND type ROM. In such a NAND type ROM or high density NOR type ROM, as a method for achieving higher integration, it is conceivable to adopt a method in which the gate electrode has a multilayer structure or a device isolation region is not provided.

Japanese Patent Application Laid-Open No. Sho 5 (1993) discloses the former method.
There is a conventional example proposed in Japanese Patent Application Laid-Open No. 3-41188 (hereinafter referred to as a second conventional example), and the latter method is taken as follows.
There is a conventional example proposed in Japanese Patent Laid-Open No. 63-131568 (hereinafter referred to as a third conventional example).

FIG. 55 shows a conventional example proposed in Japanese Patent Laid-Open No. 53-41188. This conventional example is applied to a NAND type ROM. As shown in the figure, after forming the first gate oxide film 304 on the semiconductor substrate 301,
A plurality of first gate electrodes 305 are arranged on the substrate at a predetermined distance in the horizontal direction to form a first MIS transistor. Furthermore, after forming the first gate electrode 305,
A second gate oxide film 306 is formed on the entire surface of the semiconductor substrate 301 so as to cover it, and a second gate electrode 307 is formed thereon.
To form a second MIS transistor.
In this semiconductor device, since the second gate electrode 307 is arranged between the first gate electrodes 305, the area occupied by each cell transistor in plan view is 1 / th that of the first conventional example. Can be 2. Therefore, the integration degree of the memory cells can be doubled.

FIG. 56 shows a conventional example proposed in Japanese Patent Laid-Open No. 63-131568. This conventional example is a NOR type R
It is applied to OM. After forming the source region 402 and the drain region 403 in parallel on the semiconductor substrate 401 with the channel length separated, the gate electrode 405 is formed so as to be orthogonal to the source region 402, the drain region 403, and the channel region 404 formed therebetween. Has been formed. A plurality of gate electrodes are also arranged in the horizontal direction at a predetermined distance. 406
Is a gate insulating film. According to this conventional example, since the element isolation region does not exist between the gate electrodes 405, the pitch between the wirings can be reduced by that much, so that the memory cell can be highly integrated.

However, in both the second conventional example and the third conventional example, there is a limit in meeting the recent demand for higher integration. Further, according to the second conventional example, since the step becomes large, film breakage and the like are likely to occur, and the manufacturing technique becomes complicated accordingly, which is a bottleneck in improving the manufacturing efficiency.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a novel semiconductor device capable of further increasing the integration density of a memory cell and a manufacturing method thereof.

[0016]

The semiconductor device of the present invention comprises:
A semiconductor device having a memory cell portion in which transistors are formed in a matrix on a semiconductor substrate, and a plurality of word lines also serving as gate electrodes are parallel to each other in a first direction on the semiconductor substrate via an insulating film. And a channel region of the transistor is in contact with each other in a portion of the semiconductor substrate located below the word line, the transistor having at least different sizes.
It is characterized by having different kinds of threshold voltages, whereby the above-mentioned object is achieved.

Preferably, the channel regions arranged in the second direction orthogonal to the word lines are all in contact with each other.

Further, the semiconductor device of the present invention is a semiconductor device having a memory cell portion in which transistors are formed in a matrix on a semiconductor substrate, and in the first direction via an insulating film on the semiconductor substrate. A plurality of word lines formed in parallel and a plurality of transistors connected in series in a second direction orthogonal to the word lines with the word lines serving as gate electrodes are provided, and a plurality of columns are arranged in the first direction. A first transistor array arranged, and a plurality of transistors sharing the gate electrode with each transistor of the first transistor array, using a channel region of each transistor as a source / drain, and having threshold voltages different from each other, A second transistor array in which the plurality of transistors are connected in parallel between the first transistor array, and all of the second transistor array are provided. The threshold voltage of the transistor first
It is higher than the threshold voltage of the transistors in the transistor array, which achieves the above object.

Preferably, a plurality of trenches are formed in parallel with each other in the second direction of the semiconductor substrate, the channel region of each transistor of the first transistor row or the second
One of the channel regions of each transistor in the transistor row is formed on the upper surface and the bottom surface of the semiconductor substrate between the grooves, and the other is formed on the side wall of the groove.

Also, preferably, the word line comprises a first word line and a second word line, and a plurality of grooves are formed in parallel with each other in a first direction of the semiconductor substrate, and the first word line is formed. Alternatively, one of the second word lines is formed on the upper surface and the bottom surface of the semiconductor substrate between the trenches via the insulating film, and the other is formed on the sidewall of the trench, and the channel of each transistor of the first transistor row is formed. A region and a channel region of each transistor of the second transistor row are formed on the upper surface of the semiconductor substrate between the trenches, the trench sidewall and the trench bottom surface, and extend in the second direction.

The method of manufacturing a semiconductor device according to the present invention is
A plurality of channel regions of NAND-side cell transistors extend in parallel in a second direction on the semiconductor substrate,
A channel portion of the NOR-side cell transistor extending in the second direction is formed between the channel regions of the D-side cell transistors, and the channel region of the NAND-side cell transistor is the source of the NOR-side cell transistor. A method of manufacturing a semiconductor device to be a / drain, comprising: a NAND-side cell transistor and a NOR-side cell in a first direction orthogonal to the second direction on the semiconductor substrate via a first gate insulating film. A step of forming a plurality of first gate electrodes which are gate electrodes of the transistors in parallel, and a cell transistor on the NAND side and a NO transistor on the semiconductor substrate via the second gate insulating film between the first gate electrodes.
A step of forming a second gate electrode to be a gate electrode of the R-side cell transistor, and a high-concentration diffusion layer to be a lead-out electrode of a memory cell region composed of the NAND-side cell transistor and the NOR-side cell transistor. Forming a source / drain region of a cell transistor on the NAND side by implanting ions into the memory cell region, forming a source / drain region of the NAND side cell transistor; Connecting the region end, implanting ions into the channel region of the cell transistor on the NOR side to control the threshold voltage of the cell transistor on the NOR side, and controlling the threshold voltage of the cell transistor on the NAND side Implanting ions into the channel region of the cell transistor,
Implanting ions into the channel region of the cell transistor to write data into the NAND side cell transistor; and implanting ions into the channel region of the cell transistor to write data into the NOR side cell transistor. And the steps of injecting are carried out, and each of the above steps is performed in an arbitrary step order, whereby the above object is achieved.

Preferably, a plurality of grooves are formed in parallel with each other in the second direction of the semiconductor substrate, and ions are implanted into the upper surface of the semiconductor substrate, the groove bottom surface and the groove side wall between the grooves, and between the grooves. The method further includes a step of forming one of a channel region of the cell transistor on the NAND side and a channel region of the cell transistor on the NOR side on the upper surface of the semiconductor substrate and the bottom surface of the groove, and forming the other on the side wall of the groove. The steps are performed in any order.

Further, preferably, a plurality of grooves are formed in parallel with each other in the first direction of the semiconductor substrate, and one of the first gate electrode and the second gate electrode is provided with an insulating film interposed therebetween. The semiconductor substrate upper surface and the groove bottom surface between the grooves are formed, and the other is formed on the groove side wall, and the channel region of the NAND side cell transistor and the NOR side cell transistor is formed on the semiconductor substrate upper surface between the grooves. Further, the method further includes a step of forming on the groove side wall and the groove bottom surface, and this step and each of the steps are performed in an arbitrary order.

In the method of manufacturing a semiconductor device of the present invention, performing each step in any order literally means performing each step in any order, as well as performing any of a plurality of steps at the same time. Is also meant to include.

(Operation) The semiconductor device of the present invention is a NAND
Type and NOR type cell transistors are mixed and are arranged in the memory cell region on the semiconductor substrate so that the channel regions (channel portions) of the respective cell transistors are in contact with each other. First
It is possible to achieve the degree of integration of the cell transistors, that is, the degree of integration of the memory cell in the second direction and the second direction orthogonal to the direction.

Therefore, for example, as a word line which also serves as a gate electrode, another word line is wired between adjacent word lines of the first conventional example, and the first word line and the conventional wiring pattern are wired. According to the configuration in which the second word line is also used as the gate electrode of each cell transistor, the occupied length of the cell transistor in the second direction can be halved. Also, N
Since the channel region of the cell transistor on the AND side is used as the source / drain of the cell transistor on the NOR side, the occupation length of the cell transistor in the first direction corresponds to that in the second direction, and the channel length of the first conventional example is It can be halved. Therefore, according to the semiconductor device of the present invention, the degree of integration of the memory cells can be increased four times as compared with that of the first conventional example. Further, the integration degree can be improved to about twice that of the second conventional example.

Further, if the multi-valued information is stored in the cell transistor on the NOR side, for example, the memory cell can be highly integrated. For example, if the threshold voltage of the cell transistor on the NOR side is selectively changed to have four values, the integration degree is 4 to 6 times that of the first conventional example of the single-layer polysilicon process. That is, with four values, twice as much information can be stored as in the case of a normal binary value, so that the cell transistor on the NOR side can be further doubled and highly integrated. Therefore, according to the present invention, the integration degree of 4 times can be further increased to 6 times (4 times + 2 times = 6 times) as compared with the first conventional example. Similarly, as compared with the second conventional example of the two-layer polysilicon process, the degree of integration is doubled to tripled. Furthermore, if the multilevel levels are set in multiple stages, further high integration can be achieved.

Further, a plurality of grooves are formed on the semiconductor substrate,
According to the configuration in which the channel region of the cell transistor is formed on the upper surface of the semiconductor substrate between the grooves, the groove bottom surface, and the groove side wall (groove side surface), more cell transistors can be arranged in the same plan view area. Further, the degree of integration of memory cells can be further improved.

Further, according to the structure, one of the first word line and the second word line is formed on the upper surface of the semiconductor substrate and the bottom surface of the groove between the grooves via the insulating film, and the other is formed on the side wall of the groove. Since the wiring pitch in plan view can be further reduced, higher integration can be further achieved.

Further, according to the method of manufacturing a semiconductor device of the present invention, the above steps can be performed in an arbitrary order,
For example, if the ion implantation process for writing data is performed simultaneously on the NAND side and the NOR side using one mask, only one implantation process is required, so that the process can be simplified. The manufacturing efficiency of the device can be improved.

Further, the writing of the ROM data of the mask ROM to which the present invention is applied is performed in a later step,
Since the process after writing the ROM data is shortened, this process may be performed at the end of the above process.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 5 show a first embodiment of a semiconductor device of the present invention.

Unlike the conventional high-density NOR ROM memory cell described above, the semiconductor device of the first embodiment does not have a high-concentration diffusion wiring portion corresponding to a sub-bit line, and instead has an NA.
The cell transistor 90 of the ND type ROM is arranged. That is, the NOR-side cell transistor 100 and N
The cell transistor 90 on the AND side is set to the memory cell area 110.
It has a configuration to be mixed in.

As shown in the drawing, in the first embodiment, two layers of gate electrodes also serving as word lines are arranged in the memory cell region. That is, the gate electrode 7 of the first layer in the horizontal direction
Are formed in parallel with each other at a predetermined interval, and the second-layer gate electrode 10 is provided between each adjacent gate electrodes 7. Therefore, both gate electrodes 7 and 10 are parallel to each other. In the present invention, the two gate electrodes 7 and 10 are parallel to each other.
Not only when they are parallel to each other with a predetermined interval,
This is a concept including a case where adjacent edge portions of both gate electrodes 7 and 10 are vertically overlapped with each other.

Then, the cell transistor 9 on the NAND side
By using the gate electrodes 7 and 10 of two layers, a plurality of 0 channel portions 91 are directly connected and arranged, and the region used only as a conventional wiring is utilized as a memory cell.

In addition, the cell transistor 9 on the NAND side
N sharing the same gate electrode between 0 channel portions 91
The channel portion 101 of the OR-side cell transistor 100 is arranged. Therefore, in the memory cell region, the entire surface of the semiconductor substrate 1 below the gate electrodes 7 and 10 is used as the channel region of each cell transistor. Therefore, high integration of the memory cell can be achieved.

The overall structure will now be described with reference to FIGS. 1 and 2. In the memory cell region 110, a plurality of first word lines that also serve as the first word lines in the first direction corresponding to the left-right direction in the drawing are used. The gate electrodes 7 are arranged in parallel with each other.
Then, the second gate electrodes 10 which also serve as the second word lines are provided between the first gate electrodes 7.

A plurality of select lines 71 and 72 are arranged in the first direction on both sides of the memory cell region 110 in the second direction orthogonal to the first direction.
One select line 71 ... Is arranged on the bit line BL side,
The other selection lines 72 ... Are wired on the ground line GL side. A selection line transistor 73 is connected to each of the selection lines 71 and 72. With such a configuration, when the selection lines 71 and 72 are selected by the selection line transistor 73 and the word line is selected, the cell transistor in a predetermined address region is selected.

As shown in FIGS. 1 and 2, the channel portion 91 of the cell transistor 90 on the NAND side extends in the second direction, and the channel portion 101 of the cell transistor 100 on the NOR side is provided between the adjacent channel portions 91. Extend in the second direction. The end of the channel portion 91 on the bit line BL side is connected to the extraction electrode 5 (see FIG. 2). Further, as shown in FIG. 1, the channel portion 91 of the cell transistor 90 on the NAND side is the cell transistor 10 on the NOR side.
The source / drain of 0 is also used.

Here, the threshold voltage Vth of all the cell transistors 100 on the NOR side is higher than the threshold voltage Vth of the cell transistor 90 on the NAND side. In addition,
The detailed configuration of the semiconductor device will be clarified in the manufacturing process described later.

Next, the writing operation of the ROM data information will be described with reference to FIG. 3 and Table 1.

[0043]

[Table 1]

First, the cell transistor 90 on the NAND side
Selects (1) depletion type or (2) enhancement type. On the other hand, in the NOR side cell transistor 100, all of the threshold voltage Vth higher than that of the enhancement type transistor used for the NAND side cell transistor 90 is set. The cell transistor is set (3), and the threshold voltage Vth is selectively set to a voltage equal to or higher than the power supply voltage (4) to make a transistor of complete OFF.

ROM based on Table 1, FIG. 3 and FIG.
The reading of data information will be described. Before reading, all word lines are set to "M" level. In this state, all the cell transistors 90 on the NAND side are in the ON state, and all the cell transistors 100 on the NOR side are OF.
It is in the F state.

When reading the cell transistor 90 on the NAND side, as shown in FIGS. 3 and 4, the selected word line is set to the “L” level. Then, the cell transistor 90 to be read is provided between the bit line BL and the ground line GL of the NAND-side cell transistor column to be read.
However, if it is (2) the enhancement type, it will not conduct, and (1)
If it is a depletion type, it is conductive and can be read.

Next, when reading the cell transistor 100 on the NOR side, as shown in FIGS. 3 and 5, the selected word line is set to the "H" level. Then, the bit line BL of the cell transistor column on the NOR side to be read
Read between cell and ground line GL
If 100 is (4) a high threshold voltage Vth transistor that is completely OFF, it does not conduct, and (3) an intermediate level threshold voltage Vt.
Since a transistor having h is conductive, ROM data information can be read. At this time, since all the cell transistors 90 on the NAND side are ON, it can be regarded as a wiring.

In the above description, the bit line BL of the NAND-side cell transistor column and the bit line BL of the NOR-side cell transistor column are expressed as different bit lines. By selecting a path, they are also used (see FIGS. 4 and 5).

Next, the manufacturing process of the semiconductor device of the first embodiment will be described with reference to FIGS. First, as shown in FIG. 6, the oxide film 2 is formed on the semiconductor substrate 1. Then, a resist pattern 3 is formed thereon as an ion implantation mask of impurities having a conductivity type opposite to that of the semiconductor substrate 1. Next, ions 4 are implanted into the semiconductor substrate 1 from above the resist pattern 3. Thereby, as shown in FIG. 7, source / drain regions 5 are formed in the ion-implanted region. The source / drain region 5 becomes the extraction electrode 5 from the NAND-side cell transistor shown in FIG.

Here, for example, if the cell transistor has an NMOS structure, the above-mentioned ion implantation is performed by implanting arsenic ions (As ⁺ ) in the order of 10 ¹⁵ cm ^-2 . The implantation energy is, for example, 40 keV.

Next, the oxide film 2 and the resist pattern 3 are removed, and a film thickness of 5 is formed on the semiconductor substrate 1 as shown in FIG.
A first gate oxide film 6 having a thickness of about 30 nm is formed. Then, a plurality of first gate electrodes 7 to be the first word lines are formed in parallel with each other on the gate oxide film 6. Here, as the first gate electrode 7, for example, 200 to 300
nm thick N ⁺ PolySi film or 100 nm thick lower layer N
^A two-layer structure having a ⁺ PolySi film and an upper tungsten silicide film with a thickness of 100 nm is used.

Next, as shown in FIG. 8, an insulating film is formed on the semiconductor substrate 1 so as to cover the first gate electrode 7. This insulating film becomes the inter-gate electrode insulating film 8 and the second gate insulating film 9. Then, a plurality of second gate electrodes 10 to be second word lines are formed in parallel with each other on the semiconductor substrate 1 with the inter-gate electrode insulating film 8 and the second gate insulating film 9 interposed therebetween. As shown in FIGS. 8 and 2, these second gate electrodes 10 are arranged between the first gate electrodes 8 and are parallel to the first gate electrodes 7. Here, as the second gate electrode 10, for example, 200
An N ⁺ PolySi film having a thickness of up to 300 nm or a two-layer structure including a lower layer N ⁺ PolySi film having a thickness of 100 nm and an upper tungsten silicide film having a thickness of 100 nm is used.

It is desirable that the film material and the film thickness are selected and set so that the ion implantation blocking capabilities of the first gate electrode 7 and the second gate electrode 10 are the same. That is, by doing so, the NA connected to the first gate electrode 7 at the time of the ROM data writing ion implantation in the subsequent process.
The cell transistor 90 on the ND side and the cell transistor 100 on the NOR side, and the N connected to the second gate electrode 10.
This is because the ion implantation process can be performed simultaneously on the AND-side cell transistor 90 and the NOR-side cell transistor 100, and the number of processes can be reduced by that amount, so that the manufacturing efficiency can be improved.

As a method of forming the gate electrodes 7 and 10, it is possible to use a method such as buried etchback or the like, in addition to the usual photolithography and dry etching methods, to form them by self-alignment. According to this method, it is possible to prevent the first gate electrode 7 and the second gate electrode 10 from overlapping with each other, and it is possible to prevent a defect of insufficient implantation at the overlapping portion during the ROM data writing ion implantation in a later step.

Next, in order to raise the threshold voltage Vth of all the NOR-side cell transistors to the intermediate level in advance, as shown in FIGS. 9B to 9D, the first gate electrode 7 and the first gate electrode 7 are formed. Region in the semiconductor substrate 1 below the second gate electrode 10 (channel portion 101 of the cell transistor 100 on the NOR side)
On the other hand, ions 11 of the same conductivity type as the semiconductor substrate 1 are implanted. At this time, as shown in FIGS. 9 (a) and 9 (c),
The NAND type cell transistor 100 is covered with the resist pattern 12.

Here, the ion implantation into the channel portion 101 is carried out, for example, in the case where the cell transistor has the NM0S structure, with boron ion (B ⁺ ) being implanted at a dose of 10 ¹² cm ⁻² . The implantation energy is, for example, 140 keV
Done in.

At this time, as shown in FIG. 9D, the first
If there is a misalignment between the gate electrode 7 and the second gate electrode 10 of the above and a space 13 is generated between the gate electrodes of the first and second layers, the punch-through (element isolation) breakdown voltage of the memory cell in the space 13 Is a problem.

This problem can be easily solved by taking the following means. That is, in the ion implantation step of increasing the threshold voltage Vth in advance, ion implantation 11 is performed into the channel portion through the gate electrodes 7 and 10 at a relatively high implantation energy, and at the same time, low implantation energy that does not pass through the gate electrodes 7 and 10. Then, punch-through prevention ion implantation 14 may be performed in the region where there is no gate electrode. here,
The punch-through prevention ion implantation is performed by implanting boron ions (B ⁺ ) in the order of 10 ¹² to 10 ¹³ cm ⁻² if the cell transistor has an NMOS structure, for example. The implantation energy is, for example, 20 to 50 keV.

Further, although the punch-through breakdown voltage between the extraction electrodes 5 from the cell transistor on the NAND side also poses a problem, these ion implantation steps can be simultaneously performed by one mask step by using the above method. Therefore, according to the manufacturing process of the first embodiment, the mask process is reduced by one by simultaneously performing the ion implantation for controlling the threshold voltage Vth of the cell transistor on the NOR side and the ion implantation for preventing punch-through. Therefore, a low-cost process with a simplified process can be obtained.

Further, in the first embodiment, in order to increase the density,
An example is shown in which element isolation by ion implantation is used for element isolation of the transistor connected to the select line, but element isolation can also be performed using an element isolation oxide film (see FIG. 2). .

Next, as shown in FIG. 10, by selectively selecting enhancement-type or depletion-type transistors, all the cell transistors are depleted in advance with respect to the NAND-side cell transistor 90 in which ROM data is written. Ion implantation for performing 15
To the channel section 91. At this time, the resist pattern 17 is formed on the semiconductor substrate 1. The order of the steps shown in FIG. 10 may be reversed from that of the steps shown in FIG.

Here, for the ion implantation 15, for example, N
In the case of the cell transistor having the M0S structure, phosphorus ions (P ⁺ ) are implanted with a dose of 10 ¹² to 10 ¹³ cm ^-2 . The implantation energy is, for example, 300 to 400 keV.

At this time, as shown in FIGS. 10A and 10D, at the same time, ion implantation 16 for forming the source / drain of the cell transistor 90 on the NAND side is performed,
The diffusion portion of the extraction electrode 5 may be connected to the source / drain portion 18 at the end of the memory cell region (see FIG. 11A). Ion implantation for forming the source / drain is performed, for example, when the cell transistor 90 on the NAND side is NM.
With the OS structure, arsenic ion (AS ⁺ ) is 10 ¹⁵ cm
^-Two injections. The implantation energy is, for example, 40 keV.

In the first embodiment, the mask process is performed once.
Depletion ion implantation 15 is performed on the channel portion through the gate electrodes 7 and 10 with high implantation energy, and at the same time, source / drain ion implantation 16 is performed onto the region without the gate electrode with low implantation energy that does not pass through the gate electrodes 7 and 10. Therefore, each injection process can be performed by self-alignment. Therefore, the mask process is reduced once,
A low-cost process with a simplified process is obtained.

The diffusion portion of the extraction electrode 5 and the source / drain portion 18 at the end of the memory cell region may be connected by a heat treatment process. FIG. 11A shows a state in which the above connection is performed through a heat treatment process.

According to the manufacturing method of Embodiment 1, FIG.
As shown in (d), the first and second gate electrodes 7,
It is possible to provide a manufacturing method that has a sufficient margin with respect to misalignment between the ten. That is, when there is a misalignment between the first gate electrode 7 and the second gate electrode 10 and a space 19 is generated between the gate electrodes 7 and 10 of the first and second layers (FIG. 11B). However, there is a problem that connection between the cell transistors cannot be performed due to the space 19.

However, according to the above method, the ion implantation 16 for forming the source / drain is performed in the space 19 without the gate electrode with a relatively low implantation energy which does not pass through the gate electrode. Therefore, FIG.
As shown in (b), the NAND-side cell transistor 9
Since the 0s are connected by the source / drain regions 20 injected into the semiconductor substrate 1, it is possible to prevent a defect in which the cell transistors are not connected.

In order to obtain a cell transistor having a smaller gate length, an ion implantation process for forming the source / drain is performed, and the second gate electrode 10 is provided with an insulating film such as a sidewall insulating film between the gate electrodes. It is also effective to perform after forming. That is, in this way, diffusion under the gate electrodes can be suppressed by the thickness of the insulating film between the gate electrodes.

Next, as shown in FIGS. 12A and 12B, the writing of the R0M data is simultaneously performed by the cell transistor 90 on the NAND side and the cell transistor 100 on the NOR side. Specifically, first, a resist pattern 21 shown in FIGS. 12A and 12B is formed on the semiconductor substrate 1 as an R0M data write implantation mask. Then, N
The cell transistor 90 on the AND side is a depletion type and is converted into an enhancement type by implanting ions 22 (denoted by a mark X) of the same conductivity type as the semiconductor substrate 1 (the mark Δ and a mark X overlap each other). Area).

On the other hand, in the cell transistor 100 on the NOR side, the ions 22 (×
(Indicated by a mark), the threshold voltage Vth is selectively set to be substantially equal to or higher than the power supply voltage by setting a transistor that is always OFF (region in which x is doubled).

Here, the implantation condition for writing the ROM data is, for example, if the cell transistor has an NMOS structure, boron ions (B ⁺ ) are implanted at a dose of 10 ¹³ cm ⁻² . Regarding the injection energy, for example, 140 to 180
Perform with keV.

At this time, for example, in the case of the NMOS structure, the ROM data write implantation is boron ion (B ⁺ ).
Therefore, high energy injection can be used in a process such as after laminating an interlayer insulating film, opening a contact hole, or after forming a metal wiring. With such high energy implantation, the manufacturing efficiency can be improved accordingly, and there is an advantage that it can contribute to the cost reduction of the semiconductor device.

In the first embodiment, if the threshold voltage Vth of the NOR-side cell transistor 100 is multivalued, the memory cell can be highly integrated. As an example, NO
If the threshold voltage Vth of the cell transistor on the R side is selectively changed to have four values, the integration degree is increased from 4 times to 6 times as compared with the conventional 1-layer polysilicon process, and the 2-layer polysilicon process is obtained. Compared with
Doubled. Furthermore, if the multilevel levels are set in multiple stages, further high integration can be achieved.

To manufacture the NOR-side cell transistor 100 having a multi-valued threshold voltage Vth, for example, in the implantation process for writing ROM data in FIG. 12, the ion implantation amount is changed for each different threshold voltage Vth. , You can do it multiple times.

Further, as the writing of ROM data is performed in a later step, the step after inserting the ROM is shortened and the manufacturing efficiency can be improved. Therefore, after further laminating an interlayer insulating film, opening a contact hole, or It is more desirable to use high energy implantation in a step such as after forming metal wiring.

Further, in this case, since the surface is flattened by the interlayer insulating film, even when the first gate electrode 7 and the second gate electrode 10 are overlapped with each other at the time of the ROM data writing ion implantation in the subsequent step, the overlapped portion is generated. It is possible to mitigate defects that cause insufficient injection.

After the above series of steps, the first half step of the semiconductor device is completed through the steps of forming an interlayer insulating film with a metal wiring, forming a contact hole, forming a metal wiring, forming a protective film, and the like. Perform the assembly process of the second half process,
The semiconductor device according to the first embodiment is manufactured.

(Second Embodiment) Next, a second embodiment of the semiconductor device of the present invention will be described. The configuration of the semiconductor device of the second embodiment is the same as the configuration of the semiconductor device of the first embodiment, but the ROM data writing process is different. The different steps will be described below with reference to FIGS. However, FIG. 13 shows the process shown in FIG. 9C of the first embodiment, and FIGS. 14 and 15 show FIG. 12C of the first embodiment.
Corresponds to each of the steps indicated by.

Second gate electrode 10 shown in the first embodiment
13, the ion 11 of the same conductivity type as that of the semiconductor substrate 1 is implanted in order to raise the threshold voltage Vth of the NOR-side cell transistor 100 to an intermediate level in advance, as shown in FIG. The steps up to this step are the same as those of the first embodiment.

Next, in the second embodiment, N shown in FIG.
In the process of lowering the threshold voltage Vth of the cell transistor 90 on the AND side in advance and depleting it, unlike the process of the first embodiment, ion implantation for depletion is not performed and the source / drain of the cell transistor 90 is formed. Ion implantation is performed only for this purpose. At this time, as shown in FIG. 13, the resist pattern 12 is formed on the semiconductor substrate 1 similarly to the above.

Then, as shown in FIG.
To write ROM data to the D-side cell transistor 90, a resist pattern 30 is formed on the semiconductor substrate 1 as a ROM data write injection mask, and a NAND
The cell transistor 90 on the side is of the enhancement type and is converted into the deflection type by implanting ions 31 (denoted by a triangle) of a conductivity type opposite to that of the semiconductor substrate 1. At this time, the channel portion 101 of the cell transistor 100 on the NOR side is covered with the resist pattern 30.

Here, the ion implantation conditions for writing ROM data on the NAND side are, for example, if the cell transistor 90 has an NMOS structure, phosphorus ion (P ⁺ ) is implanted at a dose of 10 ¹² to 10 ¹³ cm ^-2. Done in. The implantation energy is, for example, 300 to 400 keV.

On the other hand, in writing ROM data to the cell transistor 100 on the N0R side, as shown in FIG. 15, a resist pattern 32 is formed on the semiconductor substrate 1 as a mask for writing and writing ROM data, and the cell transistor 100 on the NOR side is formed. , Ions of the same conductivity type as the semiconductor substrate 1 (indicated by X) are implanted, thereby selectively setting the threshold voltage Vth to approximately the power supply voltage or higher, and keeping the O level at all times.
This is done by setting the transistor of FF (the area where x is double overlapped). At this time, the channel portion 91 of the NAND-side cell transistor 90 has the resist pattern 32.
Cover with.

Here, the ion implantation conditions for writing the ROM data on the NOR side are, for example, cell transistors.
If 100 is an NMOS structure, 1 boron ion (B ⁺ )
The injection amount is 0 ¹³ cm ^-2 . The implantation energy is, for example, 140 to 180 keV.

Also in the semiconductor device of the second embodiment, high integration can be achieved as in the semiconductor device of the first embodiment. Furthermore, the second embodiment is advantageous over the first embodiment in the following points. That is, the method of manufacturing the enhancement-type cell transistor on the NAND side is the enhancement type → depletion type → enhancement type in the first embodiment. The enhancement-type cell transistor is once converted to the depletion type, and then the original enhancement type is changed again. Are returning. On the other hand, in the second embodiment, the enhancement-type cell transistor remains the same from the beginning. Therefore, according to the second embodiment,
As a result, the manufacturing process can be simplified, so that there are few variations in characteristics due to various variations in manufacturing conditions. Therefore, there is an advantage that a cell transistor having stable characteristics can be obtained.

(Third Embodiment) FIG. 16 shows a third embodiment of the semiconductor device of the present invention. In addition, FIG. 17 shows the manufacturing process. However, FIG. 17 corresponds to the step shown in FIG. 11A of the first embodiment. In addition, in FIG.
Portions corresponding to those in FIG. 11A are designated by the same reference numerals, and detailed description thereof will be omitted.

As is clear from a comparison between FIG. 17 and FIG. 11A, in the third embodiment, the memory cell selection line includes the first-layer gate electrode 7 and the second-layer gate electrode 10. Since they are arranged alternately, the space between the wirings can be set to be equal to or less than the minimum processing line width of the process. That is, the wiring pitch can be made narrower than that of the first embodiment, and accordingly there is an advantage that higher integration can be achieved.

(Embodiment 4) FIGS. 18 to 20 show Embodiment 4 of the semiconductor device of the present invention. In this semiconductor device, the selection transistor 73 for selecting a memory cell is a depletion type transistor. That is, as shown in FIG. 18, outside the memory cell region, on the semiconductor substrate 1 below the plurality of select lines 71 and 72 arranged in the first direction, a plurality of depletions are provided for each select line. Type transistor 73 (indicated by a mesh) is connected. These selection transistors 73 are NAND
It is manufactured at the same time in the process of forming the side cell transistor.

The manufacturing process will be described below with reference to FIGS. 19 and 20. However, FIGS. 19 and 20 are views showing the EE ′ cross section of FIG. 18 in the order of steps, and FIG.
9 and 20 are diagrams corresponding to the steps of FIG. 10A and FIG. 11A of the first embodiment, respectively.

First, as shown in FIG. 6 of the first embodiment, the oxide film 2 is formed on the semiconductor substrate 1. Subsequently, a resist pattern 3 is formed as an ion implantation mask of impurities having a conductivity type opposite to that of the semiconductor substrate 1, and ions 4 for forming a source / drain are implanted through the resist pattern 3 to form an ion on the semiconductor substrate 1. , Source / drain regions 5 as shown in FIG. 7 are formed. The source / drain region 5 is used as the extraction electrode 5 from the NAND-side cell transistor shown in FIG. Continuing with FIG.
~ Perform the steps shown in FIG.

Next, ion implantation 15 for depletion of the cell transistor is performed, and at the same time, NAN is performed.
Ion implantation 16 is performed to form the source / drain of the D-side cell transistor. Here, in the fourth embodiment, the resist pattern serving as an ion implantation mask at the time of the ion implantation 16 is different from that of the first embodiment so that the depletion type select transistor can be simultaneously formed (FIG. 18). Therefore, as shown in FIGS. 19 and 20, by performing the same ion implantation step as described above, the depletion type select line transistor 73 can be formed without increasing the steps.

The subsequent steps, such as writing ROM data, are performed in the same procedure as in the first embodiment.

According to the fourth embodiment, the step of forming the select line transistor 73 can be performed simultaneously with the step of converting the cell transistor on the NAND side into the depletion type, only by changing the resist pattern. Therefore, the number of masking steps is reduced by one compared with that of the first embodiment, so that a low-cost process in which the steps are simplified can be obtained.

(Fifth Embodiment) FIG. 21 shows a semiconductor device according to a fifth embodiment of the present invention. In the fifth embodiment, the first-layer and second-layer gate electrodes 7 and 10 of the NAND-side cell transistor 90 are arranged on the semiconductor substrate 1 so as to be separated from each other.
Ion implantation for forming the source / drain of the cell transistor 90 on the NAND side is performed in all the cell transistors 90. Note that FIG. 21 corresponds to the step of FIG. 17 of the third embodiment and corresponds to a cross-sectional view taken along the line DD ′ of FIG. 18.

According to the fifth embodiment, the gap g is formed between the first-layer and second-layer gate electrodes 7 and 10.
Ion implantation 15 for forming the source / drain of the cell transistor 90 on the NAND side can be reliably performed on the semiconductor substrate 1 through the gap g. For this reason,
According to the fifth embodiment, a semiconductor device that can obtain a stable read current can be realized.

(Sixth Embodiment) FIG. 22 shows a sixth embodiment of the semiconductor device of the present invention. In the sixth embodiment, the configuration of the fifth embodiment is applied to that of the fourth embodiment. That is, in the configuration of the fourth embodiment in which the depletion type select line transistor 73 is simultaneously formed in the process of forming the cell transistor 90 on the NAND side, a gap is formed between the first-layer and second-layer gate electrodes 7 and 10. However, a configuration is adopted in which ion implantation is performed to form the source / drain of the cell transistor 90 on the NAND side on the semiconductor substrate 1 through this gap.

According to the sixth embodiment, it is possible to realize a semiconductor device capable of exhibiting both the effects described in the fourth embodiment and the effects described in the fifth embodiment.

FIG. 22 is a diagram corresponding to the process of FIG. 20 of the fourth embodiment, the corresponding parts are designated by the same reference numerals, and the detailed description thereof will be omitted.

(Embodiment 7) FIG. 23 shows Embodiment 7 of the semiconductor device of the present invention. The seventh embodiment differs from the first embodiment in that the lead electrode 5 is formed after the first gate electrode 7 is formed. The process will be described below.

First, as shown in FIG. 23, the semiconductor substrate 1
A first gate oxide film 6 having a film thickness of about 5 to 30 nm is formed thereon, and a plurality of gate electrodes 7 are formed on the gate oxide film 6.
Are formed parallel to each other in a first direction. As the gate electrode 7, as in the above, 200-300 nm thick N ⁺ PolySi
Film or 100 nm thick lower N ⁺ PolySi film and 100 n
A two-layer structure having an m-thick upper layer tungsten silicide film is used.

Subsequently, a resist pattern 3 is formed on the semiconductor substrate 1 and the first gate electrode 7 as an ion implantation mask of impurities having a conductivity type opposite to that of the semiconductor substrate 1. Subsequently, ions 4 for forming source / drain are implanted from above the resist pattern 3 to form the semiconductor substrate 1
Form the source / drain regions 5 on top and use this for NAND
It is used as the extraction electrode 5 from the side cell transistor.

Subsequently, the second gate electrode 9 is formed,
Then, the semiconductor device of the seventh embodiment is manufactured through the same steps as those of the first embodiment.

(Embodiment 8) FIG. 24 shows Embodiment 8 of the semiconductor device of the present invention. In the eighth embodiment, the gate electrode has a one-layer structure. That is, as shown in FIG. 24, a plurality of gate electrodes 7 ′ similar to the first gate electrode 7 are formed on the semiconductor substrate 1 with the gate oxide film 6 interposed therebetween.

According to the semiconductor device of the eighth embodiment, since the gate electrode is a single layer, it is inferior to the ones of the first to sixth embodiments in high integration, but the number of steps is reduced, and accordingly, the amount is reduced. The manufacturing method is simple, and the manufacturing efficiency can be improved.

Note that FIG. 24 is the same as FIG. 11A of the first embodiment.
It is a figure corresponding to a process of, and the same code | symbol is attached | subjected to a corresponding part and a specific description is abbreviate | omitted.

Another embodiment of the semiconductor device of the present invention, which has higher integration than those of the above embodiments, will be described below. In each of the embodiments described below, a groove 42 extending in a second direction orthogonal to the arrangement direction of the first-layer and second-layer gate electrodes 7 and 10 is formed in the semiconductor substrate 1, and the groove 42 is formed. Cell transistors are also formed on the bottom surface and side surfaces of the cell, thereby adopting a configuration in which higher integration is achieved. In the following, embodiments of this type will be described step by step.

(Ninth Embodiment) FIGS. 25 to 40 show a ninth embodiment of the semiconductor device of the present invention. A plurality of grooves 42 extending in the second direction are formed on the semiconductor substrate 41. The semiconductor substrate 41 including the groove 42 includes a first gate insulating film 43.
A plurality of first gate electrodes (first word lines) 44 extending in a first direction orthogonal to the direction of the groove 42 are formed in parallel with each other. In addition, the semiconductor substrate 41 including the groove 42
A second gate insulating film 45 is formed between the upper first gate electrodes 44.
A plurality of second gate electrodes 46 (second word lines) are formed in parallel with the first gate electrodes 44 via the.

Below the first gate electrode 44, the channel portion 91 of the first cell transistor 90 on the NAND side is formed. More specifically, the groove 4 on the upper surface of the semiconductor substrate 41
It is formed on the bottom of the groove 42 and the portion located between the two. On the side wall (groove side surface) of the groove 42, the channel portion 101 of the NOR-side third cell transistor 100 is formed. On the other hand, below the second gate electrode 46, the channel section 91 of the second cell transistor 90 on the NAND side is formed. More specifically, it is formed on a portion of the upper surface of the semiconductor substrate 41 located between the grooves 42 and on the bottom surface of the groove 42. Groove 4
A channel portion of the NOR-side fourth transistor is formed on the sidewall of 2.

As described above, also in the semiconductor device of Embodiment 9, the NAND-side cell transistor 90 and the NOR-side cell transistor 100 are mixed in the memory cell region, and the groove 42 is formed. Since the area for forming the channel portion of the cell transistor per the same planar view area is increased, eventually, higher integration can be achieved as compared with each of the above embodiments.

Embodiment 9 will be described below with reference to FIGS.
The manufacturing process of the semiconductor device will be described. First, FIG.
As shown in FIG. 6, a plurality of grooves 42 are formed in parallel in the second direction on the semiconductor substrate 41 by a known etching method.
Here, the depth of the groove 42 is formed to a depth corresponding to the channel length of the channel portion 101 of the NOR-side third and fourth cell transistors 100 formed on the sidewall of the groove 42 in a later step. Preferably, for example, 0.3 to 1.0 μm
The degree. In forming the groove 42, the resist pattern 47 or the oxide film 48 shown in FIG. 26 is used as an etching mask.

Next, as shown in FIG. 27A, the groove 42
27B, an oxide film 49 is formed on the inner wall thereof, and subsequently, as shown in FIG. 27B, in order to control the threshold voltage Vth of the channel portions of the third and fourth cell transistors formed on the sidewalls of the groove 42, Regions other than the memory cell portion are masked with the resist pattern 50, and ions are implanted into the semiconductor substrate 41 in this state. Specifically, the same conductivity type as the semiconductor substrate 41, for example, boron ions 51 is implanted with a dose of about 10 ¹² cm ^-2 . Regarding the implantation energy, for example, 2
It is performed at 0 to 50 keV. In addition, the groove 42 of the semiconductor substrate 41
Is obliquely injected from two directions at an angle of about 15 to 60 ° with respect to the side surface. More specifically, the implantation angle depends on the groove 42.
Depending on the width and depth of the groove 42, the condition for implanting only into the sidewall of the groove 42 is selected. At this time, since the oxide film 48 is formed on the upper surface of the semiconductor substrate 41 between the grooves 42, ions are not implanted. Further, since the bottom surface of the groove 42 is also shielded by the adjacent convex portion (the upper surface of the semiconductor substrate 41 between the grooves 42), ions are not implanted. When the semiconductor substrate 41 is rotated about the normal direction as a rotation axis while performing oblique implantation at an angle in the normal direction to the semiconductor substrate 41, for example, at an angle of about 15 to 60 °, Ions are also implanted into the side walls and the bottom of the groove. As such an example, FIG.
There is ion implantation shown in.

Next, as shown in FIG. 28, the oxide film 48 is removed and a sidewall insulating film 52 is formed on the sidewall of the groove 42. Subsequently, as shown in FIG. 29, the first substrate formed on the upper surface of the semiconductor substrate 41 between the grooves 42 and on the bottom surface of the groove 42.
Also, in order to control the threshold voltage Vth of the channel portion 91 of the second cell transistor 90, regions other than the memory cell portion are masked with the resist pattern 53 (see FIG. 7B), and in this state, the semiconductor substrate 41 is formed. For example, phosphorus ions 54 of opposite conductivity type are implanted. More specifically, the implantation amount is about 10 ¹³ cm ⁻² . The implantation energy is, for example, 20 to 50 keV. The implantation angle is about 0 ° in the direction normal to the semiconductor substrate 41. At this time, since the side wall of the groove 42 becomes a shadow of the ion implantation, phosphorus ions 54 are not implanted here.

Thus, if the threshold voltage Vth of all the channel portions 91 of the cell transistor 90 on the NAND side is set to a low value in advance, ions using boron ions will be used in the later ROM data writing step. Since the injection can be performed and the injection into the deep position can be performed relatively easily, the manufacturing efficiency can be improved.

Next, an extraction electrode 59 from the memory cell section
(See FIG. 25). Specifically, as shown in FIG. 30, high-concentration ions 5 of the opposite conductivity type to the semiconductor substrate 41 are used.
5 is injected to form the extraction electrode 59. The implantation of the ions 55 is performed with a dose of about 10 ¹⁵ cm ^-2 . At this time, the channel region is masked with the resist pattern 56 as shown in FIG.

Next, as shown in FIG. 31, the sidewall insulating film 52 is removed and a first gate oxide film 43 having a film thickness of about 5 to 30 nm is formed. Subsequently, as shown in FIG. 32, the first gate electrode 4 is formed through the first gate oxide film 43.
4 are formed in parallel with each other in the first direction. Figure 32
As shown in (a), the first gate electrode 44 enters the groove 42.

Next, as shown in FIG. 33, the film thickness is 5 to 30.
A second gate oxide film 45 having a thickness of about nm is formed, and a plurality of second gate electrodes 46 are formed in parallel in the first direction between the first gate electrodes 44 with the gate oxide film 45 interposed therebetween. Here, as the first and second gate electrodes 44 and 46, for example, a two-layer structure including an N ⁺ PolySi film having a thickness of 200 to 300 nm or a lower N ⁺ PolySi film having a thickness of 100 nm and an upper tungsten silicide film having a thickness of 100 nm is used. What is used. This point is the same as that of the above-mentioned embodiment.

Next, as shown in FIG. 34, the channel end of the cell transistor on the NAND side and the extraction electrode 5 described above.
9 are connected to each other at an angle of about 0 ° in the normal direction to the semiconductor substrate 41 (the implanted ions are
Inject (marked with Δ). More specifically, the high-concentration ions 58 of the conductivity type opposite to that of the semiconductor substrate 41 are applied 10 ¹⁵
The injection amount is about cm ^-2 . At this time, the region other than the channel portion is masked with the resist pattern 60.
The ions 58 are not implanted into the channel portion of the NOR-side cell transistor formed on the side wall of the groove 42. This is because the side wall is behind the ion implantation.

At this time, FIG. 35 (b) and FIG.
As shown in (b), it is assumed that there is a misalignment between the first gate electrode 44 and the second gate electrode 46 and a space 61 is generated between the gate electrodes 44 and 46. In such a case, the NOR formed on the side wall of the groove 42
Element isolation of the channel portion 101 of the side cell transistor 100 and the channel portion 9 of the NAND side cell transistor 90.
The connection between one channel becomes a problem.

Here, in the ninth embodiment, in order to improve the element isolation characteristics of the channel portion 101 of the cell transistor 100 on the NOR side, as shown in FIG. 35, a region other than the memory cell portion is formed with a resist pattern 62. For example, boron ions 200, which have the same conductivity type as the semiconductor substrate 41 and are masked, are implanted under the above conditions. That is, the boron ions 200 are further implanted where the boron ions 51 are implanted.
Therefore, element isolation is surely performed. The resist pattern 62 is formed on the side wall 6 of the groove 42 between the select lines on the select line side.
3 (see FIG. 25) is also opened, so that ions for element isolation are also implanted here. Therefore, element isolation between the upper surface and the bottom surface of the groove 42 is simultaneously performed.

On the other hand, as shown in FIG. 36, in the connection between the channels of the channel portion 91 of the cell transistor 90 on the NAND side, the source / drain is also formed in the space 61 by the implantation of the ions 58 (marked with Δ). Since the ions for implantation are implanted, the connection between the channels is surely made. Further, since the implantation amount of the ions 58 at this time is 10 ¹⁵ cm ^-2 as described above, this implantation cancels the ion implantation performed for element isolation between the upper surface and the bottom surface of the groove 42.

Subsequently, after a heat treatment process as a post process, FIG.
7 and 38, a high-concentration diffusion layer 64 of a conductivity type different from that of the semiconductor substrate 41 is formed, and the channel end of the cell transistor 90 on the NAND side and the extraction electrode 59 are connected. However, FIG. 37 shows a state in which a space due to misalignment is not generated in the first gate electrode 44 and the second gate electrode 46, and FIG. 38 is a state in which a space 61 is caused due to misalignment. Is shown.

Next, write ROM data to the NAND
The channel portion 91 of the side cell transistor 90 is performed. For this writing, as shown in FIG. 39, first, a writing resist pattern 65 patterned according to the ROM data to be written is formed, and from above the resist pattern 65, ions of the same conductivity type as the semiconductor substrate 41, for example, By using boron ions, the cell transistor 9 on the NAND side on the upper surface of the groove 42 is relatively low in implantation energy.
Ions 66 are implanted into the 0 channel portion 91 to write ROM data. On the other hand, the NA of the bottom of the groove 42
In the channel portion 91 of the cell transistor 90 on the ND side,
ROM by implanting ions 67 with relatively high implantation energy
Write data. Here, the upper surface of the groove 42 and the groove 4
2 In ion implantation for the bottom surface, because the implantation depth is different,
Injection of one does not affect the other.

Then, write the ROM data to NOR.
This is performed for the channel portion 101 of the cell transistor 100 on the side. For this writing, as shown in FIG. 40, first, a writing resist pattern 68 patterned according to the ROM data to be written is formed, and from above the resist pattern 68, ions of the same conductivity type as the semiconductor substrate 41, for example, Ion 69 is implanted into the sidewall of the groove 42 by using boron ions with an implantation energy intermediate between the implantation energy for the upper surface of the groove 42 and the implantation energy for the bottom surface of the groove 42. Also regarding this injection, the above injection is
Since the implantation depth is different, it does not affect the other.

As described above, the ion implantation performed on the upper surface, the lower surface and the side wall of the groove 42 at the time of writing the ROM data is as follows.
In either case, the implantation of one does not affect the other, so that the ROM data can be accurately written in each part of the groove 42.

Next, after a series of steps such as formation of an interlayer insulating film, formation of contact holes, formation of metal wiring, and formation of a protective film, the first half step of the semiconductor device of the ninth embodiment is completed. After that, an assembly process, which is the latter half process, is performed, whereby the semiconductor device of Embodiment 9 shown in FIG. 25 is manufactured.

(Embodiment 10) FIGS. 41 and 42 show Embodiment 10 of the semiconductor device of the present invention. This Embodiment 10
This semiconductor device has the same structure as the semiconductor device of the ninth embodiment, but the manufacturing process thereof is different as described below. However, FIG. 41 corresponds to the ROM data writing step shown in FIG. 39 of the ninth embodiment, and FIG. 42 corresponds to the ROM data writing step shown in FIG.

In the tenth embodiment, as shown in FIGS. 41 and 42, an interlayer insulating film 70 is laminated on the semiconductor substrate 41 so as to cover the first gate electrode 44 and the second gate electrode 46. Then, after the contact hole is opened in the interlayer insulating film 70 or after the metal wiring is further formed, ion implantation is performed with higher energy than the above, so that the upper surface, the bottom surface and the side wall of the groove 42 are formed. R for
Writing OM data.

The parts corresponding to those of the ninth embodiment are designated by the same reference numerals, and the detailed description thereof will be omitted.

Here, as the writing of the ROM data is performed in a later step, the step after the writing of the ROM data is shortened, and the manufacturing efficiency can be improved accordingly. Therefore, according to the tenth embodiment. Compared with the case of the ninth embodiment, there is an advantage that the manufacturing efficiency can be improved.

(Embodiment 11) FIGS. 43 to 46 show Embodiment 11 of the semiconductor device of the present invention. The semiconductor device of the eleventh embodiment has a structure in which the thickness of the first gate electrode 44 and the second gate electrode 46 is thinner than that of each of the above-described embodiments. However, FIG. 43 corresponds to the step of forming the first gate electrode shown in FIG. 32 of the ninth embodiment,
FIG. 44 corresponds to the step of forming the second gate electrode shown in FIG. Further, FIG. 45 shows the RO shown in FIG.
This corresponds to the M data writing process, and FIG. 46 corresponds to the ROM data writing process shown in FIG.
Corresponding parts are designated by the same reference numerals.

In the eleventh embodiment, particularly the gate electrode 4
This shows the case where the width of the groove 42 is wider than the thicknesses of 4 and 46 and the gate electrodes 44 and 46 cannot be completely flattened (see FIGS. 43A and 44A). Therefore, in the eleventh embodiment, the ion implantation step of the conductivity type opposite to that of the semiconductor substrate 41 shown in FIGS. 28 and 29 is omitted, and the writing of ROM data shown in FIG. 45 is performed in the channel section of the cell transistor 90 on the NAND side. Mask 165 when done at 91
Is used to implant ROM data by injecting ions 71 of the opposite conductivity type to the semiconductor substrate 41 such as phosphorus ions. Here, since the gate electrode film thicknesses of the upper surface of the groove 42 and the bottom surface of the groove 42 are substantially equal to each other as shown in FIG. 43A, the NAND of the upper surface of the groove 42 is formed by one ion implantation.
Channel portion 91 of the side cell transistor 90 and the groove 42
It is possible to simultaneously write the ROM data to the channel portion 91 of the cell transistor 90 on the NAND side on the bottom surface. Therefore, according to the eleventh embodiment, the number of steps can be reduced, and the manufacturing efficiency can be improved accordingly.

For writing ROM data to the channel portion 101 of the cell transistor 100 on the NOR side, as shown in FIG. 46, a resist pattern 68 patterned corresponding to the ROM data is formed, and in the same manner as above, For example, ion implantation of boron ions 69 is performed.

Also in the eleventh embodiment, since the ion implantation depth into the channel portion 91 of the NAND side cell transistor 90 and the ion implantation depth into the channel portion 101 of the NOR side cell transistor 100 are different, the influence of one influences the other. Therefore, the ROM data can be accurately written as in the eighth embodiment.

The parts corresponding to those of the ninth embodiment are designated by the same reference numerals, and the detailed description will be omitted.

(Embodiment 12) FIG. 47 shows Embodiment 12 of the semiconductor device of the present invention. The twelfth embodiment assumes a semiconductor device in which a space 61 exists between the first gate electrode 44 and the second gate electrode 46. In the twelfth embodiment as well, similar to the ninth embodiment, by implanting the ions 58 for forming the source / drain into the space 61, the high-concentration diffusion layer 64 is formed and the connection between the channels is established. Definitely done.

(Embodiment 13) FIG. 48 shows Embodiment 13 of the semiconductor device of the present invention. Also in the thirteenth embodiment,
Similar to the twelfth embodiment, a space 61 exists between the first gate electrode 44 and the second gate electrode 46, and the high-concentration diffusion layer 6 serving as the source / drain region is formed in the space 61.
4 are formed.

The thirteenth embodiment differs from the thirteenth embodiment having the groove 42 in the following points. That is,
In the thirteenth embodiment, the extraction electrode forming step shown in FIG. 30 is omitted, and the extraction electrode 59 is simultaneously formed in the source / drain region forming step shown in FIG.

Although the source / drain regions at the ends of the memory cell region are used as the extraction electrodes in FIG. 47, in the thirteenth embodiment, the extraction electrode wiring is formed by the depletion type cell transistor.

(Fourteenth Embodiment) FIG. 49 shows a fourteenth embodiment of the semiconductor device of the present invention. The semiconductor device of Embodiment 14 is different from the semiconductor devices of Embodiments 9 to 13 in that the gate electrode has one layer. However, FIG. 49 corresponds to the step before the ROM data writing ion implantation shown in FIG.

According to the fourteenth embodiment, the number of gate electrodes is 1.
Since it is a layer, it is inferior to those of the ninth to thirteenth embodiments in achieving higher integration, but has an advantage that the manufacturing process is simplified and the manufacturing efficiency can be improved.

(Fifteenth Embodiment) FIGS. 50 and 51 show a fifteenth embodiment of the semiconductor device of the present invention. This Embodiment 15
This semiconductor device has the same structure as the semiconductor device of the ninth embodiment except for the following points. Therefore, the corresponding parts will be denoted by the same reference numerals and the description thereof will be omitted, and only different parts will be described below.

As shown in FIG. 51, the first gate electrode 4
The channel portion of the first cell transistor 90 on the NAND side is formed on the side wall of the trench 42 below the third trench 41 on the upper surface of the semiconductor substrate 41 between the trenches 42 and the bottom surface of the trench 42 on the NOR side.
The channel portion of the cell transistor 100 is activated.
In addition, a NAND is formed on the sidewall of the groove 42 below the second gate electrode 46.
The channel portion 91 of the second cell transistor 90 on the side is formed, and the upper surface of the semiconductor substrate 41 between the grooves 42 and the groove 42 are formed.
The channel portion 101 of the NOR-side fourth cell transistor 100 is formed on the bottom surface of the. That is, in the semiconductor device of Embodiment 14, the formation positions of the channel portion 91 of the NAND-side cell transistor 90 and the channel portion 101 of the NOR-side cell transistor 100 with respect to the groove 42 are opposite to those of the ninth embodiment. ing.

Also in the semiconductor device of the fifteenth embodiment,
It is possible to obtain the same effect as that of the ninth embodiment.

(Sixteenth Embodiment) FIGS. 52 and 53 show a semiconductor device according to a sixteenth embodiment of the present invention. In the sixteenth embodiment, the first gate electrode 44 that becomes the first word line is formed on both side walls of the groove 42, and the second word line that becomes the second word line is formed on the bottom surface of the groove 42 and the upper surface of the semiconductor substrate 41 between the grooves 42. The gate electrodes 46 and 46 'are formed to thereby increase the integration of the memory cell.

More specifically, the sixteenth embodiment is different from the ninth to fifteenth embodiments in that the groove 42 is first described.
Are formed in the first direction. In addition, sidewall gate electrodes (first gate electrodes) 44, 44 which will be the first word lines are formed on both side walls of each groove 42 via the first gate insulating films 43, 43. Further, on the bottom surface of the groove 42, a bottom surface gate electrode (second gate electrode) 46 to be a second word line is erected via a second gate insulating film 45. Similarly, on the upper surface of the semiconductor substrate 41 between the trenches 42, the upper surface gate electrode 46 to be the second word line is formed via the second gate insulating film 45.

In addition, in the second direction orthogonal to the first direction, the channel portion 91 of the cell transistor 90 on the NAND side and the channel portion 101 of the cell transistor 100 on the NOR side are provided.
Are alternately formed over the upper surface, sidewalls and bottom surface of the semiconductor substrate 41 between the grooves 42.

In the sixteenth embodiment, as in the ninth embodiment, the memory cells can be further highly integrated as compared with the first embodiment.

(Other Embodiments) Although the overall contents of the illustrated embodiment are as described above, the method of the present invention is not limited to the order of the steps described in each of the above-mentioned embodiments, and each step may be arbitrarily performed. It can be done in order.

[0149]

As described above, according to the present invention, the NAND type and the N type are used.
Since the OR-type cell transistors are mixed and are arranged in the memory cell region on the semiconductor substrate so that the channel regions of the cell transistors are in contact with each other, the first direction which is the wiring direction of the word line and this The degree of integration of the cell transistors in the second direction orthogonal to, that is, high integration of the memory cells can be achieved. Therefore, according to the present invention, it is possible to significantly improve the capacity reduction of the semiconductor device including the mask ROM or the cost reduction due to the chip reduction.

By storing multi-valued information in the cell transistor on the NOR side, higher integration of the memory cell can be further achieved.

In particular, according to the semiconductor device of the fourth aspect, a plurality of grooves are formed on the semiconductor substrate, and the channel region of the cell transistor is formed on the semiconductor substrate upper surface, groove bottom surface and groove side wall between the grooves. Since the configuration is adopted, more cell transistors can be provided for the same area in plan view, and thus the degree of integration of the memory cells can be further improved.

In particular, according to the semiconductor device of the fifth aspect, either the first word line or the second word line is formed on the upper surface of the semiconductor substrate and the bottom surface of the groove between the grooves with an insulating film interposed therebetween. According to the structure in which the other side is formed on the side wall of the groove, the wiring pitch in plan view can be further reduced, so that high integration can be further achieved.

Further, according to the method of manufacturing a semiconductor device of the present invention, the above steps can be performed in an arbitrary order,
For example, if the ion implantation process for writing data is performed simultaneously on the NAND side and the NOR side using one mask, only one implantation process is required, so that the process can be simplified. The manufacturing efficiency of the device can be improved.

Further, the writing of the ROM data of the mask ROM to which the present invention is applied is performed in a later step,
Since the process after writing the ROM data is shortened, if this process is performed at the end of the above process, the manufacturing efficiency can be improved.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a semiconductor device of the present invention according to a first embodiment.

FIG. 2 is a plan view of the semiconductor device of the present invention according to the first embodiment.

FIG. 3 is a graph showing cell current characteristics of the cell transistor of the semiconductor device of the present invention according to the first embodiment.

FIG. 4 is a NAND of the semiconductor device of the present invention according to the first embodiment.
FIG. 7 is an operation explanatory diagram illustrating a read operation of the cell transistor on the side.

FIG. 5 is an operation explanatory diagram illustrating a read operation of the NOR-side cell transistor of the semiconductor device of the present invention according to the first embodiment.

6A to 6C are process diagrams showing a cross-section taken along the line AA 'in FIG. 2 and showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 7 is a process diagram showing the method for manufacturing the semiconductor device of the present invention according to the first embodiment, showing the cross section along the line AA ′ in FIG. 2;

FIG. 8 is a process diagram showing a cross-section taken along the line AA ′ of FIG. 2, showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.

9 (a), (b), (c) and (d) are cross sections taken along line AA ', line BB', line CC 'and line BB' of FIG. 2, respectively. 4A to 4C are process diagrams showing a cross-sectional view showing a method for manufacturing the semiconductor device of the present invention according to the first embodiment.

10 (a), (b), (c) and (d) are cross sections taken along the line AA ', line BB', line CC 'and line BB' of FIG. 2, respectively. 4A to 4C are process diagrams showing a cross-sectional view showing a method for manufacturing the semiconductor device of the present invention according to the first embodiment.

11A and 11B are process diagrams showing the method for manufacturing the semiconductor device of the present invention according to the first embodiment, both showing the cross section along the line AA ′ of FIG. 2.

12 (a), (b), and (c) are A of FIG. 2, respectively.
6A to 6C are process diagrams showing the method for manufacturing the semiconductor device according to the first embodiment, showing the cross section along the line A-A ', the cross section along the line BB', and the cross section along the line CC '.

FIG. 13 is a process diagram showing the method for manufacturing the semiconductor device of the present invention according to the second embodiment, which shows the cross section along the line CC ′ of FIG. 2;

FIG. 14 is a process diagram showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention, which is taken along the line CC ′ of FIG. 2;

FIG. 15 is a process diagram showing the method for manufacturing the semiconductor device of the present invention according to the second embodiment, showing the cross section along the line CC ′ of FIG. 2;

FIG. 16 is a plan view of the semiconductor device of the present invention according to the third embodiment.

17 is a second embodiment showing a cross section taken along line DD ′ of FIG.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

FIG. 18 is a plan view of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 19 is a fourth embodiment showing a cross section taken along line EE ′ of FIG. 18;
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

20 is a cross-sectional view taken along line EE ′ of FIG. 18, showing Embodiment 4;
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

FIG. 21 is a fifth embodiment showing a cross section taken along line DD ′ of FIG. 16;
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

FIG. 22 is a sixth embodiment showing a cross section taken along line EE ′ of FIG. 18;
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

23A and 23B are process diagrams showing the method for manufacturing the semiconductor device of the present invention according to the seventh embodiment, showing the AA ′ line cross section and the BB ′ line cross section of FIG. 2, respectively.

FIG. 24 is a process drawing showing the manufacturing method of the semiconductor device of the present invention according to the eighth embodiment.

FIG. 25 is a plan view of a semiconductor device of the present invention according to Embodiment 9.

26 is a ninth embodiment showing a cross section taken along the line AA ′ of FIG. 25.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

27 (a) and (b) are respectively AA ′ of FIG.
FIG. 11 is a process diagram showing a method for manufacturing a semiconductor device of the present invention according to Embodiment 9, showing a line cross section and a BB ′ line cross section.

FIG. 28 is a ninth embodiment showing a cross section taken along the line AA ′ of FIG. 25.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

29 (a) and (b) are respectively AA ′ of FIG.
FIG. 11 is a process diagram showing a method for manufacturing a semiconductor device of the present invention according to Embodiment 9, showing a line cross section and a BB ′ line cross section.

30 (a) and 30 (b) are each AA 'in FIG.
FIG. 11 is a process diagram showing a method for manufacturing a semiconductor device of the present invention according to Embodiment 9, showing a line cross section and a BB ′ line cross section.

31 is a ninth embodiment showing a cross section taken along the line AA ′ of FIG. 25.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

32 (a) and (b) are respectively AA ′ of FIG.
FIG. 11 is a process diagram showing a method for manufacturing a semiconductor device of the present invention according to Embodiment 9, showing a line cross section and a BB ′ line cross section.

33 (a) and (b) are respectively CC 'of FIG.
FIG. 11 is a process diagram showing a method for manufacturing a semiconductor device of the present invention according to Embodiment 9, showing a line cross section and a BB ′ line cross section.

34 is a ninth embodiment showing a section taken along line BB ′ of FIG. 25. FIG.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

FIG. 35 (b) is a sectional view taken along line BB ′ of FIG.
9A and 9B show sectional views taken along line DD ′ of FIG.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

FIG. 36 (b) is a sectional view taken along line BB ′ of FIG.
9A and 9B show sectional views taken along line DD ′ of FIG.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

FIG. 37 is a ninth embodiment showing a cross section taken along the line BB ′ of FIG. 25.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

38 (b) is a sectional view taken along the line BB ′ of FIG. 25 (a).
9A and 9B show sectional views taken along line DD ′ of FIG.
4A to 4D are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to the first embodiment.

FIGS. 39 (a), (b), and (c) are sectional views taken along the line AA ′, BB ′, and CC ′ of FIG. 25, respectively, according to the ninth embodiment of the present invention. 8A to 8C are process diagrams showing a method for manufacturing a semiconductor device.

FIGS. 40 (a), (b), and (c) are cross-sectional views taken along the line AA ′, the line BB ′, and the line CC ′ of FIG. 25, respectively. 8A to 8C are process diagrams showing a method for manufacturing a semiconductor device.

41 (a), (b), (c) are cross-sectional views taken along line AA ′, BB ′, and CC ′ of FIG. 25, respectively, according to the tenth embodiment of the present invention. 8A to 8C are process diagrams showing a method for manufacturing a semiconductor device.

42 (a), (b), (c) are cross-sectional views taken along line AA ′, BB ′, and CC ′ of FIG. 25, respectively, according to the present invention. 8A to 8C are process diagrams showing a method for manufacturing a semiconductor device.

43 (a) and (b) are respectively AA ′ of FIG.
13A to 13C are process diagrams showing a method for manufacturing the semiconductor device according to the eleventh embodiment, showing a line cross section and a BB ′ line cross section.

44 (a) and (b) are respectively CC 'of FIG.
13A to 13C are process diagrams showing a method for manufacturing the semiconductor device according to the eleventh embodiment, showing a line cross section and a BB ′ line cross section.

FIGS. 45 (a), (b) and (c) are cross-sectional views taken along the line AA ′, the line BB ′ and the line CC ′ of FIG. 25, respectively. 8A to 8C are process diagrams showing a method for manufacturing a semiconductor device.

FIGS. 46 (a), (b), and (c) are cross-sectional views taken along line AA ′, BB ′, and CC ′ of FIG. 25, respectively, according to an embodiment of the present invention. 8A to 8C are process diagrams showing a method for manufacturing a semiconductor device.

FIG. 47 is a first embodiment showing a cross section taken along the line BB ′ of FIG. 25.
6A to 6C are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to No. 2.

48 is a first embodiment showing a cross section taken along line BB ′ of FIG.
6A to 6C are process diagrams showing a method for manufacturing a semiconductor device of the present invention according to No. 3.

FIG. 49 is a process drawing showing the manufacturing method of the semiconductor device of the present invention according to the fourteenth embodiment.

FIG. 50 is a plan view of the semiconductor device of the present invention according to the fifteenth embodiment.

51 (a) and 51 (b) are each EE 'of FIG.
16A and 16B are process diagrams showing a method for manufacturing the semiconductor device of the present invention according to the fifteenth embodiment, showing a line cross section and a line FF ′ cross section.

52 is a plan view of the semiconductor device of the present invention according to the fifteenth embodiment. FIG.

53 (a) and (b) are respectively GG 'of FIG. 52.
16A and 16B are process diagrams showing a method for manufacturing the semiconductor device of the present invention according to the sixteenth embodiment, showing the line section and the HH 'line section.

FIG. 54 shows a first conventional example, (a) is a plan view,
(B), (c), (d) is a BB 'line sectional view, a CC' line sectional view, and a DD 'line sectional view of (a), respectively.

FIG. 55 is a plan view showing a second conventional example,
(B) and (c) are cross-sectional views taken along the line AA ′ of (a),
BB 'sectional view taken on the line.

FIG. 56 is a plan view showing a third conventional example,
(B) and (c) are cross-sectional views taken along the line AB of (a), respectively.
-D line sectional view.

[Explanation of symbols]

1, 41 Semiconductor substrate 7, 44 First gate electrode (first word line) 10, 46 Second gate electrode (second word line) 42 groove 90 NAND-side cell transistor 91 Channel part of cell transistor on NAND side 100 NAND cell transistor 101 Channel part of cell transistor on NAND side 110 memory cell area

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-6-97395 (JP, A) JP-A-6-318683 (JP, A) JP-A-8-274191 (JP, A) JP-A-9- 167806 (JP, A) JP-A-7-142610 (JP, A) JP-A-5-102436 (JP, A) JP-A-4-226071 (JP, A) JP-A-4-354159 (JP, A) JP-A-5-235308 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/112

Claims (8)

(57) [Claims] 1. A semiconductor device having a memory cell portion in which transistors are formed in a matrix on a semiconductor substrate, wherein a plurality of word lines also serving as gate electrodes are formed on the semiconductor substrate via an insulating film. Are formed parallel to each other, and the channel regions of the transistor are all in contact with each other in a portion located below the word line of the semiconductor substrate, and the transistor has at least four types of threshold voltages having different sizes. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the channel regions arranged in a second direction orthogonal to the word lines are all in contact with each other. 3. A semiconductor device having transistors, each of which has memory cell portions formed in a matrix on a semiconductor substrate, wherein a plurality of transistors are formed in parallel in a first direction with an insulating film interposed therebetween. A first transistor having a word line and a plurality of transistors connected in series in a second direction orthogonal to the word line and having a gate electrode as the gate electrode, the first transistor being arranged in a plurality of columns in the first direction A column, a plurality of transistors sharing the gate electrode with each transistor of the first transistor column, having a channel region of each transistor as a source / drain, and having different threshold voltages from each other. A second transistor array connected in parallel between one transistor array, and threshold voltages of all transistors in the second transistor array Is higher than the threshold voltage of the transistors in the first transistor row. 4. A plurality of trenches are formed in parallel with each other in the second direction of the semiconductor substrate, and each of the channel region of each transistor of the first transistor row or the channel region of each transistor of the second transistor row is formed. 4. The semiconductor device according to claim 1, wherein one of them is formed on a top surface and a bottom surface of the semiconductor substrate between the grooves, and the other is formed on a side wall of the groove. 5. The word line comprises a first word line and a second word line, and a plurality of grooves are formed parallel to each other in a first direction of a semiconductor substrate, and the first word line or the second word line is formed. One of the word lines is formed on the upper surface of the semiconductor substrate and the bottom surface of the groove between the trenches via the insulating film, and the other is formed on the sidewall of the trench, and the channel region of each transistor of the first transistor row and the The channel region of each transistor of the second transistor row is formed on the upper surface of the semiconductor substrate between the grooves, on the side wall of the groove and on the bottom surface of the groove, and extends in the second direction. The semiconductor device according to claim 2 or claim 3. 6. A plurality of channel regions of NAND-side cell transistors extend in parallel in a second direction on a semiconductor substrate, and extend in the second direction between channel regions of the NAND-side cell transistors. A method of manufacturing a semiconductor device, wherein a channel portion of an existing NOR-side cell transistor is formed, and a channel region of the NAND-side cell transistor serves as a source / drain of the NOR-side cell transistor, the method comprising: A step of forming a plurality of first gate electrodes, which are gate electrodes of the NAND-side cell transistor and the NOR-side cell transistor, in parallel through a first gate insulating film in a first direction orthogonal to the second direction. And a NAND-side cell transistor and NOR between the first gate electrodes on the semiconductor substrate via a second gate insulating film. Second to the gate electrode of the cell transistor
A step of forming a gate electrode, and ion implantation for forming a high-concentration diffusion layer to be a lead-out electrode of a memory cell region composed of the NAND-side cell transistor and the NOR-side cell transistor at the end of the memory cell region A step of performing, a step of implanting ions into the memory cell area to form a source / drain area of a cell transistor on the NAND side, a step of connecting the extraction electrode and the end of the memory cell area, a step of connecting the NOR side Implanting ions into the channel region of the cell transistor to control the threshold voltage of the cell transistor, and implanting ions into the channel region of the cell transistor to control the threshold voltage of the NAND side cell transistor And the step of writing data to the cell transistor on the NAND side. A step of implanting ions into the channel region of the cell transistor, and a step of implanting ions into the channel region of the cell transistor in order to write data to the cell transistor on the NOR side. A method of manufacturing a semiconductor device, which is performed in an arbitrary process order. 7. A plurality of grooves are formed in parallel with each other in the second direction of the semiconductor substrate, and ions are implanted into the upper surface of the semiconductor substrate, the groove bottom surface and the groove side wall between the grooves, and the semiconductor between the grooves is formed. The method further includes the step of forming one of the channel region of the NAND-side cell transistor and the channel region of the NOR-side cell transistor on the upper surface of the substrate and the bottom surface of the groove, and forming the other on the side wall of the groove. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the steps are performed in an arbitrary order. 8. A plurality of trenches are formed in parallel with each other in the first direction of the semiconductor substrate, and one of the first gate electrode and the second gate electrode is provided between the trenches with an insulating film interposed therebetween. Of the semiconductor substrate upper surface and the groove bottom surface, and the other is formed on the groove side wall, and the NAND side cell transistor channel region and the NOR side cell transistor channel region are formed between the semiconductor substrate upper surface and the groove side wall. 7. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming on the bottom surface of the groove, and performing this step and each step in an arbitrary order.