JP3525578B2 - Frequency division multiplex signal generation device and decoding device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency division multiplex signal generation apparatus and a decoding apparatus, and more particularly to orthogonal frequency division multiplexing (OFDM) of a coded digital video signal or the like in a limited frequency band.
The present invention relates to a frequency division multiplex signal generation device and a decoding device which are converted into a signal and transmitted and received.

[0002]

2. Description of the Related Art One of the methods for transmitting coded digital video signals in a limited frequency band is 25
6 Quadrature Amplitude Modul (QAM)
ation) and other multi-value modulated digital information is transmitted as an OFDM signal using a large number of carriers, the OFDM method has been known from the past due to its features such as resistance to multipath, resistance to interference, and relatively good frequency utilization efficiency. Has been. This OFDM system is a system in which a large number of carriers are arranged orthogonally and independent digital information is transmitted on each carrier. The phrase "carriers are orthogonal to each other" means that the spectrums of adjacent carriers become zero at the frequency position of the carrier.

According to this OFDM system, since a guard band period (guard interval) is set and information of the period is transmitted redundantly, transmission distortion caused by multipath of radio waves can be reduced. That is, in the reception of this OFDM signal, the amplitude and phase modulation components of the signal transmitted within the symbol period are detected, and the information value is decoded by these levels, so the signal of the first guard interval period is By removing and decoding
Since the frequency components of the multipath signal in the same symbol section and the signal to be received are the same, decoded digital data with less transmission distortion can be transmitted in a relatively narrow frequency band.

[0004]

However, the above OF
In a conventional frequency division multiplexing signal generation device that generates a DM signal, a large amount of power is rarely generated because an OFDM signal that is formed by combining a large number of information carriers is not provided with a measure against peak power that occurs instantaneously. It may be done. For example, the power of an OFDM signal using 256 information carriers is an average power that is 256 times the power of one information carrier, so if the maximum amplitude voltage values of all the information carriers are generated in agreement, , 25 of one carrier
Transmission power of 6 times (or D / A converter, dynamic range of A / D converter, linearity of analog system, etc.) is required. Conversely speaking, the signal-to-noise ratio (S / N) per carrier decreases accordingly.

The probability that the phases of all the carriers are the same is very small and hardly occurs in reality, but the average power value is set to a low value with a margin, and the transmission power device also has an average power of 10 to 20 times. A device that can generate a large output signal with a certain margin is used, and it is considered that even a rarely generated high power signal can be transmitted without being saturated. Therefore, the conventional frequency division multiplex signal generator has a problem that the entire device is expensive and becomes large in size.

The present invention has been made in view of the above points. By reducing the peak power of the generated frequency division multiplexed signal, the transmitter is reduced in size and weight, including the power supply of the transmitter. It is an object of the present invention to provide a frequency division multiplexed signal generation device and a decoding device to be obtained.

[0007]

In order to achieve the above object, the present invention provides an inverse discrete signal for a transmission information signal input to a plurality of input terminals and a transmission mode signal input to a specific input terminal. Fourier transform operation is performed to generate an in-phase signal and a quadrature signal, and either the generated in-phase signal or quadrature signal is generated.
At that time, when the signal value is equal to or more than a predetermined set value,
Whether it is a specific state that continues for more than a preset period
An arithmetic unit having a function of detecting a frequency division multiplexed signal generating apparatus der and an output buffer which temporarily stores the output signal of the calculating unit continuously read frequency division multiplexed signal
Thus, the output buffer outputs an output stop signal having a true value to the arithmetic unit when the accumulated amount is larger than the first predetermined value, and outputs a true value when the accumulated amount is smaller than the second predetermined value. The output request signal of the value of is output to the arithmetic unit, and the arithmetic unit transmits the transmission information signal and the transmission model.
Mode signal is calculated with the initially set frequency allocation and in-phase communication is performed.
Signal and quadrature signal, and then the generated sync signal and
And whether or not the quadrature signal is in a specific state,
When the specific state is not detected, the sync signal and the quadrature signal generated when the output stop signal is false are output to the output buffer, and when the output stop signal is true, the generated sync signal
And the output of the quadrature signal is stopped, a specific condition is detected,
And when the output request signal is false, the frequency allocation is
The transmission information signal and the frequency allocation are deviated from the frequency allocation.
The transmission mode signal with the information indicating
After generating the phase signal and the quadrature signal, the generated synchronization signal
Detect whether signal and quadrature signal are in a specific state
Repeat until the specific condition is no longer detected
However, the specific condition is detected and the output request signal is true.
, The in-phase signal and quadrature signal at that time
Among the results, the calculation result having the smallest peak value is output to the output buffer.

Further , the arithmetic unit detects a specific state,
And when the output request signal is false, the previous frequency allocation
One of the real and imaginary parts of the transmitted information signal
The allocation for the other is left unchanged, but the allocation for the other is shifted by a predetermined amount
Frequency allocation indicates changes in transmission information signal and frequency allocation
The transmission mode signal with added information is recalculated and the in-phase signal and
And a quadrature signal.

[0009]

[0010]

Further, in the decoding apparatus of the present invention, the frequency division multiplex signal generated by the frequency division multiplex signal generation apparatus is received, the discrete Fourier transform operation is performed, and the information indicating the change in the frequency allocation included in the transmission mode signal is received. , The frequency allocation is restored to restore the transmission information signal.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. First, before describing the frequency division multiplex signal generation apparatus of the present invention, an outline of an OFDM signal transmission apparatus to which the frequency division multiplex signal generation apparatus of the present invention is applied will be described. Here, transmission information is transmitted as an OFDM signal using 256 carriers. Further, in order to facilitate the design of the analog signal system in the latter stage, it is assumed that the double oversampling is used and the 512-point inverse discrete Fourier transform (IDFT) operation is executed to generate the OFDM signal.

In this transmitting apparatus, for example, digital data to be transmitted such as a digital video signal and an audio signal compressed by an encoding method such as an MPEG method which is a color moving image encoding display method is supplied to an arithmetic unit . This computing unit performs inverse discrete Fourier transform (IDF) on the input digital data.
T) Computation is performed to generate an in-phase signal (I signal) and a quadrature signal (Q signal). This arithmetic unit operates at a sample clock frequency higher than a predetermined frequency bandwidth. When transmitting transmission information with 256 carriers, double oversampling is used and 512-point IDFT operation is performed to generate a signal. The input allocation to the IDFT calculation unit at this time is as follows if the numbers are sequentially assigned in the input frequency alignment type.

An information signal is provided which modulates n = 0 to 128 carriers.

N = 129 to 383 Carrier level 0
And does not generate a signal.

N = 384-511 An information signal for modulating a carrier is provided.

That is, the number of input terminals of the IDFT calculation unit is 512 for the real part (R) signal and 512 for the imaginary part (I) signal, of which 127 (n = 1) to 127 are the first.
127 pieces in total up to the nth (n = 127) and 1 pieces in total from the 385th (n = 385) to the 511th (n = 511)
Information signals are input to 27 input terminals each, and 0
The DC voltage (constant) is input to the th (n = 0) th input terminal and transmitted at the center frequency of the carrier wave.
For example, a fixed voltage for the pilot signal is input to the n-th (n = M / 4) and 384-th (n = 3M / 4) input terminals, and the frequency at both ends, which is half the Nyquist frequency, is input. Is transmitted on a carrier wave.

Here, a total of 1 from the 1st to the 128th
The input information of the 28 input terminals is transmitted by the information transmitting carrier wave on the upper side (higher band side) of the central carrier wave frequency F0.
The input information from a total of 128 input terminals from the 1st to the 511th is transmitted on the information transmission carrier below the center carrier frequency (low side). Also, the remaining 129th to 38th
0 is input to the third input terminal (set to the ground potential) so that the carrier wave in that portion is not generated (not used for data transmission).

That is, in the arithmetic unit, the transmission information from the external system is "AB", "CD", "E" in units of 8 bits.
When F ”,“ GH ”, ... (each character represents a group of 4 bits) come in order, the 1st to 128th input terminals and the 384th to 511th real part input terminals and imaginary part input A 4-bit signal is input to each terminal, and in this case, the carrier number, data of the real part input terminal, and data of the imaginary part input terminal are assigned in the following first arrangement.

[0020]

[Table 1] Furthermore, since the reference data for the amplitude / phase correction on the receiving side and the synchronization data etc. (including the transmission mode) are inserted on the specific carrier, the data corresponding to these will be written later. It is transferred to another carrier.

The IDFT operation result (I signal and Q signal) of the above operation unit is bursted as a time axis signal (I signal and Q signal) of which 256 pieces of input information are 512 points in one IDFT operation. On the other hand, since it is generated in the subsequent circuit, it is necessary to perform constant and continuous signal processing. Therefore, in order to adjust the time difference between the two, the IDFT operation result is temporarily stored in the output buffer.

I read continuously from the output buffer
The signal and the Q signal are quadrature-modulated by quadrature modulating means, and each of 257 waves (128 positive and negative pairs of carriers and one central carrier) of information carriers having different frequencies are 256Q.
After being converted into an AM-modulated OFDM signal, it is frequency-converted into a transmission frequency band by a frequency converter, further power-amplified, etc. in the transmitting section and radiated from the antenna.

In the frequency division multiplex signal receiver,
After the orthogonal demodulation and the DFT calculation, the DFT calculation result is corrected according to the reference data of the specific carrier.

Next, to explain the embodiment of the present invention, FIG. 1 shows a block diagram of one embodiment of the present invention. In the figure, the arithmetic unit 1 is embodied by a digital signal processor (DSP), and a transmission information signal (such as the digital data) is transmitted from an external system (not shown).
Are supplied to a plurality of input terminals, and a transmission mode signal is supplied to a specific input terminal to perform the IDFT operation described above. At this time, the frequency allocation information indicating the frequency allocation of the transmission information is “x” in the carrier wave for setting the transmission mode signal.
Insert 0 "(x is used in other modes), ie
In the normal first frequency arrangement shown in Table 1, the lower 4 bits of the 8-bit transmission mode signal are set to "0".

The IDFT operation result of the operation unit 1 is output to the output buffer 2 under the control of the output stop signal a and the output request signal b from the output buffer 2. Here, the storage amount of the output buffer 2 will be described. Regarding the relationship between the IDFT calculation processing time A and the transmission speed B, from the viewpoint of speed performance and cost of the IDFT calculation processing time A, (1/2) × B <A <B (unit indicates required time) is appropriate. Is. In this case, if the storage amount of the output buffer 2 is only about 1 symbol, the calculation unit 1 again performs the IDFT.
There is no time margin to calculate. As will be described later, the calculation unit 1 performs the IDFT calculation again under a predetermined condition. Therefore, the storage amount of the output buffer 2 is set to about 10 symbols, which causes a time margin to intermittently perform about 10 IDFT calculations.

Next, the relationship among the output stop signal a, the output request signal b, and the buffer storage amount will be described with reference to FIG.

The buffer storage amount of the output buffer 2 is set to an empty state (empty), a semi-empty state (all-most empty), a semi-storage state (half), a semi-full state (all-most full), and a full state (full). When divided, the output stop signal a, as shown in FIG.
High level (true) only in full and full states, output request signal b is high level (true) only in empty and almost-empty empty states, as shown in FIG. Then it is low level (false).

For example, the output buffer 2 prepares about 10 symbols of the OFDM signal for the buffer accumulation amount for the above reason, and when the accumulation amount is less than about 1 symbol, the output request signal b is set to true (all-most). -Empty boundary), and when the buffer storage amount is about 9 symbols or more, the output stop signal a is set to true (all-most-full boundary).

These two signals a and b may be generated by an up / down counter that counts up with a write clock to the output buffer 2 and counts down with a read clock, and an FIF having those functions.
O-RAM (for example, integrated device
Technology Inc. IDT72245LB) or the like. The transmission speed of the entire device is controlled by the read clock of the output buffer 2, and thus the generation of transmission data is controlled by these two signals.

The arithmetic unit 1 has a function of inspecting a state of whether a value equal to or larger than a predetermined set value continues for a period equal to or larger than the predetermined set value in one of the I signal and the Q signal as the IDFT calculation result. . If this state is not detected, the operation unit 1 outputs the operation result to the output buffer 2 when the output stop signal a input from the output buffer 2 is false. Then, the buffer storage amount of the output buffer 2 increases. As a result, when the buffer storage amount becomes about 9 symbols or more, the output stop signal a becomes true (all-most
Full boundaries).

As a result, the output of the IDFT calculation result of the calculation unit 1 is stopped. However, since the accumulated information in the output buffer 2 is continuously read, the buffer accumulated amount decreases. As a result, the output buffer 2 sets the output stop signal a to false at the time when the buffer storage amount becomes equal to or less than the predetermined value. Therefore, the arithmetic unit 1 waits for this state and the IDFT of the next symbol is waited for.
The calculation result is output to the output buffer 2. Hereinafter, the same state as above is repeated. The frequency arrangement in this state in which neither the I signal nor the Q signal has a value equal to or greater than a predetermined set value for a period longer than or equal to the predetermined set value is the first arrangement.

On the other hand, when the arithmetic unit 1 detects the state of whether the value of the predetermined value or more continues for the period of the predetermined value or more in either the I signal or the Q signal, the arithmetic unit 1 has a plurality of units. It is determined that the peak power is generated when the phases of the carrier waves of 1 are coincident with each other, and the following operation is performed. These operations can be performed until the output request signal b input from the output buffer 2 becomes true at the time when the buffer storage amount decreases to about 1 symbol or less.

The computing unit 1 assigns the frequency to the IDFT computation of the transmission information as the following second allocation.

[0034]

[Table 2] Then, as the frequency allocation information, "x1" is inserted in the carrier wave for setting the transmission mode. In this way, the calculation unit 1
Repeats IDFT for the same transmission information although the frequency allocation is different.
Calculate The calculation result of the IDFT calculation again is output after confirming the false state of the output stop signal a when the above state is not detected.

Here, when the peak value of the predetermined value or more is detected in the calculation result of the second arrangement and the output request signal b is false, the calculation unit 1 further allocates the frequency to the IDFT calculation of the transmission information. The third arrangement is carried out by shifting a predetermined amount, "x2" is inserted in the carrier wave for setting the transmission mode, and the IDFT calculation is performed again.

When the calculation result of the third arrangement does not detect the above state, the third result is immediately output. If detected, the calculation is further shifted. This operation is repeated until the above condition is no longer detected. Here, when the output request signal b becomes true, the one with the smallest peak value is output from the plurality of calculation results calculated so far. this is,
This is to prevent the output buffer 2 from becoming empty. As a result, the phase of the information carrier is shifted, and the possibility of the peak power being generated can be greatly reduced.

Normally, in the stable state, the output buffer 2
The buffer storage amount of is about 9 symbols. In such a state, it is possible to try the IDFT calculation about 10 times including the first time. In each trial, shift the data one by one,
Let's try the IDFT operation. If 4 bits of frequency allocation information are prepared, 16 kinds of information (that is, 16 kinds of frequency allocation) can be expressed, but since it is rarely necessary to change 16 kinds of frequency allocation, 4 bits is sufficient. .

The present invention is not limited to the above embodiment, and other embodiments are possible. For example, the 8-bit transmission information input from the external system to the arithmetic unit 1 is “AB”, “CD”, “EF”, “G”.
When H ", ...," YZ "are input in this order, the frequency allocation for the IDFT calculation of the transmission information may be shifted only by one imaginary part as follows.

[0039]

[Table 3] As another example, it is conceivable that half of the transmission information is transferred by the first symbol and the other half is transferred by the second symbol. Null data is inserted in the place where the data is removed. As the null data, both the real number part and the imaginary number part are assigned such that the phase is random at less than half the signal points with respect to the maximum value of the predetermined signal point arrangement so that the amplitude does not become too large. However, if the amplitude is too small, the average power changes abruptly, which is not preferable.

The IDFT operation result (I signal and Q signal) of the operation unit 1 accumulated in the output buffer 2 under the control of the output stop signal a and the output request signal b from the output buffer 2.
Is read at a predetermined constant continuous clock, and the data is output to a quadrature modulator (not shown) as described above.

The receiving device (decoding device) receives the frequency division multiplex signal generated by the frequency division multiplex signal generating device and performs a discrete Fourier transform operation to change the frequency allocation included in the transmission mode signal. Based on the information shown, the frequency allocation change can be identified and undone to restore the transmitted information signal.

[0042]

As described above, according to the present invention,
Either the in-phase signal or the quadrature signal generated by the arithmetic unit
The period during which the signal value is greater than or equal to the preset value
It is checked whether it is a specific state that continues for a set period or longer.
When the specific state is detected, the frequency allocation for the IDFT operation of the transmission information signal is changed and the IDFT operation is performed again, so that the operation unit has a very low probability with a simple hardware configuration. It is possible to reduce the peak value of the frequency-division multiplexed signal that is output, so that the calculation unit that does not require a high processing speed and an inexpensive electric system (D / A converter, proper dynamic range of A / D converter) The whole device can be configured by
The size and weight of the transmission device can be reduced, including the power supply device of the transmission device, and the S / N (reliability) of the frequency division multiplexed signal can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of output signals of the output buffer of FIG.

[Explanation of symbols]

1 computing unit 2 output buffer

Continuation of the front page (56) Reference JP-A-9-18444 (JP, A) JP-A-9-18433 (JP, A) JP-A-8-274748 (JP, A) JP-A-7-143098 (JP , A) JP 5-130191 (JP, A) JP 8-340361 (JP, A) Special Table 6-504175 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) H04J 11/00

Claims (3)

(57) [Claims] 1. A transmission information signal input to a plurality of input terminals and a transmission mode signal input to a specific input terminal,
Inverse discrete Fourier transform operation is performed to generate an in-phase signal and a quadrature signal, and the generated in- phase signal or quadrature signal
At that time, when the signal value is equal to or more than a predetermined set value,
Whether it is a specific state that continues for more than a preset period
A frequency division multiplex signal generation device having an arithmetic unit having a function of detecting, and an output buffer for temporarily accumulating the output signal of the arithmetic unit and continuously reading the frequency division multiplex signal , wherein the output buffer is , A true value output stop signal is output to the arithmetic unit when the storage amount is larger than the first predetermined value, and a true value output request is output when the storage amount is smaller than the second predetermined value. The signal is output to the calculation unit, and the calculation unit outputs the transmission information signal and the transmission mode signal to the maximum.
The in-phase signal and
After generating the exchange signal, the generated synchronization signal and quadrature signal
It is detected whether or not the specified state is
When the constant state is not detected, it outputs the synchronization signal and the quadrature signal is generated when the output stop signal is false in the output buffer, wherein when the output stop signal is true the
The output of the generated the synchronization signal and the quadrature signal is stopped, before
A specific condition is detected, and the output request signal is false.
, The frequency allocation is shifted from the previous frequency allocation.
The transmission information signal and the information indicating the change in frequency allocation.
The added transmission mode signal is calculated again, and the in-phase signal and
After generating the quadrature signal, the generated synchronization signal and quadrature
It is possible to detect whether or not the signal is in the specific state.
And repeat until the specific condition is no longer detected
However, the specific condition is detected, and the output request signal is received.
When the signal is true, the in-phase and quadrature signals
Among the calculation results, the calculation result with the smallest peak value is output.
A frequency-division multiplex signal generation device which outputs to a power buffer . 2. The arithmetic unit detects the specific state.
If the output request signal is false,
The real and imaginary parts of the transmission information signal in number allocation
The allocation for one side remains unchanged and the allocation for the other side remains unchanged.
The transmission information signal and the frequency are
Replay the transmission mode signal with information indicating the change in allocation.
2. The frequency division multiplex signal generation device according to claim 1, wherein the in-phase signal and the quadrature signal are generated by calculation . 3. Information indicating a change in the frequency allocation included in the transmission mode signal, which receives the frequency division multiplexed signal generated by the frequency division multiplexed signal generation device according to claim 1 and performs a discrete Fourier transform operation on the frequency division multiplexed signal. A frequency division multiplex signal decoding apparatus which restores the transmission information signal by restoring frequency allocation based on the above.