JP3510749B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a power semiconductor device in which a power section and a control section are formed on the same semiconductor substrate.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view of a conventional power MOSFET having a general control section and a power section. N +
The type semiconductor substrate 1 has an N − type epitaxial layer 2 on its surface, and constitutes a part of the drain region of the power section. The drain region 2 of the power portion is provided with a number of regularly arranged P type body regions 5, and in the body region 5, a ring-shaped N + type source region 4 is formed. . A gate electrode 7 made of polycrystalline silicon is formed on the body region 5 to be the channel region 3 via an insulating layer, and a metal such as aluminum is vapor-deposited via the gate insulating film to commonly connect the source regions 4 to each other. The source electrode 8 is formed.

On the other hand, the N-type epitaxial layer 2 serving as a control portion is electrically isolated by a P-type diffusion layer, and a plurality of elements such as MOS transistors are formed in the isolation region PW. A predetermined control circuit for controlling the is formed. This control unit has a power M formed in the power unit.
The OSFET mainly has a built-in protection circuit for overcurrent and overvoltage protection that occurs when an abnormality occurs.
It suppresses the destruction of the OSFET.

The overcurrent protection circuit formed in the control unit is, for example, as shown in FIG. 5, a current detection resistor R for detecting an abnormal current flowing through a power MOSFET, constant current sources M1 and M2, and a constant current. A comparator 9 for comparing a reference voltage Vref formed by the sources M1 and M2 with a detection voltage detected by a detection resistor R, and a MOSFET controlled by an output signal output from the comparator 9 to turn on / off a power MOSFET. And the overcurrent is power MOSF
When it flows to ET, a predetermined output signal is output from the comparator, the MOSFET is turned on, and the predetermined signal supplied to the gate of the power MOSFET is cut off to turn off the power MOSFET.
Is turned off to prevent destruction of the power MOSFET due to overcurrent. A similar technique described above is disclosed in, for example, Japanese Patent Laid-Open No. 7-
It is described in Japanese Patent No. 231090.

[0005]

The overcurrent protection circuit is formed in the control section shown in FIG. Nch depletion MOSFET as a constant current source, and its depletion M
The drain and gate of the Nch depletion MOSFET are connected in series to the OSFET so as to be short-circuited, and a predetermined reference voltage Vref is formed and supplied to the comparator formed in the control unit.

A constant current source is an Nch depletion MOSFE.
When formed with T, there are the following problems. When an Nch depletion MOSFET is formed in the P well region of the control unit, an N-type impurity (As, As,
(P, etc.) is injected and diffused. However, after that, in the manufacturing process of the power MOSFET formed in the power portion, a high temperature heat treatment process for forming diffusion of the P or N type channel region (P or N type body region) and the P or N type high concentration region is performed. Therefore, if the P well region into which the N type impurity diffusion region serving as the channel region of the Nch depletion MOSFET that has been diffused previously is further diffused is shallow, the N type impurity diffusion region may penetrate through the P well region. The P well region was formed sufficiently deep.

The impurity diffusion concentration of the channel region of the Nch depletion MOSFET is designed in consideration of the temperature effect of these high temperature heat treatment steps so as to obtain predetermined characteristics.
There is a variation in the diffusion concentration of the channel region of the ET, and the variation is a major factor causing the variation in the IV characteristics of the Nch depletion MOSFET as shown in FIG. The above problem is the power MO
In order to reduce the ON resistance of the SFET and improve the avalanche resistance, when the channel region and the high-concentration region formed in the channel region are substantially flush with each other, the high temperature heat treatment time in the diffusion process is It takes a long time, N
The variation in the IV characteristics of the ch depletion MOSFET is likely to appear remarkably.

The Nch depletion MOSFETs M1 and M2 of the constant current source of the overcurrent protection circuit of FIG.
When there are characteristic variations as shown in FIG. 7, as shown in FIG. 7, Nch depletion MOSFETs M1 and M
The reference voltage Vref formed by 2 and 2 is the gate and drain of the Nch depletion MOSFET M2.
Since it is short-circuited to M1, the variation depends on the variation of the MOSFET M1.

For example, the overcurrent detection value is 2A, the reference voltage Vre
When f is designed to be 1.5V, due to the current variation of Nch depletion MOSFET M1, M1, M2
When the reference voltage Vref formed by Vref has a variation as shown in FIG. 7, the design overcurrent detection value is ± 10
When the reference voltage Vref within the range of% is a non-defective product, the semiconductor device having variations other than this range is treated as a defective product out of the design, which is a factor that greatly reduces the yield rate.

The above-mentioned Nch depletion MOSFET
Of the characteristics of the power MOSFET with control circuit function
When a single wafer is formed, it is distinguished into a non-defective area and a non-defective area per single wafer, and the constant current source Nc
The characteristic variation of the h-depletion MOSFET greatly affects the yield rate, and it is difficult to stably supply the same. The present invention has been made in view of the above-described circumstances, and due to the characteristic variation of the Nch depletion MOSFET used as the constant current source, even if the reference voltage Vref varies more than the allowable range, it is reproduced without being treated as a defective product. Then
The purpose is to significantly improve the yield rate.

[0011]

The present invention has the following features to attain the object mentioned above. That is, the semiconductor device of the present invention has a large number of power MOSs on the same semiconductor substrate.
A power section including an FET and a control section including a control circuit for controlling the power section are formed, and the control circuit includes:
At least a reference voltage generating circuit for generating a predetermined reference voltage, a detection means for detecting an overcurrent flowing through the power MOSFET, and the power MOSFE by comparing the reference voltage with a predetermined detection voltage generated by the detection means.
1. A semiconductor device having a comparator for supplying an output signal for controlling T, wherein the reference voltage generating circuit comprises a constant current source composed of a depletion type MOS for adjusting a plurality of reference voltages having different channel lengths. Depletion type MO
SFETs are arranged so as to be connected in parallel, and each of the adjustment depletion type MOSFETs has an M of the same size.
It is characterized in that OSFETs are arranged in series.

Here, the MOSFET is an enhancement type MOSFET. Also, the plurality of power MOSs formed in the power section.
The FET has a channel impurity region and a high-concentration impurity region formed in the channel impurity region and having a higher concentration than the channel impurity region and diffused to substantially the same plane as the bottom surface of the channel impurity region. Is characterized by.

As described above, a plurality of reference voltage adjusting depletion type MOSFETs having different channel lengths are connected in parallel to the depletion type MOSFET of the constant current source which constitutes the reference voltage generating circuit, and each depletion MOSFET is small. By arranging the MOSFETs of the same size individually, variations occur in the characteristics of the depletion MOSFET that is a constant current source in the high temperature heat treatment process, and even if the variations cause the reference voltage Vref to exceed the allowable range. , The channel length of the depletion MOSFET for adjustment, that is, the resistance value is adjusted by selectively turning on / off the MOSFETs connected to the plurality of depletion MOSFETs for reference voltage adjustment that are connected in parallel, so that the variation exceeds an allowable range. Within the allowable range of the reference voltage Vref It can be reproduced.

The adjustment depletion MOSFE described above is also provided.
The MOSFET connected to T is formed on the substrate in a small size and with the same size. Therefore, even if the characteristics of the MOSFET vary, the adjustment depletion MOSF
You can almost ignore the effect on ET,
The effective area can be reduced.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a power MOSFET with a control circuit function according to an embodiment of the present invention. The N − type epitaxial layer 12 is formed on one main surface of the N + type semiconductor substrate 11, and the MOS of the power section P is formed.
It constitutes a part of the drain region 13 of the FET. In the drain region 13 of the power portion P, P-type channel impurity regions 14 forming a channel are regularly formed. A high-concentration impurity region 15 having a higher concentration than that of the channel impurity region 14 is formed in the channel impurity region 14. The bottom portion of the high concentration impurity region 15 formed in the channel impurity region 14 is formed to be substantially flush with the bottom portion of the channel impurity region 14.

Further, a ring-shaped N + type source region 16 is formed in the channel impurity region 14, and a gate electrode 18 is formed on a region of the channel impurity region 14 which becomes a channel with an insulating layer 17 interposed therebetween. The source region 16 and the channel impurity region 14 are connected to a source electrode 19 which is a metal electrode made of a vapor deposited aluminum film, and a drain electrode 20 which is a metal electrode is formed on the back surface of the semiconductor substrate 11.

On the other hand, in the epitaxial layer 12 of the control section C adjacent to the power section P, the channel impurity region 1 is formed.
A well region 21 in which a P-type impurity having a concentration lower than the impurity concentration of 4 is diffused is formed. An overcurrent protection circuit for controlling the power section P is formed in the well region 21. The feature of the present invention resides in the overcurrent protection circuit formed in the control unit. As shown in FIG. 2, the overcurrent protection circuit includes at least the Nch depletion type MOS 31.
, Each of which has a different channel length and is connected in parallel to each other and has a plurality of reference voltage adjusting Nch depletion type MOSFETs 32, 33. ． ． And its depletion M
OSFETs 32, 33. ． ． Switch Nch enhancement MOSFETs 40, 4 connected to respective sources of
1. ． ． And a reference voltage generating circuit 30 for generating an adjustable predetermined reference voltage, a detection means 37 for detecting an overcurrent flowing through the power MOSFET, and a comparison between the reference voltage and the predetermined detection voltage generated by the detection means 37. And a comparator 38 which supplies an output signal for controlling the power MOSFET.

In the reference voltage generation circuit 30, the plurality of adjustment Nch depletion MOSFEs connected in parallel are used.
T32, 33. ． ． And MOSFETs 40, 41. ． ．
Are formed in the constant current source Nch depletion MOSFET 31 due to variations in the diffusion layer in the channel region of the constant current source Nch depletion MOSFET 31.
When the DS varies, the variation of the IDS also causes the variation of the reference voltage Vref formed by the reference voltage generating circuit 30, but the MOSFETs 40, 41. ． ． The Nch depletion MOSFETs 32, 33. ． ． The reference voltage Vref having the variation is corrected to a set value by arbitrarily adjusting the channel length of the.

The features of the present invention will be further described below with reference to a method of manufacturing a power MOSFET with a control circuit, although not particularly shown in the drawings. A substrate in which the N − type epitaxial layer 12 is grown on the N + type semiconductor substrate 11 is prepared, and boron (B), which is a P − type impurity, is injected and diffused into the epitaxial layer 12 in the region serving as the control unit, and the control unit is formed. A P well region 21 to be C is formed.

The diffusion concentration of the well region 21 is made lower than that of a channel impurity region 14 and a high concentration impurity region 15 which will be described later, a long-term thermal diffusion process is performed to stabilize the well region 21, and a thermal diffusion process to be performed thereafter is performed. Suppresses the progress of diffusion in the well region. If the well region 21 is not sufficiently diffused, the diffusion of the well region 21 will proceed in the subsequent diffusion process, and the film thickness of the epitaxial layer 12 must be increased. Since the thickness of the epitaxial layer also becomes large, which hinders the reduction of on-resistance, it is important that the epitaxial layer is sufficiently diffused for a long time. Further, the well region 21 is formed so that the depth thereof is substantially the same as the bottom surface portions of the channel impurity region 14 and the high-concentration impurity region 15 or slightly shallower.

Specifically, for example, boron having a dose energy of 1 × 10 −13 to 3.5 × 10 −13 is implanted with an implantation energy of 70 KeV, and then about 500 at about 1100 ° C. to 1200 ° C.
Well to 800 minutes to form a well region. The dose amount of the well region 21 is not limited to the above-mentioned specific example, and may be appropriately selected depending on the concentration of the epitaxial layer, that is, the breakdown voltage value to be set.
Vth of the N-channel EMOS formed in 1 is controlled.

After the well region 21 is formed, an N-type impurity such as arsenic (As) is injected / diffused into a region serving as a channel of the Nch depletion MOSFET in the well region 21, and the channel region 2 of the Nch depletion MOSFET is formed.
2 is formed. After forming the channel region 22 of the Nch depletion MOSFET, the gate electrodes 18 and 18A are selectively formed via the insulating layer. That is, the gate electrode 18 of the power MOSFET is formed in the power region P region, and the lateral MOS gate electrode 18A such as the N channel EMOS or N channel DMOS is formed in the control region C region. This Nc
The h depletion MOSFET is used as a constant current source of an overcurrent protection circuit and an element for adjusting a reference voltage. Each Nc
h enhancement MOSFETs 40, 41. ． ． Is
Since it is used only as a switch for selectively adjusting the channel length of the reference voltage adjusting depletion MOSFET, its size is formed as small as possible and the gate electrode is formed to have the same size.

In the power region P region, boron (B), which is a P-type impurity, is implanted into the surface of the epitaxial layer 12 with a predetermined dose amount using the gate electrode 18 as a mask, and the first thermal diffusion is performed under a predetermined temperature condition. An extremely shallow channel impurity region 14 to be a channel region is formed by performing the processing. Specifically, for example, boron having a dose amount of 3 × 10 −13 to 5 × 10 −13 is implanted with an implantation energy of 70 KeV to obtain about 11
A first heat treatment step is performed at 00 ° C. to 1200 ° C. for about 100 to 200 minutes. In the same step of forming the channel impurity region 14, a P + type impurity may be diffused into the well region 21 as needed.

P-type boron (B) having a higher concentration than the concentration of the channel impurity region 14 which becomes the high concentration impurity region 15 is implanted into the surface of the channel impurity region 14. Specifically, for example, when the dose amount of boron (B) in the channel impurity region 14 is 3 × 10 −13 to 5 × 10 −13, the implantation energy is 80 KeV and the dose amount is 8 × 10 −14 to 1.
Inject boron of 10-15.

After the high-concentration impurity to be the high-concentration impurity region 15 is implanted, a second thermal diffusion process for diffusing the high-concentration impurity is performed. The second diffusion step is performed so that the bottom surface portion of the high concentration impurity region 15 and the bottom surface portion of the channel impurity region 14 diffused in the first diffusion step described above are substantially flush with each other. In general, in impurity diffusion, the impurity diffusion depth is determined by the impurity concentration, diffusion temperature, and diffusion time. Since the impurity concentration of the channel impurity region and the impurity concentration of the high concentration impurity region have the difference in concentration as described above, the diffusion of the high concentration impurity region is faster than the diffusion of the channel impurity region.

Therefore, if the concentration of the impurities injected into the high concentration impurity region 15 and the concentration of the impurities injected into the channel impurity region 14 are set in advance, the temperature and time of the second thermal diffusion step can be set. The high-concentration impurity region 15 and the channel impurity region 14 are diffused at the same time, and the bottom of the high-concentration impurity region 15 and the bottom of the channel impurity region 14 in the direction of diffusion can be formed on substantially the same plane.

In this power MOSFET with control function,
As described above, the dose amount of boron (B), which is the impurity that becomes the channel impurity region 14, is 3 × 10 −13 to 5 × 1.
0-13 at about 1100 ° C to 1200 ° C for 100 minutes to 20
After performing the 0-minute first preliminary heat treatment step, the dose amount of boron (B), which is an impurity to be the high-concentration impurity region 15, is set to 8 × 10 −14 to 1 × 10 −15, and about 1100 ° C. to 120 ° C.
By performing the second heat treatment step at 0 ° C. for about 30 minutes to 90 minutes, the bottom surface portion of the high concentration impurity region 15 and the bottom surface portion of the channel impurity region 14 are formed on substantially the same surface as described above. There is.

The source region 1 is formed in the channel impurity region 14 and the well region 21 of the power P region and the control C region.
Source regions are formed by implanting and diffusing N + -type impurities to be 6, 16A and drain regions 16B. As the N-type impurity used as the source region, phosphorus (P), arsenic (As), or the like can be used.
Arsenic (As) with a dose of 5 × 10 −15 to 1 × 10 −16 is injected at ˜150 KeV and about 3 ° C. at about 900 ° C. to 1100 ° C.
The source regions 16 and 16 are subjected to a heat diffusion process for 0 to 60 minutes.
Forming A.

After forming the source regions 16 and 16A, an insulating layer such as SiO 2 is deposited on the surface of the gate electrodes 18 and 18A by atmospheric pressure or low pressure CVD method and photoetched to cover the surfaces of the gate electrodes 18 and 18A with the insulating layer 17. To do. And
An aluminum film is formed on the exposed surface by sputtering or vapor deposition to form a source electrode 19 commonly connected to the source region 16 formed in the power portion P region, and the MOS drain and source electrodes 22 and 23 formed in the control region C region. Form. Further, the power MOSFE is provided on the back surface of the semiconductor substrate 11.
A metal layer to be the drain electrode 20 of T is formed, and the power MOSFET with a control circuit function shown in FIG. 1 is completed.

The feature of the present invention resides in that, as described above, the output of the Nch depletion MOSFET 31 serving as the constant current source forming the overcurrent protection circuit formed in the control unit has a plurality of first channels having different channel lengths. , Second ,,, adjustment depletion MOSFETs 32, 3
3. ． ． Are connected in parallel and their depletion MOSFE
T32, 33. ． ． Source 32S, 33S. ． ． , MOSFETs 40, 41. ． ． Is to form the reference voltage generation circuit 30 connected to the control unit in the control unit.

Depletion MOSFE for each adjustment
T32, 33. ． ． Drains 32D, 33D. ． ． And the gates 32G, 33G. ． ． As shown in FIG.
The source 31S of the Nch depletion MOSFET 31 serving as a constant current source is commonly connected by the aluminum wiring A and the like. On the other hand, each adjustment Nch depletion MOSFET 3
2, 33. ． ． Source 32S, 33S. ． ． Are Nch enhancement MOSFETs 40, 41. ． ． Are commonly connected by different aluminum wirings B. That is, each Nch
Enhancement MOSFETs 40, 41. ． ． Drains 40D, 41D. ． ． Is an adjustment depletion MO
SFET 32, 33. ． ． Source 32S, 33
S. ． ． Formed in common with enhancement MOSF
ET40, 41. ． ． Source 40S, 41S. ． ． Are commonly connected by aluminum wiring B, so that Nch enhancement MOSFET is connected between two different aluminum wirings A and B.
40, 41. ． ． Via the plurality of adjustment Nch depletion MOSFETs 32, 33 ,. ． ． Will be connected in parallel.

Nch depletion MOSFET for each adjustment
32, 33 ,. ． ． The channel length of
The adjustment Nch depletion MOSFETs 32, 33 ,. ． ． By varying the resistance values of the Nch depletion MOSFETs 31, the current characteristics of the constant current source Nch depletion MOSFET 31 vary, and even if the reference voltage Vref greatly varies, the adjustment Nch depletion circuits connected in parallel. , MOSFETs 32, 33 ,. ． ． By adjusting the channel length of the whole, the variation of the reference voltage Vref is corrected within the allowable range.

For example, when the adjustment depletion MOSFET 32 shown in FIG. 3 is designed with a channel length L of 50 μm, a channel width W of 7 μm and Rs of 5 KΩ, the resistance value of the adjustment depletion MOSFET 32 is 35 KΩ.
Becomes This adjustment Nch depletion MOSFET3
Assuming No. 2, the first adjustment Nch depletion MOSFE
Let T. When the overcurrent detection value is 2 A and the design reference voltage to be compared with the overcurrent detection value is 1.5 V, the design value of the constant current IDS of the constant current source Nch depletion MOSFET is 42.8 μA.

Here, the channel length of the first adjustment Nch depletion MOSFET 32 is 50 μm under the above conditions.
And the remaining second, third, fourth, formed adjacently arranged
And fifth adjustment Nch depletion MOSFET 3
3,34. ． ． Channel length of 100μm, 2 respectively
00 μm, 400 μm, 800 μm, etc., the length is doubled, so that the second, third, fourth and fifth adjustment Nch depletion MOSFETs 33, 34. ． ． The resistance value of
70KΩ, 140KΩ, 280KΩ, 560K respectively
It becomes Ω. That is, the constant current source Nch depletion MOSF
The first to fifth adjustment Nch depletion MOSFETs 32, 33 ,. ． ． Will be connected.

Constant current source Nch depletion MOSFET
When the designed IDS value of 31 is 42.8 μA as described above, the impurity diffusion layer in the channel region of the constant current source Nch depletion MOSFET 31 is formed as described in “Problems to be Solved by the Invention” and the manufacturing method described above. , Before forming the channel region of the power MOSFET and the high concentration region, that is, the Nch depletion MOSF.
Before the formation of the gate electrode of ET, the constant current source Nch depletion MOSFET 3 is formed by the high temperature heat treatment process by the first and second diffusion processes for forming the channel diffusion region and the high concentration region of the power MOSFET.
The IDS also varies due to the variation of the diffusion layer in the first channel region (see FIG. 6).

Constant current source Nch depletion MOSFET
When the IDS of 31 is varied, the set reference voltage Vref is also varied depending on the variation, and when the reference voltage Vref is varied beyond the allowable range, it is treated as a defective product. However, in the present invention, it is assumed that the constant current source N
Due to the variation of the channel diffusion layer of the ch depletion MOSFET 31, the IDS varies more than the designed value, and even if the variation causes the reference voltage Vref to exceed the allowable range, the reference voltage Vref can be corrected to almost the set value. .

Nch depletion MOSFET for each adjustment
Source 32S, 33S. ． ． Aluminum wiring B commonly connected to each source 32S, 33S. ． ． Between the outputs of the enhancement MOSFETs 40, 41. ． ． The switch means consisting of is connected and formed, and each enhancement MOSF
ET40, 41. ． ． Has a circuit configuration such that it is in an ON state before adjustment of the reference voltage.
OSFETs 32, 33 ,. ． ． The conductive state is maintained by the aluminum wiring B. That is, power MO with control function
Until the completion of the SFET, each adjustment Nch depletion MOSFET 32, 33 ,. ． ． Are connected in parallel,
The combined resistance value is set to the minimum value. Here, the completion means a state in which various characteristics are checked and the wafer is individually separated.

For example, the constant current source Nch MOSFET 31
When the design IDS of the above is set to 42.8 μA and the constant current source Nch depletion MOSFET 31 is formed on the semiconductor substrate, there is no variation in channel diffusion, and the set value of 42.
When 8 μA is actually measured, the sources 33S and 34 of the second to fifth adjustment Nch depletion MOSFETs are used.
S. ． Enhancement MOSFET 4 connected to
1,42. ． ． Power is supplied to the dedicated pad so that the gates 41G, 42G. ． ． OFF
Input the signal. By turning on only the enhancement MOSFET 40, the first adjustment Nch depletion M
Only the OSFET 32 becomes conductive, and the set reference voltage value of 1.5 V can be obtained.

Next, a constant current source Nch depletion MOS
A variation occurs in the channel diffusion layer of the FET 31, and the measured I
If DS is 64.4 μA, the sources 34S, 34S of the third to fifth adjustment Nch depletion MOSFETs are
35S. ． ． Enhancement MOSFE connected to
T42, 43. ． ． Power is supplied to the dedicated pad so that the gates 42G, 4G. ． ． OF
Input F signal. Enhancement MOSFET4
First and second adjustment Nch depletion MOSFETs 32 and 3 connected in parallel by turning on only 0 and 41
Only 3 becomes conductive and the set reference voltage value is 1.5V
Can be obtained.

That is, a plurality of adjustment Nch depletion MOSFETs 32, 33 ,. ． ． Are connected in parallel to the output of the constant current source Nch depletion MOSFET 31, so that even if the IDS varies due to the variation of the channel diffusion layer of the constant current source Nch depletion MOSFET 31 and the reference voltage Vref varies from the set value, the parallel connection is performed. The adjustment Nch depletion MOSFETs 32, 33 ,. ． ． Can be adjusted to the set reference voltage by arbitrarily selecting according to the variation.

Also, the adjustment depletion MOSFET 3
2, 33. ． ． Of each enhancement MOSFET 40, 41. ． ． Are small and identical, so that the effective area can be increased. In the present embodiment, the first to fifth adjustment Nch depletion MOSFETs 32, 33 ,. ． ． It is possible to adjust in 31 steps because of using.

As described above, according to the present invention, the adjustment Nch depletion MOSFETs 32, 33. ． ． Are placed. Before the reference voltage adjustment, each adjustment Nch depletion MOSFET 32, 33. ． ． Are all connected in parallel. Depending on the size of the variation, each adjustment N
ch depletion MOSFET 32, 33. ． ． The channel length can be variably adjusted by selecting it as necessary, and the reference voltage formed by the reference voltage generating circuit can be approximated to the design value. That is, in the present invention, since the reference voltage formed by the reference voltage generation circuit can be the design reference voltage value, the overcurrent detection value detected by the overcurrent protection circuit is small, for example, 1 to 2.5 A. Can be set to.

Originally, a power MOSFET with a control circuit function
5 to 10 A or more is sufficiently guaranteed, but when the above-mentioned overcurrent flows to other peripheral circuit elements electrically connected to the power MOSFET with a control circuit,
Peripheral circuit elements may be destroyed without destroying the power MOSFET. However, power MOS with control circuit function
By setting the overcurrent detection value of the FET to 1 to 2.5 A, it is possible to prevent the destruction of the peripheral circuit element due to the overcurrent.

Therefore, in order to reliably detect with a small overcurrent detection value, the variation of the reference voltage has a great influence, but in the present invention, as described above, even when the variation of the reference voltage occurs, the design It is possible to correct to the reference voltage value, and it is possible to prevent destruction of peripheral circuit elements due to overcurrent.

[0045]

As described above, according to the semiconductor device of the present invention, a plurality of reference voltage adjusting depletion type MOSFETs having different channel lengths are connected in parallel to the depletion type MOSFET of the constant current source forming the reference voltage generating circuit. By connecting and arranging small MOSFETs of the same size individually in each depletion MOSFET, a depletion MO that is a constant current source in the high temperature heat treatment step is provided.
Even when the SFET characteristics vary and the variation causes the reference voltage Vref to exceed the allowable range, the MOSFETs connected to the plurality of reference voltage adjustment depletion MOSFETs connected in parallel are selectively used. ON / OFF to adjust depletion MOSFE
By adjusting the channel length of T, that is, the resistance value, it is possible to reproduce the reference voltage Vref that has varied more than the allowable range within the allowable range, and it is possible to significantly suppress the defective rate.

Further, according to the present invention, the MOSFET connected to the adjustment depletion MOSFET is formed on the substrate in a small size and in the same size.
Even if the characteristics of the FETs vary, the influence on the adjustment depletion MOSFET can be almost ignored, and the effective area can be increased and the density can be increased.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is an overcurrent protection circuit of the present invention.

FIG. 3 is a pattern diagram of a reference voltage generation circuit of the present invention.

FIG. 4 is a sectional view of a conventional semiconductor device.

FIG. 5 is a conventional overcurrent protection circuit.

FIG. 6 Conventional constant current source Nch depletion MOSFE
The characteristic view of T.

FIG. 7 is a characteristic diagram showing variations in reference voltage.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-152354 (JP, A) JP-A-7-169846 (JP, A) JP-A-59-121730 (JP, A) JP-A-8- 6653 (JP, A) JP 64-48464 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 656

Claims (3)

(57) [Claims] 1. A large number of power MOSFs on the same semiconductor substrate.
A power unit formed of ET and a control unit including a control circuit for controlling the power unit are formed, and the control circuit includes a reference voltage generation circuit for generating at least a predetermined reference voltage, and an overcurrent flowing through the power MOSFET. Comparing the reference voltage with a predetermined detection voltage generated by the detecting means to detect the power MOSFET
In the semiconductor device, a reference voltage generating circuit is provided with a plurality of reference voltage adjusting depletion circuits each having a different channel length from a constant current source composed of a depletion type MOS. Type MOS
A semiconductor device in which FETs are arranged in parallel, and small MOSFETs of the same size are arranged in series in each of the adjustment depletion type MOSFETs. 2. The semiconductor device according to claim 1, wherein the MOSFET is an enhancement type MOSFET. 3. The plurality of power MOSFETs formed in the power section are formed in a channel impurity region and in the channel impurity region, and have a higher concentration than the channel impurity region and substantially the bottom surface of the channel impurity region. The semiconductor device according to claim 1, wherein a high-concentration impurity region diffused to the same surface is formed.