JP3495245B2 - Electronic component storage package - Google Patents

Electronic component storage package

Info

Publication number
JP3495245B2
JP3495245B2 JP03281998A JP3281998A JP3495245B2 JP 3495245 B2 JP3495245 B2 JP 3495245B2 JP 03281998 A JP03281998 A JP 03281998A JP 3281998 A JP3281998 A JP 3281998A JP 3495245 B2 JP3495245 B2 JP 3495245B2
Authority
JP
Japan
Prior art keywords
lid
line
electronic component
ground line
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03281998A
Other languages
Japanese (ja)
Other versions
JPH11233659A (en
Inventor
義博 鍋
邦英 四方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP03281998A priority Critical patent/JP3495245B2/en
Publication of JPH11233659A publication Critical patent/JPH11233659A/en
Application granted granted Critical
Publication of JP3495245B2 publication Critical patent/JP3495245B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1616—Cavity shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1617—Cavity coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は電子部品を収納する
ための電子部品収納用パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component storage package for storing electronic components.

【０００２】[0002]

【従来の技術】従来の電子部品収納用パッケージは、内
部にタングステンやモリブデン等で形成された電源線、
グランド線、信号線を有し、且つ上面に電子部品を搭載
するための搭載部を有するアルミナセラミックス等の電
気絶縁材料より成る基体と、同じくアルミナセラミック
ス等の電気絶縁材料より成り、前記基体の搭載部に搭載
される半導体素子等の電子部品を収容する空所を形成す
るための凹部を有する蓋体とから構成されており、基体
の搭載部に半導体素子等の電子部品を搭載固定するとと
もに該電子部品の各端子を基体に設けた電源線、グラン
ド線、信号線にボンディングワイヤを介し電気的に接続
し、しかる後、基体上に蓋体を内部に電子部品を収容す
るようにしてガラス等の封止材により接合させ、これに
よって最終製品としての電子装置が完成する。2. Description of the Related Art A conventional electronic component storage package has a power supply line formed of tungsten, molybdenum, or the like,
A base made of an electrically insulating material such as alumina ceramics having a ground line and a signal line and having a mounting portion for mounting an electronic component on the upper surface, and an electrically insulating material also made of alumina ceramics, etc. And a lid having a recess for forming a cavity for accommodating an electronic component such as a semiconductor element to be mounted on the base, and mounting and fixing the electronic component such as the semiconductor element on the mounting portion of the base. Each terminal of the electronic component is electrically connected to the power supply line, the ground line, and the signal line provided on the base body through the bonding wires, and then the lid body is housed on the base body so that the electronic component is housed therein, such as glass. They are joined by the encapsulant, which completes the electronic device as the final product.

【０００３】しかしながら、従来、基体や蓋体に使用さ
れているアルミナセラミックスはノイズに対するシール
ド効果が低いこと、タングステンやモリブデン等からな
る信号線は高調波のノイズを伝搬させ易いこと、及び近
時、半導体素子等の電子部品は高速駆動が行われるよう
になってきており、ノイズの影響を極めて受け易いもの
となってきていること等から外部近接位置にノイズ発生
源があると内部に収容する半導体素子等の電子部品や基
体に設けた信号線にノイズが極めて容易に入り込み、そ
の結果、前記入り込んだノイズによって半導体素子等の
電子部品に誤動作を発生させてしまうという欠点を有し
ていた。However, the alumina ceramics conventionally used for the base and lid have a low noise shielding effect, and the signal line made of tungsten, molybdenum or the like easily propagates harmonic noise, and recently, Since electronic parts such as semiconductor elements are being driven at high speed and are becoming very susceptible to noise, semiconductors that are housed inside when there is a noise source at an external proximity position, etc. There is a drawback in that noise easily enters the electronic parts such as elements and the signal lines provided on the base body, and as a result, the entered noise causes malfunction of the electronic parts such as semiconductor elements.

【０００４】また高速駆動を行う電子部品はそれ自体が
ノイズを発生し易く、電子部品が発生したノイズは他の
装置に入り込んで誤動作等の悪影響を与えるという問題
も有していた。Further, the electronic parts which are driven at a high speed are apt to generate noises themselves, and the noises generated by the electronic parts have a problem that they enter other devices and have a bad effect such as malfunction.

【０００５】そこで上記欠点を解消するために、本願出
願人は先に、基体に形成されている信号線をグランド線
で挟み、かつ蓋体の凹部内壁に金属層を被着させるとと
もに該金属層を基体のグランド線に電気的に接続させた
電子部品収納用パッケージを提案した（特願平４ー２０
３６４６号参照）。In order to solve the above-mentioned drawbacks, therefore, the applicant of the present application first sandwiched the signal line formed on the base with ground lines, and adhered the metal layer to the inner wall of the recess of the lid, and at the same time, applied the metal layer. We proposed a package for storing electronic parts in which the board is electrically connected to the ground wire of the base (Japanese Patent Application No. 4-20).
3646).

【０００６】かかる電子部品収納用パッケージによれ
ば、基体の信号線をグランド線で挟み、かつ蓋体の凹部
内壁に金属層を被着させるとともに該金属層を前記基体
のグランド線に電気的に接続させたことから基体に形成
した信号線及びパッケージの内部に収容する電子部品の
両方はグランド線で完全にシールドされることとなって
基体に形成した信号線及びパッケージの内部に収容する
電子部品に外部ノイズが入り込むことはなく、その結
果、内部に収容する電子部品を正常、且つ安定に作動さ
せることが可能となる。According to such an electronic component storing package, the signal line of the base body is sandwiched between the ground lines, and a metal layer is adhered to the inner wall of the recess of the lid, and the metal layer is electrically connected to the ground line of the base body. Since the connection is made, both the signal line formed on the base and the electronic component housed inside the package are completely shielded by the ground line, and the electronic line accommodated inside the signal line formed on the base and inside the package. External noise does not enter, and as a result, it becomes possible to operate the electronic components housed inside normally and stably.

【０００７】また同時に内部に収容する電子部品等が発
生するノイズはパッケージの外部に漏れることは無く、
その結果、近接して配置される他の装置に誤動作等の悪
影響を与えることもない。At the same time, noise generated by electronic components housed inside does not leak to the outside of the package,
As a result, other devices arranged close to each other are not adversely affected such as malfunction.

【０００８】[0008]

【発明が解決しようとする課題】しかしながら、この電
子部品収納用パッケージにおいては、パッケージ内部に
収容する電子部品への外部ノイズの影響及びパッケージ
内部に収容する電子部品が発したノイズの外部装置への
影響は有効に防止し得るもののパッケージ内部に収容す
る電子部品が発したノイズはその一部が蓋体の凹部内壁
に被着させた金属層で反射して元の電子部品に入り込む
こと、及び搭載する電子部品の作動に伴う電源電圧の変
動によって電源線とグランド線間に発生するノイズの信
号線への入り込みは防止できず、これらノイズは依然と
して信号線を介して半導体素子等の電子部品に入り込
み、電子部品を誤動作させてしまうという解決すべき課
題を有していた。However, in this electronic component housing package, the influence of external noise on the electronic components housed inside the package and the noise generated by the electronic components housed inside the package to the external device. Although the effect can be effectively prevented, a part of the noise generated by the electronic component housed inside the package is reflected by the metal layer adhered to the inner wall of the concave portion of the lid and enters the original electronic component, and mounting It is not possible to prevent noise generated between the power supply line and the ground line from entering the signal line due to fluctuations in the power supply voltage due to the operation of electronic parts, and these noises still enter the electronic parts such as semiconductor elements via the signal line. However, there is a problem to be solved that the electronic parts malfunction.

【０００９】本発明は上記欠点に鑑み案出されたもの
で、その目的は内部に収容する電子部品にノイズが入り
込むのを有効に防止し、電子部品を長期間にわたり正
常、かつ安定に作動させることができる電子部品収納用
パッケージを提供することにある。The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to effectively prevent noise from entering an electronic component housed therein, and to operate the electronic component normally and stably for a long period of time. Another object is to provide a package for storing electronic components that can be used.

【００１０】[0010]

【課題を解決するための手段】本発明は、表面に電子部
品が搭載される搭載部を有し、表面及び内部に前記電子
部品の信号電極、グランド電極、電源電極が電気的に接
続される信号線、グランド線、電源線を有する基体と、
前記搭載部に搭載される電子部品を内部に収容するため
の凹部を有する蓋体とから成り、基体と蓋体とを封止材
を介し取着することによって内部に電子部品を気密に収
容するようになした電子部品収納用パッケージであっ
て、前記基体はガラスセラミックス焼結体から成り、前
記グランド線は少なくとも一つの補助グランド線が分岐
しており、該グランド線と補助グランド線とで前記信号
線を挟み込むとともにグランド線、補助グランド線の少
なくとも一部に磁性粉末を含有させ、前記グランド線及
び補助グランド線が前記基体と同時焼成によって形成さ
れ、かつ蓋体の凹部内壁に三角柱形状の突起が複数個配
列された金属層を被着させるとともに該金属層を前記基
体のグランド線もしくは補助グランド線に電気的に接続
させたことを特徴とするものである。The present invention has a mounting portion on the surface of which electronic components are mounted, and a signal electrode, a ground electrode, and a power electrode of the electronic components are electrically connected to the surface and inside. A base having a signal line, a ground line, and a power line,
A lid body having a recess for accommodating an electronic component mounted on the mounting portion therein, and an electronic component is hermetically accommodated inside by attaching the base body and the lid body via a sealing material. In the package for storing electronic parts, the base body is made of a glass-ceramic sintered body, and at least one auxiliary ground line is branched from the ground line. A magnetic powder is contained in at least a part of the ground line and the auxiliary ground line while sandwiching the signal line, the ground line and the auxiliary ground line are formed by co-firing with the base body, and a triangular prism-shaped projection is formed on the inner wall of the recess of the lid. A plurality of metal layers having a plurality of layers are deposited and the metal layers are electrically connected to a ground line or an auxiliary ground line of the base. Is shall.

【００１１】また本発明は、前記金属層の三角柱形状の
突起は底辺の長さが０．２乃至１．０ｍｍ、幅が０．２
乃至１．０ｍｍ、高さが０．３乃至１．０ｍｍであるこ
とを特徴とするものである。According to the present invention, the triangular prism-shaped projection of the metal layer has a base length of 0.2 to 1.0 mm and a width of 0.2.
To 1.0 mm, and the height is 0.3 to 1.0 mm.

【００１２】本発明の電子部品収納用パッケージによれ
ば、電子部品の信号電極に接続される信号線をグランド
線と該グランド線より分岐した補助グランド線とで挟み
込むとともにグランド線及び補助グランド線の少なくと
も一部に磁性粉末を含有させたことから信号線に外部か
らノイズが直接作用して入り込むことはなく、また搭載
する電子部品の作動に伴う電源電圧の変動によって電源
線とグランド線間に発生するノイズも電子部品に入り込
む前にグランド層または補助グランド層に含有されてい
る磁性粉末で熱エネルギーに変換されて吸収され、その
結果、電子部品にこれらノイズが入り込むことはなく、
電子部品を常に正常に作動させることができる。According to the electronic component storage package of the present invention, the signal line connected to the signal electrode of the electronic component is sandwiched between the ground line and the auxiliary ground line branched from the ground line, and the ground line and the auxiliary ground line are formed. Since at least part of the magnetic powder is included, noise does not directly enter the signal line from the outside, and it also occurs between the power line and the ground line due to fluctuations in the power voltage accompanying the operation of the mounted electronic components. Before entering the electronic components, the noise is also converted into heat energy by the magnetic powder contained in the ground layer or auxiliary ground layer and absorbed, and as a result, these noises do not enter the electronic components.
The electronic parts can always operate normally.

【００１３】また本発明の電子部品収納用パッケージに
よれば、蓋体の凹部内壁に金属層を被着させるとともに
該金属層を基体に形成したグランド線または補助グラン
ド線に電気的に接続させたことからパッケージ内部に収
容する電子部品はグランド線、補助グランド線及び金属
層で完全にシールドされることとなり、その結果、パッ
ケージの内部に収容する電子部品に外部ノイズが入り込
むことはなく、内部に収容する電子部品を正常、かつ安
定に作動させることが可能となる。Further, according to the electronic component storing package of the present invention, a metal layer is deposited on the inner wall of the recess of the lid, and the metal layer is electrically connected to the ground line or the auxiliary ground line formed on the substrate. Therefore, the electronic components housed inside the package are completely shielded by the ground line, auxiliary ground line, and metal layer.As a result, external noise does not enter the electronic components housed inside the package, and It is possible to operate the electronic components housed therein normally and stably.

【００１４】更に本発明の電子部品収納用パッケージに
よれば、蓋体の凹部内壁に被着させた金属層に、例え
ば、底辺の長さが０．２乃至１．０ｍｍ、幅が０．２乃
至１．０ｍｍ、高さが０．３乃至１．０ｍｍである三角
柱形状をなす突起を複数個配列させたことからパッケー
ジ内部に収容する電子部品が作動時にノイズを発したと
してもそのノイズは突起で放射角度が制御されて元の電
子部品に入り込むことはなく、その結果、電子部品を正
常、かつ安定に作動させることが可能となる。Further, according to the electronic component storing package of the present invention, for example, the bottom side has a length of 0.2 to 1.0 mm and the width of 0.2 on the metal layer adhered to the inner wall of the recess of the lid. Since a plurality of triangular prism-shaped protrusions having a height of 1.0 mm to 1.0 mm and a height of 0.3 mm to 1.0 mm are arranged, even if the electronic components housed inside the package generate noise during operation, the noise is a protrusion. The radiation angle is not controlled by and does not enter the original electronic component, and as a result, it becomes possible to operate the electronic component normally and stably.

【００１５】[0015]

【発明の実施の形態】次に本発明を添付の図面に基づき
詳細に説明する。図１乃至図３は本発明の電子部品収納
用パッケージとして半導体素子を収容する半導体素子収
納用パッケージを例に示す図であり、半導体素子収納用
パッケージ１は、主に、基体２と蓋体３とから構成され
ている。DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings. 1 to 3 are views showing an example of a semiconductor element housing package for housing a semiconductor element as an electronic component housing package of the present invention. The semiconductor element housing package 1 mainly includes a base 2 and a lid 3. It consists of and.

【００１６】 前記基体２は、概ね四角形の板状の部材
であり、ＳｉＯ２−Ａｌ２Ｏ３−ＭｇＯ−ＺｎＯ−Ｂ２
Ｏ３系結晶性ガラス等のガラスセラミックス焼結体で構
成されている。The base body 2 is a substantially rectangular plate-shaped member, and is made of SiO 2 —Al 2 O 3 —MgO—ZnO—B 2.
It is composed of a glass ceramics sintered body such as O 3 type crystalline glass.

【００１７】また前記基体２の上面中央部には半導体素
子４を搭載する搭載部Ａが形成されており、該搭載部Ａ
には半導体素子４が接着剤を介して取着固定される。A mounting portion A for mounting the semiconductor element 4 is formed in the center of the upper surface of the base body 2.
The semiconductor element 4 is attached and fixed to the semiconductor device via an adhesive.

【００１８】 前記基体２は、ＳｉＯ２−Ａｌ２Ｏ３−
ＭｇＯ−ＺｎＯ−Ｂ２Ｏ３系結晶性ガラス等のガラスセ
ラミックス焼結体から成り、酸化珪素（ＳｉＯ２）、酸
化アルミニウム（Ａｌ２Ｏ３）、酸化マグネシウム（Ｍ
ｇＯ）、酸化亜鉛（ＺｎＯ）、酸化ビスマス（Ｂ
２Ｏ３）に適当な有機溶剤、溶媒、可塑剤等を添加混合
して泥漿状となすとともに、該泥漿物をドクターブレー
ド法やカレンダーロール法等によりシート状に成形して
複数枚のグリーンシート（生シート）を得、しかる後、
前記グリーンシートに適当な打ち抜き加工を施すととも
に所定の順に上下に積層し、８００〜１０５０℃の温度
で焼成することによって製作される。The substrate 2 is made of SiO 2 —Al 2 O 3 —.
Consists MgO-ZnO-B 2 O 3 based crystalline glass ceramic sintered body such as glass, silicon oxide (SiO 2), aluminum oxide (Al 2 O 3), magnesium oxide (M
gO), zinc oxide (ZnO), bismuth oxide (B
2 O 3 ) is mixed with an appropriate organic solvent, solvent, plasticizer and the like to form a slurry, and the slurry is formed into a sheet by a doctor blade method, a calendar roll method, or the like to form a plurality of green sheets. After getting (raw sheet),
It is manufactured by subjecting the green sheet to an appropriate punching process, stacking the green sheet vertically in a predetermined order, and firing at a temperature of 800 to 1050 ° C.

【００１９】前記基体２はまたその内部及び上下面に信
号線５ａ、グランド線５ｂ、電源線５ｃが被着形成され
ており、該信号線５ａ、グランド線５ｂ及び電源線５ｃ
の基体２上面部に導出する部位には半導体素子４の各電
極がボンディングワイヤ６を介して電気的に接続され、
また基体２の下面部に導出する部位には外部リードピン
７がロウ材を介し取着されている。A signal line 5a, a ground line 5b, and a power supply line 5c are adhered and formed on the inside and upper and lower surfaces of the base body 2. The signal line 5a, the ground line 5b, and the power supply line 5c.
The electrodes of the semiconductor element 4 are electrically connected to the upper surface of the base body 2 via the bonding wires 6.
Further, external lead pins 7 are attached to the portion leading to the lower surface of the base body 2 through a brazing material.

【００２０】前記信号線５ａ、グランド線５ｂ及び電源
線５ｃは半導体素子４の各電極（信号電極、グランド電
極、電源電極等）を外部電気回路と接続される外部リー
ドピン７に電気的に接続させる作用を為し、該信号線５
ａ、グランド線５ｂ及び電源線５ｃは、銅、銀、金等の
金属粉末によって形成されている。The signal line 5a, the ground line 5b, and the power supply line 5c electrically connect each electrode (signal electrode, ground electrode, power supply electrode, etc.) of the semiconductor element 4 to an external lead pin 7 connected to an external electric circuit. It acts and the signal line 5
The a, the ground wire 5b, and the power supply wire 5c are made of metal powder such as copper, silver, and gold.

【００２１】前記信号線５ａ、グランド線５ｂ及び電源
線５ｃは、具体的には銅等の金属粉末に適当な有機溶
剤、溶媒を添加混合して得た金属ペーストを基体２とな
るグリーンシートの表面に予め従来周知のスクリーン印
刷法等の厚膜手法を採用し印刷塗布しておくことによっ
て基体２の内部及び上下面に被着形成される。The signal line 5a, the ground line 5b, and the power supply line 5c are made of a green sheet, which is a base 2 made of a metal paste obtained by adding a suitable organic solvent to a metal powder of copper or the like and mixing them. By applying a thick film method such as a conventionally known screen printing method to the surface in advance by printing and coating, it is formed on the inside and upper and lower surfaces of the substrate 2.

【００２２】なお、前記信号線５ａ、グランド線５ｂ及
び電源線５ｃを銅、銀、金等の金属粉末で形成した場
合、該銅、銀、金等はその電気抵抗率が３μΩ・ｃｍ以
下と低いことから信号線５ａを電気信号が伝搬しても電
気信号に大きな減衰を生じることはなく、これによって
半導体素子４に対し電気信号を確実に出し入れすること
ができる。When the signal line 5a, the ground line 5b and the power supply line 5c are made of metal powder such as copper, silver and gold, the electric resistivity of the copper, silver and gold is 3 μΩ · cm or less. Since it is low, even if the electric signal propagates through the signal line 5a, the electric signal is not greatly attenuated, and thus the electric signal can be surely taken in and out of the semiconductor element 4.

【００２３】 また前記銅、銀、金等の金属粉末はその
融点が９６０〜１０８０℃であるものの基体２を構成す
るＳｉＯ２−Ａｌ２Ｏ３−ＭｇＯ−ＺｎＯ−Ｂ２Ｏ３系
結晶性ガラス等のガラスセラミックス焼結体の焼成温度
が低いことから基体２を焼成して形成する際に同時に信
号線５ａ、グランド線５ｂ及び電源線５ｃを形成するこ
とが可能となる。The metal powder of copper, silver, gold or the like has a melting point of 960 to 1080 ° C., but the SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3 based crystalline glass that constitutes the substrate 2. Since the firing temperature of the glass ceramics sintered body is low, the signal line 5a, the ground line 5b, and the power supply line 5c can be simultaneously formed when the substrate 2 is fired and formed.

【００２４】更に前記グランド線５ｂはその一部から少
なくとも一つの補助グランド線５ｄが分岐されていると
ともに該グランド線５ｂと補助グランド線５ｄとの間に
信号線５ａを挟み込ませており、これによって信号線５
ａはその周囲がグランド線５ｂと補助グランド線５ｄに
よって完全にシールドされた状態となっている。そのた
め信号線５ａに外部からノイズが入り込もうとしても該
ノイズはグランド線５ｂ及び補助グランド線５ｄで遮断
され、信号線５ａにノイズが入り込んで半導体素子４を
誤動作させることはない。Further, at least one auxiliary ground line 5d is branched from a part of the ground line 5b, and the signal line 5a is sandwiched between the ground line 5b and the auxiliary ground line 5d. Signal line 5
The periphery of a is completely shielded by the ground wire 5b and the auxiliary ground wire 5d. Therefore, even if noise enters the signal line 5a from the outside, the noise is blocked by the ground line 5b and the auxiliary ground line 5d, and the noise does not enter the signal line 5a to cause the semiconductor element 4 to malfunction.

【００２５】また更に前記グランド線５ｂ及び補助グラ
ンド線５ｄにはその少なくとも一部に磁性粉末が含有さ
れた磁性領域を有しており、半導体素子４の作動に伴う
電源電圧の変動によって電源線５ｃとグランド線５ｂ及
び補助グランド線５ｄ間に発生するノイズは半導体素子
４に入り込む前にグランド線５ｂ及び補助グランド線５
ｄに含有されている磁性粉末で熱エネルギーに変換され
て吸収され、その結果、半導体素子４にこれらノイズが
入り込むことはなく、半導体素子４を常に正常に作動さ
せることができる。Further, each of the ground line 5b and the auxiliary ground line 5d has a magnetic region containing magnetic powder in at least a part thereof, and the power line 5c is changed by the fluctuation of the power voltage accompanying the operation of the semiconductor element 4. The noise generated between the ground line 5b and the auxiliary ground line 5d is prevented from entering the semiconductor element 4 before entering the ground line 5b and the auxiliary ground line 5d.
The magnetic powder contained in d converts it into heat energy and absorbs it. As a result, these noises do not enter the semiconductor element 4, and the semiconductor element 4 can always operate normally.

【００２６】 前記グランド線５ｂ及び補助グランド線
５ｄの少なくとも一部に含有される磁性粉末としてはＺ
ｎＦｅ２Ｏ４、ＭｎＦｅ２Ｏ４、ＦｅＦｅ２Ｏ４、Ｃｏ
Ｆｅ2Ｏ４、ＮｉＦｅ２Ｏ４、ＣｕＦｅ２Ｏ４や六方晶
フェライト（Ｂａ−Ｓｒ−Ｃｏ−Ｚｎ−Ｆｅ−Ｏ）の少
なくとも１種が好適に使用される。The magnetic powder contained in at least a part of the ground wire 5b and the auxiliary ground wire 5d is Z.
nFe 2 O 4 , MnFe 2 O 4 , FeFe 2 O 4 , Co
At least one of Fe 2 O 4 , NiFe 2 O 4 , CuFe 2 O 4 and hexagonal ferrite (Ba—Sr—Co—Zn—Fe—O) is preferably used.

【００２７】 前記ＺｎＦｅ２Ｏ４、ＭｎＦｅ２Ｏ４等
から成る磁性粉末は中性または還元性雰囲気中にて１２
００℃の温度で磁性を失うが、基体２を形成するＳｉＯ
２−Ａｌ２Ｏ３−ＭｇＯ−ＺｎＯ−Ｂ２Ｏ３系結晶性ガ
ラス等のガラスセラミックス焼結体の焼成温度が１０５
０℃以下と低いことから磁性領域を有するグランド線５
ｂ及び補助グランド線５ｄを基体２と同時焼成によって
形成しても磁性粉末が磁性を失うことはなく、これによ
って半導体素子４の作動に伴う電源電圧の変動に起因し
て電源線５ｃとグランド線５ｂ及び補助グランド線５ｄ
間に発生するノイズは磁性粉末により確実に熱エネルギ
ーに変換されて吸収することができる。The magnetic powder made of ZnFe 2 O 4 , MnFe 2 O 4 or the like is used in a neutral or reducing atmosphere.
Although it loses its magnetism at a temperature of 00 ° C., it forms the substrate 2.
The sintering temperature of the glass-ceramics sintered body such as 2- Al 2 O 3 —MgO—ZnO—B 2 O 3 based crystalline glass is 105.
Ground wire 5 having a magnetic region because it is as low as 0 ° C or less
Even if b and the auxiliary ground line 5d are formed by co-firing with the base body 2, the magnetic powder does not lose its magnetism, which causes the power line 5c and the ground line to change due to the fluctuation of the power voltage accompanying the operation of the semiconductor element 4. 5b and auxiliary ground wire 5d
The noise generated during the conversion can be reliably converted into heat energy by the magnetic powder and absorbed.

【００２８】前記グランド線５ｂ及び補助グランド線５
ｄの内部に含有される磁性粉末はその量が１０重量％未
満であると磁性粉末の絶対量が少なくなって電源線５ｃ
とグランド線５ｂ及び補助グランド線５ｄとの間に発生
するノイズを良好に吸収するのが困難となり、また７０
重量％を超えるとグランド線５ｂ及び補助グランド線５
ｄの導通抵抗が高くなり、半導体素子４に所定の電力を
供給するのが困難となる危険性がある。従って、前記グ
ランド線５ｂ及び補助グランド線５ｄの内部に含有され
る磁性粉末はその量を１０乃至７０重量％の範囲として
おくことが好ましい。The ground line 5b and the auxiliary ground line 5
If the amount of the magnetic powder contained in d is less than 10% by weight, the absolute amount of the magnetic powder becomes small and the power supply line 5c
It becomes difficult to satisfactorily absorb the noise generated between the ground line 5b and the auxiliary ground line 5d, and 70
If it exceeds 5% by weight, the ground wire 5b and the auxiliary ground wire 5
There is a risk that the conduction resistance of d becomes high and it becomes difficult to supply a predetermined electric power to the semiconductor element 4. Therefore, the amount of the magnetic powder contained in the ground wire 5b and the auxiliary ground wire 5d is preferably set in the range of 10 to 70% by weight.

【００２９】更に前記信号線５ａ、グランド線５ｂ、電
源線５ｃ等はその露出する表面にニッケル、金等から成
る耐蝕性に優れ、且つ良導電性の金属を従来周知のメッ
キ法によリ１．０乃至２０．０μｍの厚みに被着させて
おけば信号線５ａ、グランド線５ｂ、電源線５ｃが酸化
腐蝕して断線等をするのを有効に防止することができる
とともに信号線５ａやグランド線５ｂ、電源線５ｃ等へ
のボンディングワイヤ６の接続及び外部リードピンの取
着を確実となすことができる。従って、前記信号線５
ａ、グランド線５ｂ、電源線５ｃ等はその露出する表面
にニッケル、金等から成る耐蝕性に優れ、且つ良導電性
の金属を１．０乃至２０．０μｍの厚みに被着させてお
くことが好ましい。Further, the signal line 5a, the ground line 5b, the power supply line 5c, etc. are formed on the exposed surface by a well-known plating method, which is made of a metal such as nickel, gold, etc., which is excellent in corrosion resistance and has good conductivity. If it is adhered to a thickness of 0.0 to 20.0 μm, it is possible to effectively prevent the signal line 5a, the ground line 5b, and the power supply line 5c from being oxidized and corroded to cause disconnection and the like. It is possible to reliably connect the bonding wire 6 to the wire 5b, the power supply wire 5c, etc. and attach the external lead pin. Therefore, the signal line 5
a, the ground wire 5b, the power supply wire 5c, etc., should be coated on their exposed surfaces with a metal having good corrosion resistance and having good corrosion resistance, such as nickel, gold, etc., to a thickness of 1.0 to 20.0 μm. Is preferred.

【００３０】 また更に前記信号線５ａ、グランド線５
ｂ、電源線５ｃには外部リードピン７が取着されてお
り、該外部リードピン７は内部に収容する半導体素子４
の各電極を外部電気回路に電気的に接続する作用を為
し、コバール金属（Ｆｅ−Ｎｉ−Ｃｏ合金）や４２アロ
イ（Ｆｅ−Ｎｉ合金）等の金属を板状に加工したものが
使用されている。Furthermore, the signal line 5 a and the ground line 5
b, the external lead pin 7 is attached to the power supply line 5c, and the external lead pin 7 is housed inside the semiconductor element 4
Used to electrically connect each of the electrodes to an external electric circuit, and plate-shaped metal such as Kovar metal (Fe-Ni-Co alloy) or 42 alloy (Fe-Ni alloy). ing.

【００３１】前記外部リードピン７はまたその露出表面
にニッケル、金等を従来周知のメッキ法によリ１．０乃
至２０．０μｍの厚みに被着させておけば外部リードピ
ン７を外部電気回路に確実、且つ強固に接続させること
ができる。従って、外部リードピン７の露出表面にもニ
ッケル、金等を１．０乃至２０．０μｍの厚みに被着さ
せておくことが好ましい。If the exposed surface of the external lead pin 7 is coated with nickel, gold or the like to a thickness of 1.0 to 20.0 μm by a conventionally known plating method, the external lead pin 7 can be used as an external electric circuit. A reliable and strong connection can be achieved. Therefore, it is preferable that nickel, gold or the like is also deposited on the exposed surface of the external lead pin 7 to a thickness of 1.0 to 20.0 μm.

【００３２】更に前記基体２はその上面に後述する蓋体
３がガラス等から成る封止材８を介して接合され、これ
によって基体２と蓋体３とから成る容器内部に半導体素
子４が気密に収容される。Further, a lid 3 described later is joined to the upper surface of the base 2 via a sealing material 8 made of glass or the like, whereby the semiconductor element 4 is hermetically sealed inside the container made of the base 2 and the lid 3. Housed in.

【００３３】前記蓋体３は、酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体等の電気絶縁材料から成り、その下面中
央部に半導体素子４を収容する空所を形成するための凹
部Ｂが形成された椀状となっている。The lid 3 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. 4 has a bowl shape in which a concave portion B for forming an empty space is formed.

【００３４】前記蓋体３は例えば酸化アルミニウム質焼
結体から成る場合、酸化アルミニウム（Ａｌ2 Ｏ3 ）、
酸化珪素（ＳｉＯ2 ）、酸化マグネシウム（ＭｇＯ）、
酸化亜鉛カルシウム（ＣａＯ）等に適当な有機溶剤、溶
媒を添加混合して得た原料粉末を所定形状のプレス金型
内に充填するとともに一定圧力を印加して成形し、しか
る後、前記成形品を約１５００℃の温度で焼成すること
によって製作される。When the lid 3 is made of, for example, an aluminum oxide sintered body, aluminum oxide (Al 2 O 3 ),
Silicon oxide (SiO 2 ), magnesium oxide (MgO),
A raw material powder obtained by adding and mixing an appropriate organic solvent and a solvent to zinc calcium oxide (CaO) or the like is filled in a press die having a predetermined shape and is molded by applying a constant pressure, and then the molded product is formed. Is manufactured by firing at a temperature of about 1500 ° C.

【００３５】前記蓋体３はまたその凹部Ｂの内壁から下
面の一部にかけて銀、パラジウム等の金属から成る金属
層９が形成されており、該金属層９はその一部を基体２
の上面に形成したグランド線５ｂ上に直接接合させるこ
とによってグランド線５ｂに電気的に接続される。この
場合、内部に収容される半導体素子４は基体２に設けた
グランド線５ｂ（またはグランド線５ｂより分岐する補
助グランド線５ｄ）と該グランド線５ｂと電気的に接続
する蓋体３の金属層９とで完全に囲まれてシールドさ
れ、外部ノイズが蓋体３を介して入り込むことはなく、
内部に収容する半導体素子４を正常、かつ安定に作動さ
せることが可能となる。同時に内部に収容した半導体素
子４が発生するノイズは蓋体３を介して外部に漏れるこ
とも無くなり、外部装置に悪影響を与えることもない。The lid 3 is also provided with a metal layer 9 made of a metal such as silver or palladium extending from the inner wall of the recess B to a part of the lower surface thereof.
It is electrically connected to the ground line 5b by being directly joined to the ground line 5b formed on the upper surface of the. In this case, the semiconductor element 4 housed inside is the ground line 5b (or the auxiliary ground line 5d branched from the ground line 5b) provided on the base 2 and the metal layer of the lid 3 electrically connected to the ground line 5b. 9 is completely surrounded and shielded, and external noise does not enter through the lid 3,
The semiconductor element 4 housed inside can be operated normally and stably. At the same time, noise generated by the semiconductor element 4 housed inside does not leak to the outside through the lid body 3 and does not adversely affect the external device.

【００３６】前記金属層９は銀粉末、パラジウム粉末に
適当な有機溶剤、溶媒を添加混合することによって得た
金属ペーストを蓋体３の凹部Ｂ内壁及び下面一部に従来
周知のスクリーン印刷法等により塗布させ、しかる後、
これを９００℃の温度で焼き付けることによって蓋体３
の凹部Ｂ内壁及び下面一部に被着される。For the metal layer 9, a metal paste obtained by adding and mixing an appropriate organic solvent and a solvent to silver powder and palladium powder is formed on the inner wall of the recess B and a part of the lower surface of the lid 3 by a conventionally known screen printing method or the like. And then apply,
By baking this at a temperature of 900 ° C., the lid 3
It is attached to the inner wall of the recess B and a part of the lower surface.

【００３７】更に前記蓋体３の凹部Ｂ内壁に被着させた
金属層９には図２に示すように三角柱形状の突起１０が
複数個配列されている。Further, as shown in FIG. 2, a plurality of triangular prism-shaped projections 10 are arranged on the metal layer 9 adhered to the inner wall of the recess B of the lid 3.

【００３８】前記突起１０は内部に収容する半導体素子
４が作動時に発するノイズの放射方向を制御する作用を
なし、半導体素子４が作動時にノイズを発したとしても
そのノイズは突起１０で放射角度が制御されて元の半導
体素子４に入り込むことはなく、これよって半導体素子
４を常に正常、かつ安定に作動させることが可能とな
る。The protrusion 10 has a function of controlling the radiation direction of noise generated when the semiconductor element 4 housed therein operates. Even if the semiconductor element 4 emits noise during operation, the noise is emitted by the protrusion 10 at an emission angle. The semiconductor element 4 is not controlled and enters the original semiconductor element 4, and thus the semiconductor element 4 can always be operated normally and stably.

【００３９】前記突起１０は例えば、フェライト、亜
鉛、アルミニウム等の金属材料からなり、放電加工、プ
レス加工、いこみ加工等によって三角柱形状となしたも
のを金属層９にエポキシ樹脂等の接着材で接着すること
によって蓋体３の凹部Ｂ内壁に被着させた金属層９に形
成される。The protrusion 10 is made of, for example, a metal material such as ferrite, zinc or aluminum, and is formed into a triangular prism shape by electric discharge machining, press working, indentation or the like and is bonded to the metal layer 9 with an adhesive such as an epoxy resin. By doing so, the metal layer 9 adhered to the inner wall of the recess B of the lid 3 is formed.

【００４０】また前記突起１０は底辺の長さを０．２乃
至１．０ｍｍ、幅を０．２乃至１．０ｍｍ、高さを０．
３乃至１．０ｍｍの範囲とした三角柱形状を成してお
り、底辺の長さを０．２乃至１．０ｍｍ、幅を０．２乃
至１．０ｍｍ、高さを０．３乃至１．０ｍｍの範囲とし
ておくと、側面の角度が金属層９の面に対して３０乃至
８５゜となり、突起１０が半導体素子４の作動時に発し
たノイズの放射角度を効率よく制御し、ノイズが該ノイ
ズを発した元の半導体素子４に入り込むのを完全に防止
して、半導体素子４をより正常、かつ安定に作動させる
ことができる。従って、前記三角柱形状を成す突起１０
はその底辺の長さを０．２乃至１．０ｍｍ、幅を０．２
乃至１．０ｍｍ、高さを０．３乃至１．０ｍｍの範囲と
しておくことが好ましい。The protrusion 10 has a bottom length of 0.2 to 1.0 mm, a width of 0.2 to 1.0 mm, and a height of 0.
It has a triangular prism shape with a range of 3 to 1.0 mm, the base length is 0.2 to 1.0 mm, the width is 0.2 to 1.0 mm, and the height is 0.3 to 1.0 mm. The angle of the side surface is 30 to 85 ° with respect to the surface of the metal layer 9, and the protrusion 10 efficiently controls the radiation angle of the noise emitted during the operation of the semiconductor element 4, and the noise suppresses the noise. It is possible to completely prevent the emitted semiconductor element 4 from entering the original semiconductor element 4 and operate the semiconductor element 4 more normally and stably. Therefore, the protrusion 10 having the triangular prism shape is formed.
Has a bottom length of 0.2 to 1.0 mm and a width of 0.2
It is preferable to set the height in the range of 0.3 to 1.0 mm and the height in the range of 0.3 to 1.0 mm.

【００４１】なお、前記蓋体３に被着させた金属層９は
その露出表面を酸化アルミニウム、ムライト、窒化アル
ミニウム、炭化珪素等の電気絶縁材料から成る被覆層で
覆っておくと基体２に形成した信号線５ａ、グランド線
５ｂ、電源線５ｃ等に半導体素子４の各電極をボンディ
ングワイヤ６を介して接続する際、ボンディングワイヤ
６の一部が蓋体３に被着させた金属層９に接触して短絡
するのを有効に防止することができる。従って、前記蓋
体３に被着させた金属層９はその露出表面を電気絶縁材
料から成る被覆層で覆っておくほうが好ましい。The metal layer 9 deposited on the lid 3 is formed on the base 2 by covering the exposed surface with a coating layer made of an electrically insulating material such as aluminum oxide, mullite, aluminum nitride, or silicon carbide. When each electrode of the semiconductor element 4 is connected to the signal line 5a, the ground line 5b, the power line 5c, etc. via the bonding wire 6, a part of the bonding wire 6 is applied to the metal layer 9 adhered to the lid body 3. It is possible to effectively prevent contact and short circuit. Therefore, it is preferable that the exposed surface of the metal layer 9 applied to the lid 3 is covered with a coating layer made of an electrically insulating material.

【００４２】更に前記被覆層はその材質を蓋体３と実質
的に同一材質となしておくと蓋体３と被覆層との間に熱
が印加された際、両者間に両者の熱膨張係数の相違に起
因した熱応力が発生することは殆どなく、被覆層を蓋体
３に強固に被着させて金属層９を常に被覆することがで
きる。従って、前記被覆層は蓋体３と実質的に同一の材
質で形成しておくことが好ましい。Further, if the material of the coating layer is substantially the same as that of the lid body 3, when heat is applied between the lid body 3 and the coating layer, the coefficient of thermal expansion between the two is large. There is almost no occurrence of thermal stress due to the difference, and the metal layer 9 can be always covered by firmly applying the cover layer to the lid body 3. Therefore, it is preferable that the covering layer is formed of substantially the same material as the lid 3.

【００４３】 また一方、蓋体３を基体２上に接合させ
る封止材８はガラス、樹脂等から成り、例えば、ガラス
から成る場合、酸化鉛（ＰｂＯ）７５．０重量％、酸化
チタン（ＴｉＯ２）１０．０重量％、酸化ホウ素（Ｂ２
０３）５．０重量％、フッ素（Ｆ２）２．０重量％等を
含む低融点のガラスを準備し、該ガラスから成る封止材
８を基体２と蓋体３との間に配置させるとともにこれを
約３００℃の温度で溶融させることによって基体２と蓋
体３とは強固に接合される。また同時に封止材８がガラ
スから成る場合には基体２と蓋体３とから成る容器内部
への水分等の入り込みを有効に防止することができる。On the other hand, the sealing material 8 for bonding the lid 3 onto the base 2 is made of glass, resin, or the like. For example, when it is made of glass, lead oxide (PbO) 75.0% by weight, titanium oxide (TiO 2). 2 ) 10.0% by weight, boron oxide (B 2
0 3 ) 5.0 wt%, fluorine (F 2 ) 2.0 wt% and the like having a low melting point glass is prepared, and the sealing material 8 made of the glass is placed between the base 2 and the lid 3. The base 2 and the lid 3 are firmly bonded to each other by melting them at a temperature of about 300 ° C. At the same time, when the sealing material 8 is made of glass, it is possible to effectively prevent the entry of water or the like into the inside of the container made of the base body 2 and the lid body 3.

【００４４】なお、前記封止材８は蓋体３を基体２上に
接合させる際の作業性を考慮して予め蓋体３の下面に枠
状に被着されており、封止材８がガラスから成る場合に
はガラス粉末に有機溶剤、溶媒を添加混合することによ
って得たガラスペーストを蓋体３の下面に従来周知のス
クリーン印刷法等により所定厚みに印刷塗布しておくこ
とによって蓋体３の下面に予め枠状に被着される。この
場合、枠状の封止材８はその幅が０．６ｍｍ未満である
と封止材８を介して基体２と蓋体３とを接合させ基体２
と蓋体３とから成る容器内部に半導体素子４を気密に収
容する際、容器の気密封止の信頼性が劣化し、内部に収
容する半導体素子４を長期間にわたり、正常、且つ安定
に作動させるのが困難となる傾向にある。従って、前記
枠状の封止材８はその幅を０．６ｍｍ以上としておくこ
とが好ましい。The sealing material 8 is preliminarily applied to the lower surface of the lid 3 in a frame shape in consideration of workability when the lid 3 is bonded to the base body 2. In the case of glass, a glass powder obtained by adding and mixing an organic solvent and a solvent to glass powder is printed and applied on the lower surface of the lid 3 by a known screen printing method or the like to a predetermined thickness. It is preliminarily attached to the lower surface of 3 in a frame shape. In this case, if the frame-shaped sealing material 8 has a width of less than 0.6 mm, the base body 2 and the lid body 3 are bonded to each other via the sealing material 8.
When the semiconductor element 4 is hermetically housed in the container including the lid 3 and the lid 3, the reliability of hermetic sealing of the container is deteriorated, and the semiconductor element 4 housed inside is normally and stably operated for a long period of time. It tends to be difficult to do. Therefore, the frame-shaped sealing material 8 preferably has a width of 0.6 mm or more.

【００４５】かくして上述のパッケージによれば、基体
２の搭載部Ａに半導体素子４を取着搭載した後、半導体
素子４の各電極を基体２に形成した信号線５ａ及びグラ
ンド線５ｂにボンディングワイヤ６を介して接続し、最
後に基体２の上面に蓋体３を、該蓋体３の凹部内壁に被
着させた金属層９が基体２に形成したグランド線５ｂに
電気的に接続するようにしてガラス等から成る封止材８
を介して接合させ、基体２と蓋体３から成る容器内部に
半導体素子４を気密に封止することによって最終製品と
しての半導体装置となる。Thus, according to the above-mentioned package, after mounting the semiconductor element 4 on the mounting portion A of the base 2, the electrodes of the semiconductor element 4 are bonded to the signal line 5a and the ground line 5b formed on the base 2. 6, and finally, the lid 3 is electrically connected to the upper surface of the base 2, and the metal layer 9 adhered to the inner wall of the recess of the lid 3 is electrically connected to the ground wire 5b formed on the base 2. Sealing material 8 made of glass or the like
Then, the semiconductor element 4 is hermetically sealed inside the container composed of the base 2 and the lid 3 to form a semiconductor device as a final product.

【００４６】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば上述の実施例では蓋体
３に被着させた金属層を銀、パラジウムの金属粉末で形
成したが、タングステン、モリブデン等の他の金属粉末
で形成してもよい。The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-mentioned embodiments, the lid 3 is covered. Although the deposited metal layer is formed of silver or palladium metal powder, it may be formed of other metal powder such as tungsten or molybdenum.

【００４７】 また、蓋体３に被着させた金属層９と基
体２に形成したグランド線５ｂとの間に図３に示す如
く、コバール金属（Ｆｅ−Ｎｉ−Ｃｏ合金）等の金属部
材１１を介在させ、該金属部材１１を介して金属層９と
グランド線５ｂとを電気的に接続するようにしておけば
基体２と蓋体３との間に前記金属部材１１によって所定
の大きさの間隙が形成され、該間隙内に多量の封止材８
が介入されて基体２と蓋体３とから成る容器の気密封止
が完全となる。従って、前記基体２と蓋体３とから成る
容器の気密封止をより完全なものとするには蓋体３に被
着させた金属層９と基体２に形成したグランド線５ｂと
の間にコバール金属（Ｆｅ−Ｎｉ−Ｃｏ合金）等の金属
部材１１を介在させておくことが好ましい。Further, as shown in FIG. 3, a metal member 11 such as a Kovar metal (Fe—Ni—Co alloy) is provided between the metal layer 9 attached to the lid 3 and the ground wire 5b formed on the base 2. If the metal layer 9 and the ground line 5b are electrically connected via the metal member 11 with the interposition of, the metal member 11 provides a predetermined size between the base 2 and the lid 3. A gap is formed and a large amount of the sealing material 8 is provided in the gap.
Is intervened to complete the hermetic sealing of the container composed of the base body 2 and the lid body 3. Therefore, in order to complete the airtight sealing of the container composed of the base body 2 and the lid body 3, between the metal layer 9 adhered to the lid body 3 and the ground wire 5b formed on the base body 2 It is preferable to interpose a metal member 11 such as Kovar metal (Fe—Ni—Co alloy).

【００４８】更に前記実施例では半導体素子収納用パッ
ケージを例にとって説明したが、水晶振動子やＳＡＷフ
ィルタ等の他の種類の電子部品を収容するパッケージに
も適用可能である。Further, in the above-mentioned embodiment, the semiconductor element housing package has been described as an example, but the present invention can be applied to a package housing other kinds of electronic parts such as a crystal oscillator and a SAW filter.

【００４９】[0049]

【発明の効果】本発明の電子部品収納用パッケージによ
れば、電子部品の信号電極に接続される信号線をグラン
ド線と該グランド線より分岐した補助グランド線とで挟
み込むとともにグランド線及び補助グランド線の少なく
とも一部に磁性粉末を含有させたことから信号線に外部
からノイズが直接作用して入り込むことはなく、また搭
載する電子部品の作動に伴う電源電圧の変動によって電
源線とグランド線間に発生するノイズも電子部品に入り
込む前にグランド層または補助グランド層に含有されて
いる磁性粉末で熱エネルギーに変換されて吸収され、そ
の結果、電子部品にこれらノイズが入り込むことはな
く、電子部品を常に正常に作動させることができる。According to the electronic component storing package of the present invention, the signal line connected to the signal electrode of the electronic component is sandwiched between the ground line and the auxiliary ground line branched from the ground line, and the ground line and the auxiliary ground are provided. Since magnetic powder is contained in at least part of the wires, noise does not directly enter the signal wires from the outside, and due to fluctuations in the power supply voltage that accompanies the operation of the mounted electronic components, there is a gap between the power supply wire and the ground wire. The noise generated in the electronic component is also converted into thermal energy and absorbed by the magnetic powder contained in the ground layer or auxiliary ground layer before it enters the electronic component. Can always operate normally.

【００５０】また本発明の電子部品収納用パッケージに
よれば、蓋体の凹部内壁に金属層を被着させるとともに
該金属層を基体に形成したグランド線または補助グラン
ド線に電気的に接続させたことからパッケージ内部に収
容する電子部品はグランド線、補助グランド線及び金属
層で完全にシールドされることとなり、その結果、パッ
ケージの内部に収容する電子部品に外部ノイズが入り込
むことはなく、内部に収容する電子部品を正常、かつ安
定に作動させることが可能となる。According to the package for storing electronic parts of the present invention, a metal layer is deposited on the inner wall of the recess of the lid, and the metal layer is electrically connected to the ground line or the auxiliary ground line formed on the substrate. Therefore, the electronic components housed inside the package are completely shielded by the ground line, auxiliary ground line, and metal layer.As a result, external noise does not enter the electronic components housed inside the package, and It is possible to operate the electronic components housed therein normally and stably.

【００５１】更に本発明の電子部品収納用パッケージに
よれば、蓋体の凹部内壁に被着させた金属層に、例え
ば、底辺の長さが０．２乃至１．０ｍｍ、幅が０．２乃
至１．０ｍｍ、高さが０．３乃至１．０ｍｍである三角
柱形状をなす突起を複数個配列させたことからパッケー
ジ内部に収容する電子部品が作動時にノイズを発したと
してもそのノイズは突起で放射角度が制御されて元の電
子部品に入り込むことはなく、その結果、電子部品を正
常、かつ安定に作動させることが可能となる。Further, according to the electronic component storing package of the present invention, the base layer has a length of 0.2 to 1.0 mm and a width of 0.2 on the metal layer adhered to the inner wall of the recess of the lid. Since a plurality of triangular prism-shaped protrusions having a height of 1.0 mm to 1.0 mm and a height of 0.3 mm to 1.0 mm are arranged, even if the electronic components housed inside the package generate noise during operation, the noise is a protrusion. The radiation angle is not controlled by and does not enter the original electronic component, and as a result, it becomes possible to operate the electronic component normally and stably.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の電子部品収納用パッケージを半導体素
子を収容する半導体素子収納用パッケージを例にとって
説明するための断面図である。FIG. 1 is a cross-sectional view for explaining an electronic component storage package of the present invention by taking a semiconductor element storage package for storing a semiconductor element as an example.

【図２】図１に示す半導体素子収納用パッケージに使用
される突起を説明するための斜視図である。FIG. 2 is a perspective view for explaining a protrusion used in the semiconductor element housing package shown in FIG.

【図３】図１に示す半導体素子収納用パッケージの部分
拡大断面図である。FIG. 3 is a partially enlarged cross-sectional view of the semiconductor element housing package shown in FIG.

【符号の説明】[Explanation of symbols]

１・・・半導体素子収納用パッケージ ２・・・基体 ３・・・蓋体 ４・・・半導体素子 ５ａ・・信号線 ５ｂ・・グランド線 ５ｃ・・電源線 ５ｄ・・補助グランド線 ８・・・封止材 ９・・・金属層 １０・・・突起 1 ... Package for semiconductor element storage 2 ... Base 3 ... Lid 4 ... Semiconductor element 5a ... Signal line 5b ··· Ground wire 5c ... Power supply line 5d ... Auxiliary ground wire 8 ... Sealing material 9 ... Metal layer 10 ... Protrusion

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０５Ｋ 9/00 Ｈ０１Ｌ 23/14 Ｘ (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/04 H01L 23/00 H01L 23/02 H01L 23/12 H01L 23/14 H05K 9/00 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 identification code FI H05K 9/00 H01L 23/14 X (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/04 H01L 23 / 00 H01L 23/02 H01L 23/12 H01L 23/14 H05K 9/00

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 表面に電子部品が搭載される搭載部を有
し、表面及び内部に前記電子部品の信号電極、グランド
電極、電源電極が電気的に接続される信号線、グランド
線、電源線を有する基体と、前記搭載部に搭載される電
子部品を内部に収容するための凹部を有する蓋体とから
成り、基体と蓋体とを封止材を介し取着することによっ
て内部に電子部品を気密に収容するようになした電子部
品収納用パッケージであって、前記基体はガラスセラミ
ックス焼結体から成り、前記グランド線は少なくとも一
つの補助グランド線が分岐しており、該グランド線と補
助グランド線とで前記信号線を挟み込むとともにグラン
ド線、補助グランド線の少なくとも一部に磁性粉末を含
有させ、前記グランド線及び補助グランド線が前記基体
と同時焼成によって形成され、かつ蓋体の凹部内壁に三
角柱形状の突起が複数個配列された金属層を被着させる
とともに該金属層を前記基体のグランド線もしくは補助
グランド線に電気的に接続させたことを特徴とする電子
部品収納用パッケージ。1. A has a mounting portion on which an electronic component is to be mounted on the surface, the electronic component of the signal electrodes in the surface及beauty unit, the signal line where the ground electrode, the power supply electrodes are electrically connected, a ground line, It is composed of a base body having a power supply line and a lid body having a recess for accommodating an electronic component mounted in the mounting portion therein. By attaching the base body and the lid body via a sealing material, An electronic component storage package for hermetically storing electronic components, wherein the substrate is a glass ceramic.
At least one auxiliary ground wire is branched from the ground wire, the signal wire is sandwiched between the ground wire and the auxiliary ground wire, and at least a part of the ground wire and the auxiliary ground wire is magnetic. Powder is included, and the ground wire and the auxiliary ground wire are the base body.
And a metal layer having a plurality of triangular prism-shaped protrusions arranged on the inner wall of the recess of the lid , and the metal layer is electrically connected to the ground line or the auxiliary ground line of the base. This is a package for storing electronic components. 【請求項２】 前記金属層の三角柱形状の突起は底辺の
長さが０．２乃至１．０ｍｍ、幅が０．２乃至１．０ｍ
ｍ、高さが０．３乃至１．０ｍｍであることを特徴とす
る請求項１記載の電子部品収納用パッケージ。2. The triangular prism-shaped protrusions of the metal layer have a base length of 0.2 to 1.0 mm and a width of 0.2 to 1.0 m.
The package for storing electronic components according to claim 1, wherein m and height are 0.3 to 1.0 mm.
JP03281998A 1998-02-16 1998-02-16 Electronic component storage package Expired - Fee Related JP3495245B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03281998A JP3495245B2 (en) 1998-02-16 1998-02-16 Electronic component storage package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03281998A JP3495245B2 (en) 1998-02-16 1998-02-16 Electronic component storage package

Publications (2)

Publication Number Publication Date
JPH11233659A JPH11233659A (en) 1999-08-27
JP3495245B2 true JP3495245B2 (en) 2004-02-09

Family

ID=12369452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03281998A Expired - Fee Related JP3495245B2 (en) 1998-02-16 1998-02-16 Electronic component storage package

Country Status (1)

Country Link
JP (1) JP3495245B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344902A (en) * 2005-06-10 2006-12-21 Fujifilm Holdings Corp Semiconductor module
JP2010161271A (en) * 2009-01-09 2010-07-22 Panasonic Corp Semiconductor package

Also Published As

Publication number Publication date
JPH11233659A (en) 1999-08-27

Similar Documents

Publication Publication Date Title
JP3495246B2 (en) Electronic component storage package
JP2000340687A (en) Package for storing semiconductor elements
JPH0653355A (en) Package for storing electronic components
JP3495245B2 (en) Electronic component storage package
JP3495244B2 (en) Electronic component storage package
JP2851732B2 (en) Electronic component storage package
JPH11233661A (en) Electronic component storage package
JP2750232B2 (en) Electronic component storage package
JP3464138B2 (en) Electronic component storage package
JP2801449B2 (en) Package for storing semiconductor elements
JP2873105B2 (en) Package for storing semiconductor elements
JP3464136B2 (en) Electronic component storage package
JPH11150202A (en) Electronic component storage package
JP2813072B2 (en) Package for storing semiconductor elements
JPH11150201A (en) Electronic component storage package
JP3464143B2 (en) Electronic component storage package
JP2958201B2 (en) Package for storing semiconductor elements
JP3464137B2 (en) Electronic component storage package
JP2577088Y2 (en) Package for storing semiconductor elements
JP3716111B2 (en) Electronic component storage container
JP2750255B2 (en) Electronic component storage package
JP2851740B2 (en) Electronic component storage package
JP2813073B2 (en) Package for storing semiconductor elements
JP2746802B2 (en) Semiconductor device
JP3495247B2 (en) Electronic component storage container

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071121

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081121

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees