JP3490903B2 - Semiconductor light emitting device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optoelectronic integrated circuit (optoelectronic integrated circuit).
The present invention relates to a semiconductor light emitting element used in an ed circuit (OEIC), an image display device, and the like, and particularly to a semiconductor light emitting element using porous silicon and a manufacturing method thereof.

[0002]

2. Description of the Related Art Porous silicon (hereinafter referred to as "PS")
Has a different optical property from crystalline silicon (hereinafter referred to as “c-Si”), and generally has a large absorption edge energy. In addition, the electrical properties change, and the resistivity is generally higher than that of the original c-Si.

The porosity is 20 to 80% and the fine pore size is about 2n.
PS of m or less (hereinafter referred to as “nanostructured PS”) is c
Unlike -Si, it emits light in the visible light range. When this nanostructure PS is excited with light having a short wavelength in the blue to ultraviolet region, photoluminescence (PL) with a luminous efficiency (external quantum efficiency) of about 10% at maximum can be observed. Also,
Light emission (electroluminescence; EL) can also be obtained by injecting a current into the nanostructure PS.

On the other hand, PS having a porosity of 40 to 60% and a micropore diameter of about 2 to 50 nm (hereinafter referred to as "mesostructure PS") generally has a lower luminous efficiency than that of the nanostructure PS, and has an emission wavelength. Also has a wavelength generally longer than that of the nanostructured PS. The mesostructured PS has a slightly rougher structure than the nanostructured PS, and the electrical resistance is lower than that of the nanostructured PS.

Further, the porosity is lower than that of the mesostructured PS, PS having a fine pore size of 50 nm or more (hereinafter referred to as “macrostructured PS”) hardly emits light, and its electric resistance is higher than that of the mesostructured PS. Even lower.

PS is a solution containing hydrogen fluoride,
It is formed from the c-Si surface toward the inside by passing a current (anodic formation) using single crystal or polycrystal c-Si as an anode. For the cathode, a material such as platinum, which is usually insoluble in the chemical conversion solution, is used. Although PS and materials having a structure similar to PS can be produced by other methods, they are not important in the present invention and are therefore omitted.

As described above, PS is composed of a large number of fine holes having a diameter of about 1 to 100 nm, residual c-Si fine particles or skeleton, and an amorphous portion surrounding the fine particles. By changing conditions such as the conductivity type and resistivity of the original c-Si, the current density during anodization, the composition of the forming solution, the presence or absence of light irradiation, and the light irradiation intensity, the structure of PS produced is changed. Changed to the above nanostructure PS, mesostructure P
S, a macro structure PS or the like is obtained.

The nanostructure PS is obtained, for example, by anodizing c-Si containing p-type impurities (non-degenerate p-type) to the extent that degeneracy does not occur. It can also be obtained by anodizing the non-degenerate n-type c-Si having a low impurity density while irradiating light. This nanostructured PS has a porosity of 20-80.
%, The pore diameter is as fine as 2 nm or less. That is, since the size of the remaining c-Si fine particles or skeleton is fine, the resistance is higher than that of the original c-Si. The mesostructure PS can be obtained, for example, by anodizing c-Si containing degenerate p-type impurities (degenerate p-type) or degenerate n-type c-Si. The macrostructure PS can be obtained, for example, by anodizing non-degenerate n-type c-Si in the dark.

The above description of the three types of PS having different structures is about the general properties of typical ones. In reality, nanostructured PS and mesostructured P
There are PS having an intermediate property of S and PS having an intermediate property of mesostructured PS and macrostructured PS. In addition, for example, PSs belonging to the same nanostructure may have different fine structures due to the difference in the conductivity type of the original c-Si. Further, depending on the anodization conditions, PS having a different structure in the depth direction may be produced even if the original c-Si is uniform. Furthermore, even if the PS belongs to the mesostructure or the macrostructure PS in terms of the overall structure and properties, a PS that partially contains the nanostructure PS in the micro area may be produced depending on the anodization conditions.

Therefore, when manufacturing a light emitting device using PS, the device design such as how to use the PS layer of which structure and how to select a manufacturing method for manufacturing the device structure are selected. We must pay close attention to both sides.

Proceedings of the 44th Joint Lecture Meeting on Applied Physics, No. 2, P.I. 806, 31a-B-6 (Nishimura,
Nagao, Ikeda: "pn junction type photochemical conversion porous silicon LED"
It has been reported that the external quantum efficiency of EL emission is about 1% at maximum in a light emitting device using PS (hereinafter referred to as “PS light emitting device”). For this PS light-emitting element, a c-Si wafer having ap ⁺ -type c-Si layer formed on an n-type c-Si substrate is prepared, and a lamp is used.
It was produced by anodizing the surface of this c-Si wafer under the irradiation of light. When anodization is performed under such conditions, the p ⁺ -type c-Si layer on the surface having a low resistivity reaches the mesostructured PS layer and is an n-type c-S layer within a range where light from the lamp reaches.
The i substrate portion is the nanostructured PS layer, and the n-type c-Si substrate portion in the range where the light from the lamp does not reach is the macrostructure P layer.
It becomes the S layer. 22 and 23 show the structure and manufacturing method of the PS light emitting device.

In FIG. 22, a macro structure PS layer (hereinafter referred to as "n-type macro structure PS layer") 63 formed of n-type c-Si is formed on an n-type c-Si substrate 64. A nanostructured PS layer (hereinafter referred to as “n-type nanostructured PS layer”) 62 formed from n-type c-Si is formed on the structure PS layer 63, and further formed from p ⁺ -type c-Si. The formed mesostructured PS layer (hereinafter referred to as a p-type mesostructured PS layer) 61 is formed. The expressions such as “n-type macro structure PS layer”, “n-type nano structure PS layer”, and “p-type meso structure PS layer” are for convenience, and are different from n-type and p-type in c-Si. . This is because acceptor impurities and donor impurities are generally inactivated at room temperature in the PS layer.
A semi-transparent gold electrode 66 that serves as an anode electrode is formed on the p-type mesostructured PS layer 61, and an Al electrode 65 that serves as a cathode electrode is formed on the back surface of the n-type c-Si substrate 64. E is provided between the anode electrode 66 and the cathode electrode 65.
A DC power supply 67 for L light emission is connected. FIG. 22
In the structure shown in, the n-type nanostructured PS layer 62 functions as an EL light emitting layer. Further, the p-type mesostructured PS layer 61 and the n-type nanostructured PS layer 62 have a junction similar to the pn junction in c-Si (hereinafter, this type of junction by the PS layer is also referred to as “pn junction”). And the function of forming
It has a function of improving electrical contact with the semitransparent gold electrode 66.

In order to form the structure shown in FIG. 22, first, a thermal diffusion method is applied to the surface of an n-type c-Si substrate 72 having a thickness of 500 μm and a resistivity of 5 Ω-cm. A c-Si wafer 7 on which a p ⁺ type c-Si layer 71 having a rate of 2 × 10 ⁻³ Ω-cm is formed is prepared. And this c-S
The i-wafer 7 can be manufactured by anodizing as shown in FIG. That is, as shown in FIG. 23, a Teflon-made chemical conversion container 1 having an opening at the bottom is brought into close contact with the surface of the p ⁺ -type c-Si layer 71 by using an O-ring 2, and hydrofluoric acid is put into the Teflon-made container 1. -Fill with ethyl alcohol mixed formation solution 4. Since the O-ring 2 is used, the hydrofluoric acid / ethyl alcohol mixed chemical conversion solution 4 does not leak from the bottom of the Teflon chemical conversion container 1. The chemical conversion solution 4 is a mixture of 50 wt% hydrofluoric acid and 99.9 wt% ethyl alcohol in a volume ratio of 1: 1. A platinum electrode 3 is arranged in a hydrofluoric acid / ethyl alcohol mixed conversion solution 4. On the other hand, on the back surface of the n-type c-Si substrate 72, an Al electrode 65 which will eventually become a cathode electrode shown in FIG. 22 is provided, and the variable DC power supply 6 connected between the platinum electrode 3 and the Al electrode 65. As a result, a desired formation current is passed through the hydrofluoric acid / ethyl alcohol mixed formation solution. The anodization is performed while irradiating the p ⁺ -type c-Si layer 71 and the n-type c-Si substrate 72 thereunder by the tungsten lamp 5 arranged above the Teflon production-use container 1. Therefore, the platinum electrode 3 receives the light emitted from the tungsten lamp 5 c-
It is arranged so as not to prevent it from reaching the surface of the Si wafer 7.

The P-type mesostructured PS layer 61 shown in FIG. 22 can be formed by anodizing the p ⁺ -type c-Si layer 71 shown in FIG. In addition, the n-type nanostructured PS layer 62 shown in FIG. 22 is formed on a portion of the n-type c-Si substrate 72 shown in FIG. 23, which is close to the surface affected by light irradiation. Then, the n-type macro structure PS layer 63 is formed in the n-type c-Si substrate 72, at a portion far from the surface not affected by the light irradiation. The n-type c-Si substrate 64 shown in FIG. 22 is the portion of the n-type c-Si substrate 72 of FIG. 23 that remains as c-Si. According to the manufacturing method shown in FIG. 23, the nanostructured PS layer 6
2 becomes thicker as the anodization time becomes longer, and the macrostructure PS layer 63 formed thereunder becomes thicker accordingly. The anode electrode 66 in FIG. 22 is a semi-transparent gold electrode formed by vacuum evaporation of a gold thin film after anodization.

The luminous efficiency (quantum efficiency) of the nanostructured PS layer depends on the method of anodization and the formation time and is not always constant. In general, a nanostructured PS layer that has been sufficiently anodized with a long anodization time has a short anodization time, and has a higher luminous efficiency than a nanostructured PS layer with insufficient anodization.

[0016]

PS having such a structure
The external quantum efficiency and power efficiency of the light emitting device increase to some extent as the anodization time increases. This is because the quantum efficiency is improved when the anodization time becomes long and the anodization progresses sufficiently. However, if the anodization time is too long, the power efficiency will decrease again. This is because the nanostructured PS layer 62, which is a light emitting layer, becomes thicker as the anodization time increases and the external quantum efficiency gradually increases. However, when the thickness exceeds a certain thickness, the series resistance of the nanostructured PS layer having high resistance increases. This is because the effect comes into play. This can be understood by looking at FIG. That is, FIG. 24 shows the relationship between the series resistance Rs of such a PS light emitting device and the thickness d of the nanostructured PS layer 62. In FIG. 24, the ∘ mark indicates the series resistance R _S of the light emitting device having the n-type nanostructured PS layer shown in FIG. 22, and the ⋄ mark has almost the same device structure, but the light emitting layer is the p-type c-Si. 3 shows the series resistance Rs of the light emitting device made of the p-type nanostructured PS layer manufactured from. Almost R _S ∝
It can be seen that there is a relationship of d ² to ³ . Therefore, a light emitting element having a high external quantum efficiency inevitably has a high series resistance. Particularly, the series resistance of a PS light emitting device having a high external quantum efficiency of 0.1 to 1% has a large value of 100 kΩ to 1 MΩ, and thus a large driving voltage is required to inject current into such a PS light emitting device. . That is, the electric energy converted into heat energy is relatively increased as compared with the electric energy exchanged with the light energy, and the power efficiency is reduced.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to reduce the series resistance of the PS light emitting device and improve the power efficiency without impairing the external quantum efficiency. is there.

Another object of the present invention is to provide a PS light emitting device having a low operating voltage and a high external quantum efficiency.

Still another object of the present invention is to make it easy to control the thickness of the light emitting layer and to have high external quantum efficiency and power efficiency.
It is to provide a method for manufacturing an S light emitting device.

Still another object of the present invention is to provide a method for manufacturing a PS light emitting device which can be easily integrated on the same silicon substrate as an electronic device and can be manufactured at low cost.

[0021]

In order to achieve the above object, a first feature of the present invention is to provide a first first conductivity type nanostructured porous silicon (PS) layer and the first first conductivity type. Second conductivity type mesostructure P formed on the P-type nanostructure PS layer
The semiconductor light emitting device includes at least an S layer and a first first-conductivity-type mesostructured PS layer formed below the first first-conductivity-type nanostructured PS layer. Here, the "first conductivity type nanostructured PS layer" is an abbreviation for the nanostructured PS layer formed from the first conductivity type crystalline silicon (c-Si), and is referred to as "second conductivity type mesostructured PS layer". Is an abbreviation for a mesostructured PS layer formed of the second conductivity type c-Si. The “first conductivity type mesostructured PS layer” is the first conductivity type c.
It is an abbreviation for a mesostructured PS layer formed from -Si. The first first-conductivity-type nanostructured PS layer is a layer that functions as a main light emitting layer, but has a high resistivity (specific resistance). While the first
The first conductivity type mesostructured PS layer has a low luminous efficiency but a low resistivity. As described above, the “nanostructured PS layer” is a P having a porosity of 20 to 80% and a micropore size of about 2 nm or less.
It means the S layer. On the other hand, the “mesostructured PS layer” has a porosity of 4
It means a PS layer with 0 to 60% and a fine pore size of about 2 to 50 nm. A pn junction is formed between the first first-conductivity-type nanostructured PS layer and the second-conductivity-type mesostructured PS layer, and the second-conductivity-type mesostructured PS is converted into the first first-conductivity-type nanostructured PS layer. Carriers are injected to emit light.

The first conductivity type nanostructured PS layer of the present invention is a non-degenerate crystalline silicon (c-Si) having a low impurity density.
The layer may be formed by anodizing. That is, the first conductivity type non-degenerate c-Si layer is changed to the second conductivity type degenerate c having a high impurity density.
If the structure sandwiched between the -Si layer and the first conductivity type degenerate c-Si layer is anodized, only the first conductivity type non-degenerate c-Si layer becomes the nanostructured PS layer, so that the thickness can be accurately controlled. Becomes That is, according to the first aspect of the present invention, the thickness of the first first-conductivity-type nanostructured PS layer, which is the light emitting layer, is set to
It is possible to control the thickness so that _S does not increase and the maximum luminous efficiency is obtained. Conversely speaking, since the final thickness of the first conductive type nanostructured PS layer is limited to a predetermined thickness, a sufficient anodization time is spent during anodization to ensure a sufficient anodization. It is possible to do. That is, the nanostructured PS layer according to the first aspect of the present invention is, so to speak, a “complete nanostructured PS layer” in which “porous siliconization” has been sufficiently advanced. Therefore, according to the first feature of the present invention, since the light emission by the complete nanostructured PS layer is utilized, the conventional incomplete nanostructured PS layer is used.
The luminous efficiency (quantum efficiency) is extremely higher than that of the layer.

In the first aspect of the present invention, a second first-conductivity-type nanostructured PS layer and a second first-conductivity-type nanostructured PS layer are further provided under the first first-conductivity-type mesostructured PS layer.
It is preferably configured to include at least a second first conductivity type mesostructured PS layer below the layer. The second first-conductivity-type nanostructured PS layer is also a complete nanostructured PS layer. As described with reference to FIG. 24, the series resistance R _S of the nanostructured PS layer is proportional to the square or cube of the thickness d of the nanostructured PS layer. Becomes smaller rapidly. Therefore, if a plurality of thin nanostructured PS layers (N layers where N is a positive integer) are connected in series, the overall series resistance R _{S (total)} becomes a small value.

For example, one of the nanostructured PS layers having a single thickness is
An N-type nanostructured PS layer having a thickness of / N is prepared, and an N-1 layer of n-type mesostructured PS layer is sandwiched between the N layers to form a multilayer structure. In this case, the resistance of the mesostructured PS layer is much smaller than that of the nanostructured PS layer, and therefore contributes little to the series resistance. Therefore, the overall series resistance R _{S (total)} of this multilayer structure is reduced to 1 / N as compared with the case where the n-type nanostructure PS is a single layer. That is,
If the thickness of each layer of the nanostructured PS layers divided into multiple layers is selected so that the total thickness of the N layers is the same as that of the single-layered nanostructured PS layer, both layers have the same thickness as a whole, and therefore the emission intensity is Although it is almost comparable, the series resistance is drastically reduced due to the multilayer structure. Therefore, the power efficiency can be improved by the amount that the series resistance is reduced. It also emits light with a smaller operating voltage.

A second feature of the present invention relates to a method of manufacturing the semiconductor light emitting device of the first feature. That is, the second feature of the present invention is that the first degenerate crystalline silicon of the first conductivity type (c-
Si) layer, a first first conductivity type non-degenerate c-Si layer on top of the first first conductivity type degenerate c-Si layer, and an upper portion of the first first conductivity type non-degenerate c-Si layer. Preparing a c-Si wafer including at least the second conductivity type degenerate c-Si layer,
And a step of anodizing the c-Si wafer to form the first non-degenerate c-Si layer of the first conductivity type into the first PS layer of the first conductivity type nanostructured PS layer. That is. At this time, the first degenerate c-Si of the first conductivity type
The layer and the second-conductivity-type degenerate c-Si layer are c-Si layers having a high impurity density, and each has a mesostructure P due to anodization.
Since it becomes the S layer, if the thickness of the first non-degenerate c-Si layer of the first conductivity type having a low impurity density is accurately determined by the epitaxial growth method or the like, the first conductivity type nano-structure PS of the first conductivity type is obtained.
The thickness of the layer automatically becomes the thickness of the first non-degenerate c-Si layer of the first conductivity type, and since the thickness is not greater than this thickness, accurate thickness control is possible. First degenerate first conductivity type c-
A degenerate c-Si substrate may be used as the Si layer. Further, according to the second feature of the present invention, even if the anodization time is sufficiently long, the thickness of the first first-conductivity-type nanostructured PS layer does not increase. It is possible to proceed sufficiently. In the prior art, when the porous siliconization proceeds, the porous siliconization progresses from the surface layer side, and a nanostructure having a low degree of progress of the porous siliconization and a low luminous efficiency is formed in a portion far from the surface. . Moreover, although the thickness thereof is unnecessarily increased, the second feature of the present invention enables the formation of a complete nanostructured PS layer having a high luminous efficiency evenly in the thickness direction. Further, in the conventional technique, a certain thickness is required to sufficiently advance the porous siliconization, and it is difficult to reduce the film thickness. On the other hand, according to the second feature of the present invention, it is possible to form a complete nanostructured PS layer even with an extremely thin film thickness, and it is easy to reduce the film thickness.

In the first feature, it has been stated that the series resistance is further reduced by forming the nanostructured PS layer into multiple layers. Therefore, in order to form a multi-layered nanostructured PS layer, in the second aspect of the present invention, the c-Si wafer is the second first layer below the first degenerate c-Si layer of the first conductivity type.
At least a conductive type non-degenerate c-Si layer and a second first conductive degenerate c-Si layer below the conductive type non-degenerate c-Si layer are included, and a second first conductive type non-degenerate c-Si layer is formed into a second layer by anodization. A nanostructured PS layer may be used. Further, it is needless to say that a further multi-layer structure can be realized by adopting a structure in which the second and third non-degenerate c-Si layers of the first conductivity type and the degenerate c-Si layers are alternately laminated. A degenerate c-Si substrate may be used as the lowermost degenerate c-Si layer.

In the anodization in the second aspect of the present invention, the second conductivity type degenerate c-Si layer located on the uppermost layer of the above c-Si wafer is contacted with a conversion solution containing hydrogen fluoride, and c
A metal electrode may be provided on the lowermost surface of the -Si wafer, and an electric current may be passed between the metal electrode and the electrode provided in the chemical conversion solution containing hydrogen fluoride. At this time, if the first conductivity type is n-type, it is preferable to perform anodization while irradiating light.

It is needless to say that the c-Si in the first and second features of the present invention may be either single crystal Si or polycrystalline Si.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However,
The drawings are schematic, the relationship between thickness and plane dimensions,
It should be noted that the ratio of the thickness of each layer is different from the actual one. Therefore, the specific thickness and dimensions should be determined in consideration of the following description. Further, it is needless to say that the drawings include portions having different dimensional relationships and ratios.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows a structure of a semiconductor light emitting device according to the embodiment. Figure 1
As shown in FIG. 3, the semiconductor light emitting device according to the first embodiment of the present invention has the n-type mesostructure PS on the n ⁺ -type c-Si substrate 14.
Layer (first first-conductivity-type mesostructured PS layer) 13, thickness 2 μ
m n-type nanostructure PS layer (first first conductivity type nanostructure P
An S layer) 12 and a p-type mesostructured PS layer (second conductivity type mesostructured PS layer) 61 having a thickness of 0.6 μm are sequentially formed.
A semitransparent gold electrode 66 serving as an anode electrode is formed on the p-type mesostructured PS layer 61, and an Al electrode 65 serving as a cathode electrode is formed on the back surface of the n ⁺ -type c-Si substrate 14. A DC power supply 67 for EL light emission is connected between the anode electrode 66 and the cathode electrode 65. Figure 1
In the structure shown in (1), the n-type nanostructured PS layer 12 acts as an EL light emitting layer, but this thickness is accurately controlled to a thickness necessary for design, and becomes a completely nanostructured PS layer in which porous siliconization is sufficiently advanced. That is the feature of the present invention.
That is, as will be apparent from the description of the manufacturing method described later,
The n-type nanostructure PS layer 12 is a layer in which the non-degenerate n-type c-Si layer is made porous, and the thickness of the n-type nanostructure PS layer 12 is accurately controlled by the thickness of the non-degenerate n-type c-Si layer. ing.

The p-type mesostructured PS layer 61 has a function of forming a pn junction with the n-type nanostructured PS layer 12 and a function of improving electrical contact with the semitransparent gold electrode 66. There is.

FIG. 2 shows a method of manufacturing a semiconductor light emitting device according to the first embodiment of the present invention.

(A) First, as shown in FIG. 2, the thickness is 500 μm.
m, resistivity 1 × 10 ⁻³ Ω-cm, degenerate n ⁺ type c-Si substrate (first first conductivity type degenerate c-Si layer) 23 by epitaxial growth, thickness 2 μm, resistivity 1 Ω-cm. Non-degenerate n-type c-Si layer (first first conductivity type non-degenerate c-S
i layer) 23 and thickness 0.6 μm, resistivity 2 × 10 ⁻³
Ω-cm degenerate p ⁺ type c-Si layer (second conductivity type degenerate c-
A c-Si wafer 8 on which a Si layer) 71 is formed is prepared.

(B) Next, an Al electrode 65 is formed on the back surface of the degenerate n ⁺ type c-Si substrate 23 by using a vacuum evaporation method or a sputtering method. Thereafter, sintering is performed at 400 to 450 ° C. to improve the adhesion of the Al electrode 65 and reduce the contact resistance.

(C) After that, as shown in FIG. 2, a Teflon container 1 having an opening at the bottom is c-shaped using an O-ring 2.
-The surface of the Si wafer 8 is closely contacted, and the Teflon container 1 is filled with the hydrofluoric acid / ethyl alcohol mixed chemical conversion solution 4. Since the O-ring 2 is used, the hydrofluoric acid / ethyl alcohol mixed chemical conversion solution 4 does not leak from the bottom of the Teflon chemical conversion container 1. The chemical conversion solution 4 contains 50% by weight of hydrofluoric acid and 9
It is a mixture of 9.9% by weight of ethyl alcohol in a volume ratio of 1: 1. A platinum electrode 3 is arranged in a hydrofluoric acid / ethyl alcohol mixed conversion solution 4. A tungsten lamp 5 is arranged above the Teflon chemical conversion container. The platinum electrode 3 is the tungsten lamp 5.
It is arranged so as not to prevent the light emitted from the device from reaching the surface of the c-Si wafer 7.

(D) Next, the formation current of 30 mA / cm ² is applied for 6 minutes in the hydrofluoric acid / ethyl alcohol mixed formation solution by the variable DC power source 6 connected between the platinum electrode 3 and the Al electrode 65. At this time, the intensity of irradiation light on the surface of the c-Si wafer 8 is 2,0001x to 200, due to the tungsten lamp 5 arranged above the Teflon chemical conversion container 1.
Anodization is performed while irradiating light by adjusting the irradiation light intensity so as to be about 0001x, preferably about 20,000 lx. As a result, the degenerate p ⁺ type c-Si layer 71 becomes the p type mesostructured PS layer 61 by anodization. Also degenerate n ⁺ type c
A part of the —Si substrate 23 is also anodized to form the n-type mesostructured PS layer 13. On the other hand, the non-degenerate n-type c-Si layer 22 becomes the n-type nanostructured PS layer 12 by anodization, and the laminated structure shown in FIG. 1 is completed.

(E) After that, the Teflon chemical conversion container 1 and the like are removed, and gold is vapor-deposited on the surface of the p-type mesostructured PS layer 61 to a semitransparent thickness by vacuum vapor deposition or the like to form the anode electrode 66. Form. In FIG. 2, the p ⁺ -type c-Si layer 71 that is not in contact with the chemical conversion solution 4 and the portion located below this,
That is, although the c-Si layer remains in the peripheral portion of the c-Si wafer 8, the peripheral portion of the c-Si wafer 8 that remains without being anodized is cut and removed using a diamond blade or the like, as shown in FIG. The semiconductor light emitting device is completed. After this, the steps such as cutting on a die of a desired size and mounting on a predetermined lead frame etc. are carried out by a general LE.
It is similar to the process of D. The Al electrode 65 used as a contact for anodization is used as the cathode electrode 65. Of course, the Al electrode 65 used for the anodization may be removed once and a new metal electrode may be formed for the cathode electrode.

According to the method of manufacturing a semiconductor light emitting device described above, unlike the light emitting device using the conventional technique shown in FIGS. 22 and 23 and its manufacturing method, the nanostructure PS has a non-degenerate n-type c-type.
-Si layer 22 is formed only in the portion, and the other portions are all mesostructured PS layers. As a result, the thickness of the nanostructured PS layer 12, which is the light emitting layer, can be controlled to a thickness necessary for design,
Moreover, the porous siliconization can be sufficiently aged.

As described above, when the formation time of the nanostructured PS layer increases to some extent, the thickness thereof increases and the EL emission intensity increases. However, in the conventional technique, the thickness of the nanostructured PS layer inevitably increases with the formation time. Has a drawback that it becomes excessively thick and the resistance increases. On the other hand, FIG.
If the manufacturing method shown in FIG. 2 is used, the thickness of the nanostructured PS layer 12 is equal to or larger than the thickness of the non-degenerate n-type c-Si layer 22 (2 μm in the first embodiment of the present invention shown in FIG. 1) previously laminated. The mesostructured PS having a relatively low resistance even after the formation time has passed beyond the time for forming the optimum thickness of the nanostructured PS layer.
Only the layer 13 becomes thicker. Therefore, it is possible to obtain a perfect nanostructure having a high quantum efficiency by sufficiently increasing the formation time to promote the porous siliconization sufficiently. For this reason, the promotion of the porous siliconization necessary and sufficient to increase the quantum efficiency of the nanostructured PS layer 12 and its thickness are secured, and even if the excessive formation time elapses, the nanostructured PS layer 12 The thickness of 12 does not increase further, and the series resistance Rs of the manufactured light emitting element does not increase significantly beyond the value determined by the thickness of the designed desired nanostructured PS layer. Therefore, it is possible to provide a semiconductor light emitting device having high luminous efficiency as designed.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
2 shows a structure of a semiconductor light emitting device according to the embodiment. Figure 3
As shown in FIG. 4, the semiconductor light emitting device according to the second embodiment of the present invention has the fourth n-type mesostructured PS layer 13 and the fourth n-type nanostructured PS layer 31 on the n ⁺ -type c-Si substrate 14. , Third n-type mesostructured PS layer 32, third n-type nanostructured PS layer 3
3, second n-type mesostructured PS layer (second first conductivity type mesostructured PS layer) 34, second n-type nanostructured PS layer (second first conductivity type nanostructured PS layer) 35, First n-type mesostructured PS layer (first first conductivity type mesostructured PS layer) 36, first
N-type nanostructured PS layer (first first conductivity type nanostructured PS layer)
(Layer) 37 is formed in this order. The thickness of each of the third to first n-type mesostructured PS layers 32, 34, 36 is 0.
It is 1 μm. On the other hand, the fourth to first n-type nanostructured PS layers 3
The thickness of each of 1, 33, 35 and 37 is 0.5 μm. On the first n-type nanostructured PS layer 37, a thickness of 0.
6 μm p-type mesostructured PS layer (second conductivity type mesostructured PS layer)
(Layer) 61 is further formed. p-type mesostructured PS layer 6
A semi-transparent gold electrode 66 serving as an anode electrode is formed on the first electrode 1, and an Al electrode 65 serving as a cathode electrode is formed on the back surface of the n ⁺ type c-Si substrate 14. Anode electrode 6
A DC power supply 67 for EL light emission is provided between 6 and the cathode electrode 65. In the structure shown in FIG. 3, the fourth to first n-type nanostructured PS layers 31, 33, 35, 37
Acts as an EL light emitting layer, and this thickness is accurately controlled to the thickness required for design. That is, the fourth to first n
The type nanostructured PS layers 31, 33, 35, and 37 are layers in which the non-degenerate n-type c-Si layer having a low impurity density is made into porous silicon, and the thickness of the non-degenerate n-type c-Si layer set in advance is n. The thickness of the type nanostructured PS layer 12 is accurately controlled, and the anodization is sufficiently advanced so that high quantum efficiency is achieved. The p-type mesostructured PS layer 61 has a function of forming a pn junction with the first n-type nanostructured PS layer 37 and a function of improving electrical contact with the semitransparent gold electrode 66. ing.

FIG. 4 shows a method of manufacturing a semiconductor light emitting device according to the second embodiment of the present invention.

(A) First, as shown in FIG. 4, the thickness is 500 μm.
m, and a fourth non-degenerate n-type c-Si epitaxial growth layer 4 on the degenerate n ⁺ -type c-Si having a resistivity of 1 × 10 ⁻³ Ω-cm.
1, third degenerate n ⁺ type c-Si epitaxial growth layer 4
2, third non-degenerate n-type c-Si epitaxial growth layer 4
3, second degenerate n ⁺ type c-Si epitaxial growth layer (second first conductivity type degenerate c-Si layer) 44, second non-degenerate n type c-Si epitaxial growth layer (second first conductivity type) Non-degenerate c-Si layer) 45, first degenerate n ⁺ type c-Si
Epitaxial growth layer (first degenerate c-Si of the first conductivity type)
Layer) 46, a first non-degenerate n-type c-Si epitaxial growth layer (first first conductivity type non-degenerate c-Si layer) 47, and a degenerate p ⁺ type c-Si epitaxial growth layer (second conductivity type degenerate c). The c-Si wafer 9 in which the -Si layer) 71 is continuously epitaxially grown in this order is used. Fourth to first non-degenerate n-type c-Si epitaxial growth layers 41, 43, 4
5 and 47 each have a thickness of 0.5 μm and a resistivity of 5 Ω-c.
m is an epitaxial growth layer. Further, the third to first degenerate n ⁺ type c-Si epitaxial growth layers 42, 44, 4
6 has a thickness of 0.1 μm and a resistivity of 1 × 10 ⁻³ cm.
The degenerate p-type c-Si epitaxial growth layer 71 is an epitaxial growth layer having a thickness of 0.6 μm and a resistivity of 2 × 10 ⁻³ cm.

(B) Next, an Al electrode 65 is formed on the back surface of the degenerate n ⁺ type c-Si substrate 23 by using a vacuum evaporation method or the like.
Further, sintering is performed at a predetermined temperature.

(C) After that, as shown in FIG. 4, a Teflon container 1 having an opening at the bottom is c-shaped using an O-ring 2.
The surface of the Si wafer 9 is brought into close contact, and the Teflon container 1 is filled with the hydrofluoric acid / ethyl alcohol mixed chemical conversion solution 4. Since the O-ring 2 is used, the hydrofluoric acid / ethyl alcohol mixed chemical conversion solution 4 does not leak from the bottom of the Teflon chemical conversion container 1. The chemical conversion solution 4 contains 50% by weight of hydrofluoric acid and 9
It is a mixture of 9.9% by weight of ethyl alcohol in a volume ratio of 1: 1. A platinum electrode 3 is arranged in a hydrofluoric acid / ethyl alcohol mixed conversion solution 4. A tungsten lamp 5 is arranged above the Teflon chemical conversion container. The platinum electrode 3 is the tungsten lamp 5.
It is arranged so as not to prevent the light emitted from the device from reaching the surface of the c-Si wafer 7.

(D) Next, by the variable DC power source 6 connected between the platinum electrode 3 and the Al electrode 65, a formation current of 30 mA / cm ² is flowed in the hydrofluoric acid / ethyl alcohol mixed formation solution for 6 minutes. . At this time, by the tungsten lamp 5 arranged above the Teflon chemical conversion container 1, c-S
Anodization is performed while irradiating light so that the irradiation light intensity on the surface of the i-wafer 8 becomes 20,000 lx. As a result, the fourth to the first non-degenerate n-type c-Si epitaxial growth layers 41, 43, 45 and 47 become the fourth to the first n-type nanostructured PS layers 31, 33, 35 and 37, respectively. In addition, a part of the degenerate n ⁺ type c-Si substrate 23, the third to the first degenerate n ⁺
The c-Si epitaxial growth layers 42, 44, 46 are the fourth to first n-type mesostructured PS layers 13, 32, 3 respectively.
4,36. Further, the degenerate p ⁺ type c-Si layer 71 becomes the p type mesostructured PS layer 61.

(E) After that, the Teflon chemical conversion container 1 and the like are removed, and gold is vapor-deposited on the surface of the p-type mesostructured PS layer 61 by a vacuum vapor deposition method to a semitransparent thickness to form the anode electrode 66. Form. C-Si located outside the O-ring
Since the c-Si layer remains on the peripheral portion of the wafer 8, it is cut and removed with a diamond blade or the like. Thus, the semiconductor light emitting device shown in FIG. 3 is completed. Note that the subsequent dicing and assembling steps are the same as those of a general LED, and the description thereof will be omitted. The Al electrode 65 used as a contact for anodization is used as the cathode electrode 65. Of course, the Al electrode 65 used for the anodization may be removed once and a new metal electrode may be formed for the cathode electrode.

As shown in FIG. 3, the fourth to first n-type nanostructured PS layers 31, 33, 35 and 37 are connected by the third to first n-type mesostructured PS layers 32, 34 and 36. Then, the fourth to first n-type nanostructured PS layers 31, 33, 3
The series resistance R _S can be reduced as compared with a semiconductor light emitting device having a single-layer nanostructured PS layer having the same thickness as the total thickness of 5,37 four layers. This is because the series resistance R _S of the n-type nanostructured PS layer increases in proportion to the square of the thickness as shown in FIG. Thus, for example the series R _S resistance of the n-type nanostructure PS layer with a thickness of 2μm is 16 times of the series resistance Rs of the nanostructure PS layer having a thickness of 0.5 [mu] m. However, as shown in FIG. 3, when the four n-type nanostructured PS layers having a thickness of 0.5 μm are connected in series by the n-type mesostructured PS having a low resistance, the total series resistance R _{S (total)} is It is only about four times as large as a single layer of 0.5 μm nanostructured PS layer. Generally, the total series resistance R _{S (total-div)} of a multilayer structure in which an n-type nanostructured PS layer having a thickness of d / N and an N layer is connected by an n-type mesostructured PS layer is a single layer having a thickness of d. Nano structure PS
Approximately 1 / the _total series resistance R _{S (total-single) of the} layer
It can be reduced to N. If it is manufactured by the method as shown in FIG.
N-type nanostructured PS layers 31, 33, 35 having high luminous efficiency,
37 is an original non-degenerate n-type c-Si layer 41, 43, 45,
As in the case of the first embodiment, accurate film thickness control, sufficient porous siliconization are promoted, and the luminous efficiency of the nanostructured PS layer can be improved because it can be formed only in the portion 47.

FIG. 5 shows the EL external quantum efficiency and the series resistance R of the semiconductor light emitting device (marked with a circle) according to the second embodiment of the present invention.
Show the relationship with s. For comparison, FIG. 5 shows the relationship between the EL external quantum efficiency and the series resistance R _S of the conventional semiconductor light emitting device (marked with Δ) and the semiconductor light emitting device according to the first embodiment of the present invention (marked with □). Are also shown at the same time.

The anodization conditions of the conventional semiconductor light emitting devices according to the first and second embodiments are the same. Further, the thickness (2 μm) of the nanostructured PS layer 12 of the semiconductor light emitting device according to the first embodiment and the nanostructured PS layers 31, 33, 3 of the semiconductor light emitting device according to the second embodiment.
The sum of the thicknesses of the four layers of 5,37 (0.5 μm × 4 = 2 μm) is the same. E of each semiconductor light emitting device shown in FIG.
The L external quantum efficiencies are almost the same, but a significant difference is observed in the series resistances R _S. That is, the thickness of the nanostructured PS layer of the conventional semiconductor light emitting device indicated by a triangle is 8
Since it is as thick as μm, the series resistance Rs is the largest at about 120 kΩ. On the other hand, in the semiconductor light emitting device according to the first embodiment of the present invention shown by □, the thickness of the nanostructured PS layer can be accurately controlled to be thinned to 2 μm, and the series resistance R _S is about 8 kΩ.
It is reduced to 1/15. The series resistance R _S of the semiconductor light emitting device according to the second embodiment of the present invention shown by a circle is 1.6 kΩ, which is 1/5 of that of the semiconductor light emitting device according to the first embodiment. And the smallest value has been achieved. Thus, the effect of reducing the series resistance R _S of the semiconductor light emitting device according to the second embodiment of the present invention is clear.

(Third Embodiment) The PS layer can be formed on the same c-Si substrate as the semiconductor integrated circuit (IC). Therefore, the semiconductor light emitting device of the present invention can be easily integrated into an IC such as an optoelectronic integrated device (OEIC) or a display for displaying an image, and can be applied to various fields. A technique of selective diffusion may be used for integration. That is, if a multi-layer diffusion region including a degenerate c-Si layer and a non-degenerate c-Si layer is formed in a predetermined portion of a Si wafer, the present invention is selectively applied to a portion of the multi-layer diffusion region centering on the degenerate c-Si layer. The semiconductor light emitting device structure can be formed.

FIG. 6 shows a 512 × 512 PS light emitting diode (LE) in the center of a 300 mmφ silicon wafer.
D) A data driver 1 for arranging an array and driving a PS light emitting diode (LED) array on the periphery thereof.
9 is a schematic diagram of a display device in which circuits such as 09 and a scan driver 115 are integrated.

FIG. 7 is a block diagram showing the structure of the display device shown in FIG. This display device includes PS light emitting diodes (L
It is a gradation control type LED display device for gradation control of lighting time of (ED). The data input control circuit 103 receives the clock signal CK1 while the select signal SE is "H".
In synchronization with the above, predetermined display data is fetched and given to the RAM. For example, 8-bit display data may correspond to 1 dot and may show 255 levels of brightness. RA
The M105 stores the 8-bit data for 512 dots and outputs it to the gradation control circuit 107. Gradation control circuit 10
7 controls the lighting time for each dot in 255 gradations based on 8-bit display data. Driver circuit for data (data driver) based on lighting time with gradation control
Reference numeral 109 simultaneously drives the PS-LED 101a for 512 dots.

On the other hand, the two-stage counter 1 which is reset by the reset signal RE and is synchronized with the clock signal CK1
The signals output from 11a and 111b are output to the decoder 11
3 is input to the scan driver circuit (scan driver) 115. Scan driver circuit 11
Each time the data driver circuit 109 drives the 512-dot LED 101a, the LED 5 sequentially scans the 512-dot LED 101a.

FIG. 8 is a schematic sectional view showing the LED matrix portion. As shown in FIG. 8, in the matrix portion of the LED display device according to the third embodiment of the present invention, the n ⁺ type c-Si buried layer 14 is formed on the p type c-Si substrate 83. And this n ⁺ type c-Si
An n-type mesostructured PS layer (first first-conductivity-type mesostructured PS layer) 13 and an n-type nanostructured PS layer (first first-conductivity-type nanoscale layer) having a thickness of about 1 to 2 μm are formed on the buried layer 14. Structure PS
Layer) 12, p-type mesostructure P having a thickness of about 0.5 to 1 μm
The S layer (second conductivity type mesostructured PS layer) 61 is sequentially formed. n ⁺ type c-Si buried layer 14, n type mesostructured PS layer 13, n type nanostructured PS layer 12, p type mesostructured P
The S layer 61 is formed as a plurality of electrically isolated regions separated by the element isolation region 86. A plug (electrode lead-out portion) 85 penetrating the p-type mesostructured PS layer 61, the n-type nanostructured PS layer 12, and the n-type mesostructured PS layer 13 to reach the n ⁺ -type c-Si buried layer 14 is formed. . The plug (electrode extraction portion) 85 is the LED 101a.
Becomes the cathode electrode of. The plug 85 is formed of a refractory metal such as impurity-doped polysilicon (doped polysilicon) or tungsten (W). On the p-type mesostructured PS layer 61, a transparent electrode 87 such as an ITO film or a SnO2 film which serves as an anode electrode of the LED 101a is formed. The transparent electrode 87 is connected to a scan line 96 made of a metal such as aluminum or an aluminum alloy, and the plug 85 is connected to a data line 89. The data line 89 is also made of metal such as aluminum or aluminum alloy. The data line 89 and the transparent electrode 87 are separated by the first interlayer insulating film 88, and the scan line 96 and the data line 89 are separated by the second interlayer insulating film 9.
Separated by 5. A DC power supply 67 for EL light emission is connected between the anode electrode 66 and the cathode electrode 65. With such a configuration, it is possible to easily form a display device in which the semiconductor light emitting element region is arranged in the central portion of the large-diameter silicon wafer and the drive circuit of the semiconductor light emitting element region is arranged in the peripheral portion of the silicon wafer.

As shown in FIG. 8, the LED display device according to the third embodiment of the present invention can be manufactured as follows.

(A) First, the diameter is 300 mm, the thickness is 1 mm,
Degenerate n ⁺ type c-Si substrate 2 having a resistivity of 1 × 10 ⁻³ Ω-cm 2
3 has a thickness of 5 μm and a resistivity of 10 Ω-cm to 2 × 10 ^-2 Ω-cm by non-degenerate p-type c.
-Form a Si layer. Then, an ion implantation mask 131 made of metal and having a thickness of about 1 μm is formed on the peripheral portions of the c-Si substrate 23 where the scan driver circuit 115 and the data driver circuit 109 are to be formed. Using this ion implantation mask 131, first, as shown in FIG. 9A, the acceleration energy is 3 MeV to 5 MeV and the dose amount is 4 ×.
Ion-implant 10 ¹⁶ cm ^-2 arsenic ( ⁷⁵ As ⁺ ). Further, in order to correct the lattice distortion due to the high concentration ion implantation, the acceleration energy is 2.5 MeV to 4 MeV, and the dose amount is 4
Phosphorus ( ³¹ P ⁺ ) of × 10 ¹⁶ cm ^-2 is ion-implanted and heat-treated to form a degenerate n ⁺ -type c-Si buried layer. Further, as shown in FIG. 9B, the acceleration energy is 0.8 MeV using the ion implantation mask 131.
To 1.5 MeV, dose 1 × 10 ¹³ cm ^{−2 to} 4 ×
Non-degenerate n-type c-Si layer 22 is formed by ion-implanting 10 ¹⁴ cm ⁻² of phosphorus ( ³¹ P ⁺ ) and performing heat treatment. Further, as shown in FIG. 9C, using an ion implantation mask 131, an acceleration energy of about 50 KeV,
Dose amount Dose amount 4 × 10 ¹⁶ cm ^-2 boron ( ¹¹ B ⁺ ).
Is ion-implanted and heat-treated. As a result, FIG.
As shown in (d), on the degenerate n ⁺ type c-Si substrate 23, the degenerate n ⁺ type c-Si buried layer 24 and the non-degenerate n type c
The -Si layer 22 and the degenerate p ⁺ -type c-Si layer 71 are selectively formed in the central portion of the wafer.

(B) Then, an Al electrode 65 is formed on the back surface of the degenerate n ⁺ type c-Si substrate 23 by a vacuum deposition method or a sputtering method. Then 400-45
Sintering is performed at 0 ° C. to improve the adhesion of the Al electrode 65 and reduce the contact resistance.

Thereafter, as shown in FIG. 10 (e), a Teflon container 1 having an opening at the bottom is brought into close contact with the surface of a 300 mmc-Si wafer by using an O-ring 2. The O-ring 2 is located at the boundary between the LED array section and the peripheral circuit section. Since the LED array section 101 is quadrangular, it is preferable to open a quadrangular window at the bottom of the Teflon container 1. Therefore, the O-ring 2 is also guided by the O-ring groove as shown in FIG. Then, as in the case of FIG. 2 described above, the Teflon container 1 is filled with the hydrofluoric acid / ethyl alcohol mixed chemical conversion solution 4, and a chemical conversion current is passed between the platinum electrode 3 and the Al electrode 65 for 6 minutes. At this time, the intensity of irradiation light on the surface of the c-Si wafer 8 is 2,0001x to 200,0001 by the tungsten lamp 5 arranged above the Teflon chemical conversion container 1.
x, preferably about 20,000 lx, and the anodization is performed while adjusting the irradiation light intensity and irradiating light. As a result, the degenerate p ⁺ -type c-Si layer 71 is p-typed by anodization.
It becomes the type mesostructured PS layer 61. Also degenerate n ⁺ type c-Si
A part of the buried layer 24 is similarly anodized to become the n-type mesostructured PS layer 13. The remaining degenerated n ⁺ type c-Si buried layer 24 becomes the degenerated n ⁺ type c-Si buried layer 14. On the other hand, the non-degenerate n-type c-Si layer 22 is n-typed by anodization.
The nano-structured PS layer 12 is formed, and the laminated structure as shown in FIG.

(C) Next, the bonding insulating film 81 is formed on the p-type mesostructured PS layer 61 by the CVD method, and the surface thereof is mirror-finished by the CMP method or the like. On the other hand, separately,
A 300 mmc-Si wafer 82 is prepared, and its surface is C
Mirror finish by MP method or the like. Then, the surfaces are joined together to form a direct bonding substrate as shown in FIG. Then, the back surface of this direct bonding substrate is shown in FIG.
As shown in (g), grinding and polishing, degenerate n ⁺ type c-
The thickness of the Si substrate 23 is reduced to 2 to 10 μm (or the degenerate n ⁺ type c-Si substrate 23 is removed to expose the degenerate n ⁺ type c-Si buried layer 14). Hereinafter, the degenerated n ⁺ type c-Si substrate 23 that remains thin is also referred to as the “degenerated n ⁺ type c-Si buried layer” 14. Then, the surface of the degenerate n ⁺ type c-Si buried layer 14 is mirror-finished by the CMP method or the like.

(D) Further, another c-Si wafer 83 having a diameter of 300 mm and a resistivity of about 10 to 500 Ω-cm is prepared, and its surface is mirror-finished by the CMP method or the like.
Then, the surfaces are joined together to form a direct bonding substrate as shown in FIG. Then, this time, the 300 mmc-Si wafer 82 directly bonded previously is removed by grinding and polishing, and as shown in FIG. 13I, the bonding insulating film 81 is also removed.

(E) Next, as shown in FIG.
-Type mesostructured PS layer 61, n-type nanostructured PS layer 12 and n
A groove 91 penetrating the type mesostructured PS layer 13 and reaching the n ⁺ type c-Si buried layer 14 is formed. The formation of the groove 91 is
An etching mask made of a silicon oxide film is first formed on the p-type mesostructured PS layer 61, and CF ₄ , SF ₆ , CBrF ₃ , SiC is used as a mask for the silicon oxide film.
RIE or ECR ion etching with l ₄ , or CCl ₄ may be performed. It is also effective to cool the substrate to -110 ° C to -130 ° C during this trench etching.

(F) Then, as shown in FIG. 14K, the surface of the groove 91 is thermally oxidized to form an oxide film 84.
Then, as shown in FIG.
By E, the oxide film 84 at the bottom of the groove 91 is removed. After that, as shown in FIG. 15M, a refractory metal such as impurity-doped polysilicon (doped polysilicon) or tungsten (W) is embedded in the groove 91 to form a plug 85 serving as an electrode lead-out portion. Form. Then, the surface is further planarized by the CMP method.

(G) Next, as shown in FIG.
The element isolation trench 92 is formed through the p-type mesostructured PS layer 61, the n-type nanostructured PS layer 12, the n-type mesostructured PS layer 13, and the n ⁺ -type c-Si buried layer 14. And
As shown in FIG. 16O, an element isolation oxide film 86 is embedded in the element isolation trench 92. Then, the surface is further planarized by the CMP method.

(H) After that, as shown in FIG. 16P, a transparent electrode 87 such as an ITO film or a SnO ₂ film is formed by the CVD method or the sputtering method. And RIE
By the method, as shown in FIG. 17 (q), the transparent electrode 87 is separated into the positions of the dots forming the matrix. After separating the transparent electrode 87, peripheral circuits such as the scan driver circuit 115 and the data driver circuit 109 are formed in the peripheral portion of the c-Si substrate 23 by using a known MOS transistor process or the like. After forming the polysilicon gate region of the peripheral circuit, the polysilicon gate region and the transparent electrode 8
As shown in FIG. 17 (r), an oxide film, PS,
A first interlayer insulating film 88 such as a G film or a BPSG film is formed. A contact hole is opened in this first interlayer insulating film 88, a data line 89 made of a metal such as aluminum or an aluminum alloy is formed, and is connected to a plug 85 as shown in FIG. 18 (s). At the same time, required metal wiring of the peripheral circuit section is performed. Then, an oxide film, a PSG are further formed on the data line 89 and the required metal wiring of the peripheral circuit section.
Film, BPSG film, second interlayer insulating film 9 such as Si3N4 film
5 is formed. A contact hole is opened in the second interlayer insulating film 95, and a scan line 96 made of a metal such as aluminum or an aluminum alloy is connected to the transparent electrode 87.
8 and connecting the required metal wiring in the peripheral circuit section,
The matrix portion of the LED display device according to the third embodiment of the present invention shown in is completed. Although the final passivation film is omitted in FIG. 8, the final passivation film is formed as necessary, as is well known to those skilled in the art.

Even if the method shown in FIGS. 11 (f) to 13 (i) is not adopted, the n ⁺ type c is formed on the p type c-Si substrate 83 as shown in FIG. 13 (i). A structure in which the —Si buried layer 14, the n-type mesostructured PS layer 13, the n-type nanostructured PS layer 12, and the p-type mesostructured PS layer 61 are sequentially formed can be realized. For example, first, diameter 300mm, thickness 1
mm, the resistivity of 10 to 500 Ω-cm, and the degenerate n ⁺ type c-Si embedded layer 23, the non-degenerate n type c-Si layer 22, and the degenerate p ⁺ type c on the non-degenerate p type c-Si substrate 83.
-Si layer 71 is formed by epitaxial growth. Then, from the back surface of the non-degenerate p-type c-Si substrate 83, as shown in FIG.
As shown in, a groove reaching the n ⁺ type c-Si buried layer 23 may be opened, a cathode electrode may be provided, and a formation current may flow between the platinum electrode 3 and the cathode electrode. However, since the n ⁺ -type c-Si burying layer 14 is thin, the resistance at this portion is large and the anodization may be non-uniform. Therefore, the diameter is 300mm
11 (f) to FIG.
It is preferable to use the direct bonding method as shown in (i).

In the structure shown in FIG. 8, since the element isolation oxide film 85 is transparent, there is light leakage from adjacent dots. Therefore, in order to obtain a clear image, the light shielding region 142 as shown in FIG. 20 may be formed in the element isolation oxide film 85. A metal such as tungsten (W) may be used for the light shielding region 142. In FIG. 20, a Bragg reflection film 141 made of a dielectric multilayer film is further arranged under the n ⁺ type c-Si buried layer 14 so that light can be efficiently emitted from the surface. The Bragg reflection film 141 made of a dielectric multilayer film is
In the process of direct bonding of FIG. 12 (h), n ⁺ type c-Si
It may be sandwiched between the buried layer 14 and the c-Si wafer 83.

Further, a structure may be adopted in which the c-Si wafer 83 under the LED array portion is removed by etching to extract light below the wafer. In this case, the diameter is 300 mm
The non-degenerate n-type c-Si layer 22 and the degenerate p + -type c-Si layer 71 are formed on the degenerate n + -type c-Si substrate by epitaxial growth, and finally, the degenerate n + -type layer under the LED array section. Since the c-Si substrate may be selectively removed by etching, it is not necessary to use the direct bonding method as shown in FIGS. 11 (f) to 13 (i). However, since it has a large area, there are problems in the warp and mechanical strength of the wafer.

Although a wafer having a diameter of 300 mm (12 inches) has been described as an example of a large diameter wafer in the above, it goes without saying that other wafer sizes such as 4 inches to 8 inches may be used.

(Other Embodiments) As described above, the present invention has been described by the first to third embodiments.
The discussion and drawings forming a part of this disclosure should not be understood as limiting the invention. From this disclosure, various alternative embodiments, embodiments, and operation techniques will be apparent to those skilled in the art.

For example, in the first and second embodiments, the case where the n-type nanostructured PS layer in which the non-degenerate n-type c-Si layer was anodized under light irradiation was used as the EL light emitting layer was described. Of course, the p-type nanostructured PS layer formed by forming the non-degenerate p-type c-Si layer by reversing the conductivity type of the c-Si layer may be used as the light emitting layer. In this case, the p-type / n-type in the first and second embodiments are all inverted. Note that the non-degenerate p-type c-Si layer becomes a p-type nanostructured PS layer even after anodization without light irradiation.
The tungsten lamps shown in 4 and 4 can be omitted. Further, as shown in FIG. 24, the value of the series resistance Rs of the p-type nanostructured PS layer increases in proportion to the cube of the thickness of the p-type nanostructured PS layer. By dividing into a large number of layers, the effect of the multi-layer division becomes more remarkable.

In the third embodiment, it has been shown that a light emitting diode array using PS layers arranged in a matrix can form a large area light emitting element at a low cost. However, even if the PS light emitting diode is not divided into a plurality of parts so as to form a dot matrix, it is possible to provide a light emitting device for indoor lighting or the like in which the entire surface of a silicon wafer having a diameter of 8 to 12 inches is used as a light emitting region. FIG. 21 is a partial cross-sectional view of a light emitting device in which the entire surface of such a silicon wafer is used as a light emitting region.
When the resistance of the semi-transparent gold electrode comes into play due to the increase in area, as shown in FIG. 21, stripe-shaped low resistance electrode wiring 97 is provided, and a transparent electrode layer 87 such as a thick ITO film or SnO ₂ film is formed. It may be formed on the p-type mesostructured PS layer 61.

As described above, it should be understood that the present invention includes various embodiments and the like not described here. Therefore, the present invention is limited only by the matters specifying the invention according to the scope of claims, which is appropriate from this disclosure.

[0073]

As described above in detail, the present invention provides a semiconductor light emitting device using porous silicon having high EL light emission efficiency (quantum efficiency) and low series resistance.
In particular, the thickness of the nanostructured PS layer that contributes to EL emission is controlled to a desired thickness with low series resistance and maximum luminous efficiency,
In addition, since the quality of the PS layer can be improved so that the maximum quantum efficiency can be obtained, the light emission efficiency can be easily improved.

According to the present invention, the nanostructured PS layer that contributes to EL emission is divided into a plurality of thin layers, the thickness for obtaining the maximum emission efficiency as a whole is secured, and the series resistance can be dramatically reduced. , The operating voltage is lowered, and the power efficiency and the light emission efficiency are improved.

According to the present invention, it is possible to easily control the thickness of the nanostructured PS layer that contributes to EL emission, and to secure a sufficiently long anodization time so that the maximum quantum efficiency can be obtained.
Since the anodization can be promoted, the production yield is high and the productivity is improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor light emitting device according to a first embodiment of the present invention.

FIG. 2 is a schematic view illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment of the invention.

FIG. 3 is a sectional view showing a structure of a semiconductor light emitting device according to a second embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating a method for manufacturing a semiconductor light emitting device according to a second embodiment of the invention.

FIG. 5 is a diagram showing a relationship between external quantum efficiency and series resistance of each of the semiconductor light emitting devices according to the first and second embodiments of the present invention and the prior art.

FIG. 6 is a schematic diagram of a display device using a 300 mmφ silicon wafer according to a third embodiment of the present invention.

7 is a block diagram showing a configuration of the display device shown in FIG.

FIG. 8 is a schematic cross-sectional view showing an LED matrix portion.

FIG. 9 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 1).

FIG. 10 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 2).

FIG. 11 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 3).

FIG. 12 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 4).

FIG. 13 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 5).

FIG. 14 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 6).

FIG. 15 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 7).

FIG. 16 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 8).

FIG. 17 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 9).

FIG. 18 is a schematic process sectional view explaining the manufacturing method of the LED display device according to the third embodiment of the present invention (No. 10).

FIG. 19 is a schematic diagram illustrating another method for manufacturing the LED display device according to the third embodiment of the invention.

FIG. 20 is an L according to a modification of the third embodiment of the present invention.
It is a typical sectional view showing an ED matrix part.

FIG. 21 is a schematic cross-sectional view showing a part of a light emitting device for indoor lighting according to another embodiment of the present invention.

FIG. 22 is a cross-sectional view showing an example of a structure of a conventional semiconductor light emitting device using PS.

23 is a schematic diagram illustrating a method for manufacturing the semiconductor light emitting device shown in FIG.

FIG. 24 is a diagram showing the relationship between the thickness of the nanostructured PS layer and the series resistance.

[Explanation of symbols]

1 Teflon chemical conversion container 2 O-ring 3 Platinum electrode 4 Hydrofluoric acid / ethyl alcohol mixed chemical solution 5 Tungsten lamp 6 Variable DC power supply 7, 8, 9, 82, 83 c-Si wafer 12 n-type nanostructured PS layer 13 n -Type mesostructured PS layer 14 n ⁺ -type c-Si layer 22 n-type c-Si layer 23 n ⁺ -type c-Si layer 31 Fourth n-type nanostructured PS layer 32 Third n-type mesostructured PS layer 33 Third n-type nanostructured PS layer 34 Second n-type mesostructured PS layer 35 Second n-type nanostructured PS layer 36 First n-type mesostructured PS layer 37 First n-type nanostructured PS layer 41 4 n-type c-Si epitaxial growth layer 42 3rd n ⁺ -type c-Si epitaxial growth layer 43 3rd n-type c-Si epitaxial growth layer 44 2nd n ⁺ -type c-Si epitaxial growth layer 45 2nd n-type c-Si epitaxy Le growth layer 46 first n ⁺ -type c-Si epitaxial layer 47 a first n-type c-Si epitaxial layer 61 p-type mesostructure PS layer 65 cathode electrode (Al electrode) 66 anode electrode (translucent gold electrode) 67 DC power source 71 p ⁺ type c-Si layer 81 Insulating insulating film 85 Plug (electrode extraction portion) 86 Element isolation oxide film 86 Element isolation region 87 Transparent electrode 88 First interlayer insulating film 89 Data line 91 Groove 92 Element Separation groove 95 Second interlayer insulating film 96 Scan line 97 Electrode wiring 101a PS-LED 101 LED array section 103 Data input control circuit 105 RAM 107 Gradation control circuit 109 Data driver 111 Counter 113 Decoder 115 Scan driver 131 Ion implantation Mask 141 Bragg reflection film 142 Light shielding area

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-6-97500 (JP, A) JP-A-7-288337 (JP, A) JP-A-6-310816 (JP, A) JP-A-6- 77102 (JP, A) JP 8-139359 (JP, A) JP 10-135500 (JP, A) JP 10-269932 (JP, A) JP 55-71081 (JP, A) JP-A-6-163982 (JP, A) JP-A-6-97419 (JP, A) JP-A-5-327017 (JP, A) JP-A-9-506211 (JP, A) JP-A-5-502978 (JP, A) Tokumei Hyo 6-509685 (JP, A) Proceedings of 44th Joint Lecture on Applied Physics, 1997, No. 2, p. 806 31a-B-6 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 33/00 H05B 33/10 H05B 33/14

Claims (5)

(57) [Claims] 1. A first conductivity type nanostructured porous silicon layer and a second conductivity type mesostructured porous silicon layer formed on the first conductivity type nanostructured porous silicon layer. And a first first conductivity type mesostructured porous silicon layer formed below the first first conductivity type nanostructured porous silicon layer. 2. A second first conductivity type nanostructured porous silicon layer and a second first conductivity type mesostructured porous silicon layer under the first first conductivity type mesostructured porous silicon layer. The semiconductor light emitting device according to claim 1, comprising at least: 3. The first first-conductivity-type nanostructured porous silicon layer, the second-conductivity-type mesostructured porous-silicon layer, and the first first-conductivity-type mesostructured-porous-silicon layer are central to a silicon wafer. 3. The semiconductor light emitting device according to claim 1 or 2, wherein the integrated circuit is stacked on the silicon wafer, and an integrated circuit is arranged in the other region of the silicon wafer. 4. A first first-conductivity-type degenerate crystalline silicon layer, and a first first-conductivity-type non-degenerate-crystalline silicon layer on top of the first first-conductivity-type degenerate-crystalline silicon layer. A step of preparing a crystalline silicon wafer including at least a second conductive type degenerate crystalline silicon layer above the first first conductive type non-degenerate crystalline silicon layer; and anodizing the crystalline silicon wafer. The first the first
And a step of forming the conductive type non-degenerate crystalline silicon layer into a first first conductive type nanostructured porous silicon layer. 5. The crystalline silicon wafer further comprises a second layer below the first first conductivity type degenerate crystalline silicon layer.
Of the first conductivity type non-degenerate crystalline silicon layer, and at least a second first conductivity type non-degenerate crystalline silicon layer thereunder, wherein the second first conductivity type non-degenerate crystalline layer is formed by the anodization. The method for manufacturing a semiconductor light emitting device according to claim 4, wherein the silicon layer is a second nanostructured porous silicon layer.