JP3486041B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device such as a dynamic RAM having a redundant structure.

[0002]

2. Description of the Related Art In a semiconductor memory device, when a normal memory cell becomes defective due to a defect, the defective memory cell can be replaced with a redundant memory cell prepared in advance, and the device can be repaired as a good product. Has been done. This is an indispensable technique for improving the device yield, and efficient relief is an important point for improving the yield and reducing the cost.

A generally known alternative method for defective memory cells is defective because a normal memory cell in a certain block in a memory cell array composed of a plurality of memory cell blocks divided according to an address has a defect. In this case, the entire block including the defective memory cell is replaced with the redundant memory cell block.

A semiconductor memory device adopting a conventional alternative method of defective memory cells will be described below with reference to FIGS. 12, 13, 14, 15, and 16.

FIG. 12 is a block diagram of a conventional semiconductor memory device. FIG. 13 is a circuit configuration diagram of the redundant memory cell block selecting fuse circuit block FB00 in FIG. 12, which is a redundant memory cell block selecting fuse circuit block FB01, FB10, FB11 ,.
The FB31 has the same configuration as the redundant memory cell block selecting fuse circuit block FB00. 14
FIG. 13 is a circuit configuration diagram of the redundant decoder SDEC00 in FIG. 12, showing redundant decoders SDEC01 and SDEC1.
0, SDEC11, ..., SDEC31 are redundant decoders S
It has the same configuration as DE00. 15 is the same as FIG.
3 is a circuit configuration diagram of a normal decoder control circuit NDC0 in FIG. 1, in which normal decoder control circuits NDC1 to NDC3 have the same configuration as the normal decoder control circuit NDC0. 16 is shown in FIG.
2 is a circuit configuration diagram of a normal decoder NDEC00 in FIG.
n, NDEC10 to NDEC1n, NDEC20 to ND
EC2n and NDEC30 to NDEC3n have the same configuration as the normal decoder NDEC00.

12, FIG. 13, FIG. 14, FIG. 15 and FIG. 16, MCA0 is a memory cell array, which has normal memory cell blocks NCB00 to NCB0n and redundant memory cell blocks SCB00, SCB01. MCA1 to MCA3 are memory cell arrays MCA
0 is another memory cell array having the same structure as 0, FB00, FB01, FB10, FB11, ..., F
B31 is a fuse circuit block for selecting a redundant memory cell block, SDEC00, SDEC01, SDEC10,
SDEC11, ..., SDEC31 are redundant decoders, ND
EC00 to NDEC0n, NDEC10 to NDEC1
n, NDEC20 to NDEC2n, NDEC30 to ND
EC3n is a normal decoder, NDC0 to NDC3 are normal decoder control circuits, and XA0 to XB0.
To 3, XC0 to 3 are address signals, RSL0 to RSL3
Is a memory cell array selection signal, WDRV0 to WDRV3
Is a word line drive signal, WDRV00 to WDRV03, W
DRV10 to WDRV13, WDRV20 to WDRV2
3, WDRV30 to WDRV33 are normal word line drive signals, WL00, WL01, WL02, WL03, ...
Is a normal word line, SWL00, SWL01, SWL
02, SWL03, SWL04, SWL05, SWL0
6, SWL07 is a redundant word line, RSP00, RSP0
1, RSP10, RSP11, ..., RSP31 are redundancy instruction signals, PRCH is a signal, VCC is a power supply voltage, VSS is a ground voltage, QP0 to QP1 are P-type MOS transistors,
QN0 to QN47 are N-type MOS transistors, FU0 to FU0
FU11 is a fuse.

In such a conventional example, a plurality of normal memory cell blocks each having four normal word lines and two redundant memory cell blocks each having four redundant word lines are provided in each memory cell array. For selecting these redundant memory cell blocks,
A fuse circuit block for selecting a redundant memory cell block is provided for each redundant memory cell block. For example, for the memory cell array MCA0, in order to replace the normal memory cell blocks NCB00 to NCB0n, two redundant memory cell blocks SCB00, SCB are provided.
Fuse circuit blocks FB00 and FB01 for redundant memory cell block selection are provided for B01. Further, one normal decoder provided for each normal memory cell block controls four normal word lines connected to each normal memory cell block, and for one redundant memory cell block. Redundant decoders provided one by one control four redundant word lines connected to each redundant memory cell block. The word line drive signals WDRV0 to WDRV3 are partially decoded by the least significant bit A0R of the row address and the immediately upper bit A1R thereof, and one of them is selected by the logic voltage of each of A0R and A1R and has a predetermined word line potential. The address signals XA0 to XA3 are set by the upper bits A2R and A3R
The address signals XB0 to XB3 have higher bits A4.
The address signals XC0 to XC3 are further partially decoded by R and A5R by their higher bits A6R and A7R, respectively.

The memory cell array is selected by the memory cell array selection signals RSL0 to RSL3. Selection of a normal memory cell block in one memory cell array is performed by address signals XA0-3, XB0-3, XC.
This is performed by selecting the normal decoder from 0 to 3. The normal word line in the selected memory cell block is selected by the word line drive signals WDRV0 to WDV.
RV3 is connected to each normal decoder via the normal decoder control circuit. Normal word line drive signals WDRV00 to WDRV03, WDRV10 to WDRV
13, WDRV20 to WDRV23, WDRV30 to W
It is performed by DRV33.

In the conventional structure as described above, for example, one normal memory cell block including a defective memory cell exists in the normal memory block provided in the memory cell array MCA0, and the normal memory cell block SCB00, When it is desired to substitute one of the SCB01, the fuse corresponding to the address of the block including the defective memory cell is blown in any of the redundant memory cell block selecting fuse circuit blocks FB00 and FB01. As a result, the block including the defective memory cell is replaced with the redundant memory cell block corresponding to the redundant memory cell block selecting fuse circuit block in which the fuse has been blown, and the redundant memory cell block is used. If there are two normal memory cell blocks including defective memory cells and two redundant memory cell blocks SCB00 and SCB01 are to be used as substitutes, the redundant memory cell block selection fuse circuit blocks FB00 and FB01 are respectively used. By cutting the fuses corresponding to the addresses of the two blocks including the defective memory cells, the two blocks including the defective memory cells are replaced by the redundant memory cell blocks SCB00 and SCB01, respectively.

The detailed circuit operation of the semiconductor memory device adopting the alternative method of the defective memory cell according to the conventional example will be described below with reference to FIGS. 13, 14 and 15.

Here, the memory cell array is MCA0-M.
It is assumed that MCA0 of CA3 is selected. In the initial state, in the redundant memory cell block selection fuse circuit block FB00 shown in FIG.
Is a logic "LOW" (hereinafter referred to as "L") P-type MOS
The transistor QP0 is on, and the address signals XA0-3,
XB0-3 and XC0-3 are all "L" and N-type MOS
The transistors QN0 to QN11 are off, and the redundancy instructing signal RSP00 has a logic "High" (hereinafter referred to as "H"). Further, all the memory cell array selection signals RSL0 to RSL3 are "L" and all the word line drive signals WDRV0 to WDRV3 are "L". Therefore, the redundancy decoder SDEC00 shown in FIG.
, The redundant word lines SWL00 to SWL03 are "L".

First, the signal PRCH becomes "H" and the P-type M
The OS transistor QP0 is turned off. Then, the memory cell array selection signal RSL which was initially "L"
Of 0 to RSL3, RSL0 becomes "H". Further, at the beginning, one of the address signals XA0 to XA3, which is all "L", one of XB0 to 3 and one of XC0 to 3 becomes "H" and is selected. When the address of the memory cell block changes, twelve N-type MOS transistors QN0 to QN0-Q corresponding to the change of the address signal.
Three of N11 are turned on.

At this time, the combination of the addresses set to "H" is not the address of the block including the defective memory cell in the memory cell array MCA0, and
Redundant memory cell block selecting fuse circuit block FB0 provided corresponding to the memory cell array MCA0
When neither 0 nor FB01 match the combination of addresses corresponding to the blown fuses, both the redundancy instruction signals RSP00 and RSP01 are "L". Therefore, the redundant decoder SDEC0 shown in FIG.
0 or SDEC01, the N-type MOS transistors QN13, QN16, QN19, and QN22 are off and the N-type MOS transistors QN14, QN17, and QN are turned off even if the memory cell array selection signal RSL0 becomes "H".
Since N20 and QN23 are on, all redundant word lines SWL00 to SWL07 remain "L" even if any one of the selected word line drive signals WDRV0 to WDRV3 becomes a predetermined word line potential. Is. That is, none of the redundant memory cell blocks SCB00 and SCB01 are selected.

However, the combination of the above "H" addresses is the address of the block including the defective memory cell in the memory cell array MCA0, which is the redundant memory cell block selecting fuse circuit block F.
If the combination of the addresses corresponding to the blown fuses at B00 matches, the redundancy instruction signal RSP0
0 remains “H”. Therefore, in the redundant decoder SDEC00 shown in FIG. 14, when the memory cell array selection signal RSL0 becomes "H", the N-type MOS transistors QN13, QN16, QN19, QN22 are turned on, and the N-type MOS transistors QN14, QN17, QN.
Since 20 and QN23 are turned off, the word line drive signal W
When a selected one of DRV0 to WDRV3 has a predetermined word line potential, the potential is transferred to the corresponding redundant word line. That is, the redundant memory cell block SCB00 is selected.

At this time, as described above, the redundancy instruction signal RS
Since P00 is "H", in the normal decoder control circuit NDC0 shown in FIG. 15, even if the memory cell array selection signal RSL0 becomes "H", the N-type MOS
Transistors QN25, QN28, QN31, QN34
Is off, and N-type MOS transistors QN26, QN
29, QN32, QN35 are on. Therefore,
All the normal word line drive signals WDRV00 to WDRV are generated even if one selected one of the word line drive signals WDRV0 to WDRV3 has a predetermined word line potential.
03 remains "L", and the memory cell array MC concerned
All normal memory cell blocks NCB00 of A0
~ NCB0n is not selected.

If the combination of the above-mentioned "H" addresses coincides with the combination of the addresses corresponding to the fuses blown in the redundant memory cell block selecting fuse circuit block FB01, the redundant memory cell block. Fuse circuit block for selection FB00
Similarly to the case where the combination of the addresses corresponding to the blown fuses is matched, the redundant memory cell block SCB01 is selected and the redundancy instruction signal RSP01 is "H". Therefore, all the normal memory cell blocks of the memory cell array MCA0 are selected. NCB00 to NCB0n
Is deselected. Therefore, the normal memory cell block selected by the combination of the above-mentioned "H" addresses is the redundant memory cell selected by the redundant memory cell block selecting fuse circuit block in which the fuse corresponding to the address is cut. It will be replaced by a block.

Here, when the fuse is blown, 1
For one redundant memory cell block selecting fuse circuit block, one of four corresponding to the address signals XA0 to XA, one of four corresponding to XB0 to 3, and X
One fuse out of four fuses corresponding to C0 to 3 is cut.

[0018]

However, the replacement by the redundant memory cell block in the above-mentioned conventional semiconductor memory device is such that one normal memory cell block controlled by one normal decoder is used for selecting the redundant memory cell block. The replacement is limited to one redundant memory cell block by the fuse circuit block. Therefore, the degree of substitution is low, and the more redundant memory cell blocks are prepared in one memory cell array to improve the repair rate, the more redundant memory cell block selecting fuse circuit blocks are required. There is a problem that the area is expanded and the cost is increased.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device having a structure that suppresses an increase in chip area and enhances replacement efficiency of redundant memory cell blocks.

[0020]

According to the semiconductor memory device of the first aspect of the present invention, a memory cell array having a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, and the plurality of normal memories are provided. In order to replace a plurality of defective normal memory cell blocks of the cell blocks with some or all of the plurality of redundant memory cell blocks, the defective normal memory cell blocks are cut corresponding to the addresses of the plurality of defective normal memory cell blocks. A redundant memory cell block selecting fuse circuit block having a plurality of fuses, a normal decoder for controlling access to the normal memory cell block, and a redundant decoder for controlling access to the redundant memory cell block, Multiple defective normal memory cell blocks An address signal from the redundant memory cell block selecting fuse circuit block, in which the fuse has been blown corresponding to an address, is input to the redundant decoder, so that the defective normal memory cell blocks are divided into the plural normal memory cell blocks. The address signal is replaced by a part or all of the redundant memory cell block,
It is a signal of the lowest address in the normal memory cell block selection address set in the redundant memory cell block selecting fuse circuit block.

In the semiconductor memory device according to the first configuration of the present invention, two normal memory cell blocks, one normal memory cell block and another normal memory cell block adjacent to the one normal memory cell block, are provided. When the normal memory cell block is replaced by the two redundant memory cell blocks, the common part of the addresses of the address of the one normal memory cell block and the address of the other normal memory cell block is one of the above. By cutting and selecting a common fuse of the redundant memory cell block selecting fuse circuit blocks, and by cutting and selecting two of the plurality of fuses corresponding to the lowest address, the lowest addresses different from each other are selected. The above two normal memory cell blocks are replaced with the above two redundant memory cell blocks. It is better to replace it with a hook.

According to the semiconductor memory device of the second configuration of the present invention, a memory cell array having a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, and a defective one of the plurality of normal memory cell blocks. To replace a certain normal memory cell block with a part or all of the plurality of redundant memory cell blocks, a plurality of fuses are cut corresponding to addresses of the defective normal memory cell blocks. A redundant memory cell block selecting fuse circuit block; a normal decoder for controlling access to the normal memory cell block; and a redundant decoder for controlling access to the redundant memory cell block. Corresponds to the address of the normal memory cell block Then, the address signal from the redundant memory cell block selecting fuse circuit block whose fuse has been blown is input to the redundant decoder, so that the defective normal memory cell blocks are transferred to the redundant memory cells. The plurality of normal memory cell blocks are replaced by some or all of the blocks, and each of the plurality of normal memory cell blocks is a normal memory cell block to which a combination of a plurality of addresses is allocated for each normal memory cell block. The arrangement form of the combination is a combination of addresses assigned to one normal memory cell block and a combination of addresses assigned to other normal memory cell blocks adjacent to the one normal memory cell block. Is the union of the above addresses Characterized in that only any one of the addresses of said plurality of addresses which configuration is arranged form always placed the address combination of differently each other.

In the semiconductor memory device according to the second configuration of the present invention, a redundant decoder selection signal determined according to a combination of the addresses assigned to the normal memory cell block is input to the redundant decoder. As a result, the defective normal memory cell blocks may be replaced with some or all of the redundant memory cell blocks.

Further, two normal memory cell blocks, one normal memory cell block and another normal memory cell block adjacent to the one normal memory cell block, are replaced with two normal memory cell blocks and two redundant memory cell blocks. , The common part of the addresses of the address of the one normal memory cell block and the address of the other normal memory cell block is a common fuse of the redundant memory cell block selecting fuse circuit block. By cutting, and selecting different addresses, and by cutting and selecting two of the plurality of fuses corresponding to the different addresses,
It is preferable to replace the two normal memory cell blocks with the two redundant memory cell blocks.

In the semiconductor memory device according to the first and second configurations of the present invention, the number of the redundant memory cell block selecting fuse circuit blocks may be smaller than the number of the redundant memory cell blocks.

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

According to one redundant memory cell block selecting fuse circuit block, a plurality of defective normal memory cell blocks are replaced by a part or all of the redundant memory cell blocks, and a plurality of defective memory cell blocks are selected. The address signal from the redundant memory cell block selecting fuse circuit block, in which the fuse corresponding to the address of the normal memory cell block is blown, is input to the redundant decoder, whereby a plurality of defective normal memory cell blocks are replaced by a plurality of redundant memories. The configuration is such that a part or all of the cell block is substituted, and the address signal is a signal of the lowest address in the normal memory cell block selection address set in the redundant memory cell block selection fuse circuit block. Because I did Reduces the number of redundant memory cell block selection fuse circuit block, it is possible to suppress an increase in chip area while securing the alternate freedom.

Normally, when a defect that causes a defect does not fit in one normal memory cell block, the defect extends over two adjacent normal memory cell blocks, and therefore, two normal memory cell blocks are used. When it is necessary to replace a memory cell block with two redundant memory cell blocks, the two normal memory cell blocks are often adjacent to each other. Therefore, when the two normal memory cell blocks adjacent to each other are replaced by the two redundant memory cell blocks, the common part of the addresses of the two normal memory cell blocks is cut by cutting the common fuse. Since the lowest addresses that are different from each other are selected by cutting two fuses out of the plurality of fuses corresponding to the lowest addresses,
By replacing two normal memory cell blocks with two redundant memory cell blocks in one redundant memory cell block selecting fuse circuit block, the number of redundant memory cell block selecting fuse circuit blocks is reduced, and substitution is free. It is possible to suppress the increase of the chip area while ensuring the degree.

To each of the plurality of normal memory cell blocks, a combination of a plurality of addresses is assigned to each normal memory cell block, and the arrangement form of the assigned address combinations is assigned to one normal memory cell block. And a combination of addresses assigned to other normal memory cell blocks adjacent to each other for one normal memory cell block is one of a plurality of addresses forming each address combination. Since the arrangement is such that the address combinations are arranged so that only the addresses are always different from each other, any combination of the addresses of the two normal memory cell blocks adjacent to each other can be selected arbitrarily. Even if multiple addresses that make up a combination of addresses are All but one of the scan will be the same, different from the only one either. as a result,
It is always possible to substitute two redundant normal memory cell blocks adjacent to each other with two redundant memory cell blocks by one redundant memory cell block selecting fuse circuit block.

A redundant decoder selection signal determined according to a combination of addresses assigned to the normal memory cell blocks is input to the redundant decoder, so that a plurality of defective normal memory cell blocks are replaced with a plurality of redundant memory cells. Since some or all of the blocks are replaced, the number of redundant memory cell block selecting fuse circuit blocks can be reduced, and the increase in chip area can be suppressed while ensuring the degree of replacement.

In the case of replacing two normal memory cell blocks of one normal memory cell block and another normal memory cell block adjacent to the one normal memory cell block with two redundant memory cell blocks. Of the addresses of one normal memory cell block and the addresses of other normal memory cell blocks, the common part of the addresses is selected by cutting the common fuse of the fuse circuit block for selecting one redundant memory cell block, For different addresses, two normal memory cell blocks are replaced by two redundant memory cell blocks by cutting and selecting two fuses from a plurality of fuses corresponding to different addresses. Redundant memory cell block selection fuse circuit block By replacing each memory cell block with two redundant memory cell blocks, it is possible to reduce the number of redundant memory cell block selecting fuse circuit blocks, and to suppress the increase in chip area while ensuring the degree of substitution. .

Since the number of redundant memory cell block selecting fuse circuit blocks is set to be as small as possible than the number of redundant memory cell blocks, the number of redundant memory cell block selecting fuse circuit blocks is reduced and replaced. An increase in the chip area can be suppressed while ensuring the degree of freedom.

[0056]

[0057]

[0058]

[0059]

[0060]

[0061]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device adopting an alternative method of defective memory cells according to a first embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3 and 4.

FIG. 1 is a block diagram of a semiconductor memory device according to the first embodiment.

At the top of the block diagram of FIG.
A plurality of normal memory cell blocks NCB00 to NCB
0n and two redundant memory cell blocks SCB00, SC
A memory cell array MCA0 having B01 and B01 is shown.

One end of each of the normal word lines WL00 to 03 is connected to the normal memory cell block NCB00, and the other end of each of the normal word lines WL00 to 03 is connected to the normal decoder NDEC00. Other normal memory cell blocks NCB01-N
CB0n and other normal decoders NDEC01 to 0n are also connected by normal word lines (not shown in the figure).

In each normal decoder NDEC00-0n, the address signals XA0-3, XB0-3 corresponding to the address of the normal memory cell block to which the normal decoders NDEC00-NDEC0n are connected by the normal word lines WL00-03 ,. Any one of XC0 to XC3 is input, and further, the word line drive signals WDRV00 to 03 from the normal decoder control circuit NDC10 are input.

Normal decoder control circuit NDC
The redundancy instruction signal RSP00 from the redundancy memory cell block selection fuse circuit block FB00 and the memory cell array selection signal RSL0 are input to the memory cell 10.

Two redundant memory cell blocks SCB0
0, SCB01 have redundant word lines SWL00-03, S
One end of each of WL04 to 07 is connected, and the other ends of the redundant word lines SWL00 to 03 and SWL04 to 07 are connected to the redundant decoders SDEC100 and 101, respectively.

The redundancy decoder SDEC100 has word line drive signals WDRV0 to WDRV3 and address signals XA0 and XA.
A2, the redundancy instruction signal RSP00 from the redundancy memory cell block selection fuse circuit block FB00, and the memory cell array selection signal RSL0 are input.

The redundancy decoder SDEC101 has word line drive signals WDRV0 to WDRV3 and address signals XA1 and XA.
A3, the redundancy instruction signal RSP00 from the redundancy memory cell block selection fuse circuit block FB00, and the memory cell array selection signal RSL0 are input.

The connection relation of the uppermost stage portion of the block diagram has been described above, but each stage has the same connection relation.

Fuse circuit blocks FB00, FB10, FB2 for selecting redundant memory cell blocks in FIG.
0 and FB30 have the same configuration as the redundant memory cell block selecting fuse circuit block according to the conventional example shown in FIG.

The redundant memory cell block selecting fuse circuit block includes a P-type M controlled by a signal PRCH.
OS transistor QP0 and address signals XA0-3
N-type MOS transistors QN0 to 11 controlled by XB0 to 3 and XC0 to 3 are provided.
A P-type MOS transistor QP1 controlled by a signal from the P-type MOS transistor QP0 and a signal from each of the N-type MOS transistors QN0 to 11 via the fuses FU0 to 11 and an inverter is provided. Therefore, the P-type MOS transistors QP0,1
And signals from the N-type MOS transistors QN0 to QN11 control the redundancy instructing signal RSP00 which is an output signal of the redundancy memory cell block selecting fuse circuit block.

FIG. 2 is a circuit diagram of the first redundant decoder SDEC100 shown in FIG.
The EC 110, SDEC 120, and SDEC 130 have the same configuration as the redundant decoder SDEC 100.

The first redundancy decoder SDEC100 has a signal through the OR gates of the address signals XA0 and XA2, a redundancy designating signal RSP00, and a memory cell array selection signal R.
The signal from the NAND gate to which SL0 is input is the signal that has passed through the inverter. The input signals are N-type MOS transistors QN48, 51, 54, 5
N-type MOS transistor QN49,
52, 55, 58, and also controls N-type MOS transistors QN50, 53, 56, 59 via an inverter. Word line drive signal WDRV0, 1, 2, 3
Are N-type MOS transistors QN49 and QN5, respectively.
0, QN52 and QN53, QN55 and QN56, QN5
8 and QN59, the redundant word line SWL00,
It controls SWL01, SWL02, and SWL03.

FIG. 3 is a circuit configuration diagram of the second redundant decoder SDEC101 in FIG.
The EC111, SDEC121, and SDEC131 have the same configuration as the redundant decoder SDEC101.

The second redundancy decoder SDEC101 has a signal through the OR gates of the address signals XA1 and XA3, a redundancy designating signal RSP00, and a memory cell array selection signal R.
The signal from the NAND gate to which SL0 is input is the signal that has passed through the inverter. The input signals are N-type MOS transistors QN60, 63, 66, 6
N type MOS transistor QN61,
64, 67, 70, and also controls N-type MOS transistors QN62, 65, 68, 71 via inverters. Word line drive signal WDRV0, 1, 2, 3
Are N-type MOS transistors QN61 and QN6, respectively.
2, QN64 and QN65, QN67 and QN68, QN7
0 and the control of QN71, the redundant word line SWL04,
It controls SWL05, SWL06, and SWL07.

FIG. 4 is a circuit diagram of the normal decoder control circuit NDC10 shown in FIG. 1. The normal decoder control circuits NDC11 to NDC13 have the same structure as the normal decoder control circuit NDC10.

In the normal decoder control circuit,
A signal of the redundancy instruction signal RSP00 through the inverter,
NA to which the memory cell array selection signal RSL0 is input
The signal from the ND gate receives the signal from the inverter as an input signal. The input signal is transmitted through N-type MOS transistors QN72, 75, 78 and 81 to N-type MO.
Controlling the S-transistors QN73, 76, 79, 82,
In addition, the N-type MOS transistor QN
74, 77, 80, 83 are controlled. The word line drive signals WDRV0, 1, 2, 3 are supplied to N-type MOS transistors QN73 and QN74, QN76 and QN77, QN, respectively.
The normal word line drive signals WDRV00, 01, 02, 0 are controlled through 79 and QN80 and QN82 and QN83.
Control 3

Normal decoder NDEC0 in FIG.
0-NDEC0n, NDEC10-NDEC1n, ND
EC20 to NDEC2n, NDEC30 to NDEC3n
Has the same configuration as the normal decoder according to the conventional example shown in FIG.

The normal decoder has the address signal XA
The signals from the NAND gate to which 0, XB0, and XC0 are respectively input are the signals passed through the inverter. The input signal is an N-type MOS transistor QN3
The N-type MOS transistors QN37, 40, 43 and 46 are controlled via 6, 39, 42 and 45, respectively, and
N-type MOS transistor QN38 via an inverter,
41, 44, 47 are controlled. The normal word line drive signals WDRV00, 01, 02 and 03 are N-type M
OS transistors QN37 and QN38, QN40 and QN
41, QN43 and QN44, QN46 and QN47, and the normal word lines WL00, 01, 02, 03.
To control.

In FIG. 1, FIG. 2, FIG. 3 and FIG.
CA0 is a memory cell array having normal memory cell blocks NCB00 to NCB0n and redundant memory cell blocks SCB00 and SCB01, and MCA1 to MCA3.
Is another memory cell array having the same structure as the memory cell array MCA0, and is FB00, FB10, F
B20 and FB30 are redundant memory cell block selecting fuse circuit blocks, SDEC100, SDEC101,
SDEC110, SDEC111, ..., SDEC131
Is a redundant decoder, NDEC00 to NDEC0n, NDE
C10-NDEC1n, NDEC20-NDEC2n,
NDEC30 to NDEC3n are normal decoders, ND
C10, NDC11, NDC12, NDC13 are normal decoder control circuits, XA0-3, XB0-
3, XC0 to 3 are address signals, RSL0 to RSL3 are memory cell array selection signals, WDRV0 to WDRV3 are word line drive signals, WDRV00 to WDRV03, WD
RV10 to WDRV13, WDRV20 to WDRV2
3, WDRV30 to WDRV33 are normal word line drive signals, WL00, WL01, WL02, WL03, ...
Is a normal word line, SWL00, SWL01, SWL
02, SWL03, SWL04, SWL05, SWL0
6, SWL07 is a redundant word line, RSP00, RSP1
0, RSP20, RSP30 are redundancy instruction signals, PRCH
Is a signal, VCC is a power supply voltage, VSS is a ground voltage, QN4
8 to QN83 are N-type MOS transistors.

Generally, when a defect causing a defect does not fit in one normal memory cell block, the defect extends to two adjacent normal memory cell blocks. Therefore, when it is necessary to substitute two redundant memory cell blocks for two normal memory cell blocks, these two normal memory cell blocks are often adjacent to each other.

As described above, in the first embodiment, defective memory cells are respectively assigned to two adjacent normal memory cell blocks selected by addresses having the same XC and XB but different XA in the address combinations. If included, the two normal memory cell blocks are replaced by two redundant memory cell blocks, and if there is one normal memory cell block including a defective memory cell, the one normal memory cell block Is replaced by any one redundant memory cell block of the two redundant memory cell blocks.

In the first embodiment, the configuration of the memory cell array is the same as that of FIG. 12, and each memory cell array has a plurality of normal memory cell blocks each having four normal word lines and one normal memory cell block. Two redundant memory cell blocks each having four redundant word lines are provided. However, the redundant memory cell block selecting fuse circuit block for selecting those redundant memory cell blocks is one, and the configuration for inputting an address signal to the redundant decoder is different from the conventional configuration shown in FIG. Is different.

For example, for the memory cell array MCA0, normal memory cell blocks NCB00 to NCB0
n and two redundant memory cell blocks SCB00, SC
The provision of B01 is the same as in the conventional example, but the redundant memory cell block selecting fuse circuit block is FB00.
Of the redundant decoder SDEC1 and the addresses XA0 and XA2 are stored in the redundant decoder SDEC1.
Addresses XA1 and XA3 are input to 01, respectively.

Further, as in the conventional example, one normal decoder provided for each normal memory cell block is connected to each normal memory cell block.
One redundant word line is controlled, and one redundant decoder is provided for each redundant memory cell block to control four redundant word lines connected to each redundant memory cell block. Word line drive signals WDRV0 to WDRV
3 is partially decoded by the least significant bit A0R of the row address and the most significant bit A1R of the row address A0R, A1R.
One is selected by each logic voltage and has a predetermined word line potential. The address signals XA0-3 are partially decoded by their upper bits A2R, A3R, the address signals XB0-3 are further decoded by their upper bits A4R, A5R, and the address signals XC0-3 are further decoded by their upper bits A6R, A7R. Constitute. A memory cell array selection signal RSL is used to select the memory cell array.
0 to RSL3. The selection of the normal memory cell block in one memory cell array is performed by selecting the normal decoder by the address signals XA0-3, XB0-3 and XC0-3. The normal word line selection in the selected memory cell block is
The normal word line drive signals WDRV0 to WDRV0 are connected to the respective normal decoders via the normal decoder control circuit.
0-WDRV03, WDRV10-WDRV13, WD
RV20 to WDRV23, WDRV30 to WDRV33
Done by.

In the configuration of the first embodiment of the present invention as described above, for example, one normal memory cell block including a defective memory cell exists in the normal memory cell blocks provided in the memory cell array MCA0, When it is desired to replace it with either of the redundant memory cell blocks SCB00 and SCB01, the fuse corresponding to the address of the block including the defective memory cell in the redundant memory cell block selecting fuse circuit block FB00 is broken, and thus the defective memory cell is defective. The block including the memory cell is replaced with the redundant memory cell block, and the redundant memory cell block is used. In this case, the alternative destination is selected by the address of XA in the combination of the addresses of the block including the defective memory cell, which is XA0 or XA.
If A2, the redundant memory cell block SCB00 is X
If A1 or XA3, redundant memory cell block SC
B01 is used. At this time, the fuse blown in the redundant memory cell block selecting fuse circuit block FB00 is one of the four fuses corresponding to the address signals XA0-3 and one of the four fuses corresponding to XB0-3.
This is a total of three, one out of four corresponding to XC0 to XC3.

Further, two adjacent normal memory cell blocks selected by a combination of addresses having the same addresses XC and XB but different only in XA include defective memory cells, and two redundant memory cell blocks SCB are included.
00 and SCB01 are used, in the redundant memory cell block selecting fuse circuit block FB00, the fuses corresponding to the respective addresses of the two blocks including the defective memory cell are cut off, thereby The two blocks including the above are replaced by redundant memory cell blocks SCB00 and SCB01, respectively. At this time, since the fuses to be blown in the redundant memory cell block selecting fuse circuit block FB00 have the same combination of two addresses, XC and XB are the same and only XA is different, the address signal XC0
1 to 4 for XB0-3, 1 for 4 for XB0-3, and 2 for 4 for XA0-3.

The detailed circuit operation of the semiconductor memory device adopting the alternative method of the defective memory cell according to the first embodiment will be described below with reference to FIGS. 1, 2, 3, 4, and 13. .

Here, the memory cell array is MCA0 to MCA.
It is assumed that MCA0 of CA3 is selected. First, in the redundant memory cell block selecting fuse circuit block FB00 shown in FIG. 13, the signal PRCH is "L", the P-type MOS transistor QP0 is turned on, and all the address signals XA0-3, XB0-3, and XC0-3. At "L", the N-type MOS transistors QN0 to QN11 are off, and the redundancy instruction signal RSP00 is "H". In addition, all memory cell array selection signals RSL0
~ RSL3 is "L", all word line drive signals WDR
V0 to WDRV3 are "L", and therefore redundant decoders SDEC100, shown in FIGS. 2 and 3, respectively.
In SDEC 101, redundant word lines SWL00 to SWL
WL03 and redundant word lines SWL04 to SWL07 are "L".

First, the signal PRCH becomes "H" and the P-type M
The OS transistor QP0 is turned off. Then, the memory cell array selection signal RSL which was initially "L"
Of 0 to RSL3, RSL0 becomes "H". Further, at the beginning, one of the address signals XA0 to XA3, which is all "L", one of XB0 to 3 and one of XC0 to 3 becomes "H" and is selected. When the address of the memory cell block changes, twelve N-type MOS transistors QN0 to QN0-Q corresponding to the change of the address signal.
Three of N11 are turned on.

At this time, the combination of the addresses which have become "H" is not the address of the block including the defective memory cell in the memory cell array MCA0, and
Redundant memory cell block selecting fuse circuit block FB00 provided corresponding to the memory cell array MCA0
If the combination of the addresses corresponding to the blown fuses does not match, the redundancy instruction signal RSP00 becomes "L". Therefore, even if the memory cell array selection signal RSL0 becomes "H" in either of the redundant decoders SDEC100 and SDEC101 shown in FIGS. 2 and 3, the N-type MOS transistors QN49, QN52,
QN55, QN58, QN61, QN64, QN67,
QN70 is off and N-type MOS transistor QN5
0, QN53, QN56, QN59, QN62, QN6
Since 5, QN68 and QN71 are on, all the redundant word lines SWL00 to SWL07 are "L" even if any one of the word line drive signals WDRV0 to WDRV3 has a predetermined word line potential. It remains.
That is, the redundant memory cell blocks SCB00, SCB
Neither 01 is selected.

However, the combination of the above "H" addresses is the address of the block including the defective memory cell in the memory cell array MCA0, and the redundant memory cell block selecting fuse circuit block FB00.
When all the fuses corresponding to the address are blown in, the redundancy instructing signal RSP00 remains "H". At this time, the address of XA is XA0 or XA2 among the combinations of the above-mentioned "H" addresses.
In the redundant decoder SDEC100 shown in FIG. 2, when the memory cell array selection signal RSL0 becomes "H", the N-type MOS transistors QN49, QN52, QN.
55 and QN58 are on, N-type MOS transistors QN50, QN53, QN56 and QN59 are off, and any one of the word line drive signals WDRV0 to WDRV3 has a predetermined word line potential. The potential is transferred to the corresponding redundant word line. That is, the redundant memory cell block SCB00 is selected.

If the address of XA is XA1 or XA3 among the combinations of the above-mentioned "H" addresses and the memory cell array selection signal RSL0 becomes "H" in the redundant decoder SDEC101 shown in FIG. Type MOS transistors QN61, QN64, QN
67 and QN70 are turned on, and N-type MOS transistors QN62, QN65, QN68 and QN71 are turned off. Therefore, the word line drive signals WDRV0 to WDR
When a selected arbitrary one of V3 reaches a predetermined word line potential, that potential is transferred to the corresponding redundant word line. That is, the redundant memory cell block SCB01
Is selected.

As described above, when all the fuses corresponding to the address which has become "H" in the redundant memory cell block selecting fuse circuit block FB00 are blown, the redundancy instructing signal RSP00 is "H".
Normal decoder control circuit NDC1 shown in FIG.
0, the memory cell array selection signal RSL0 is "H"
Even if it becomes, N-type MOS transistors QN73, QN7
6, QN79, QN82 are off, and N-type MOS transistors QN74, QN77, QN80, QN83 are on. Therefore, the word line drive signals WDRV0-
All the normal word line drive signals WDRV00 to WDRV03 remain "L" even if any one selected from the WDRV3 has a predetermined word line potential, and all the normal memory cells of the memory cell array MCA0. The blocks NCB00 to NCB0n are unselected.
As a result, the normal memory cell block selected by the combination of the above-mentioned "H" addresses is replaced with the redundant memory cell block selected by the address of XA in the combination of the addresses.

A semiconductor memory device adopting the alternative method of the defective memory cell according to the second embodiment of the present invention will be described below with reference to FIGS. 5, 6, 7, 8 and 9.

FIG. 5 is a block diagram of a semiconductor memory device according to the second embodiment.

The uppermost part of the block diagram of FIG.
A plurality of normal memory cell blocks NCB00 to NCB
0n and two redundant memory cell blocks SCB00, SC
A memory cell array MCA0 having B01 and B01 is shown.

One end of each of the normal word lines WL00-03 is connected to the normal memory cell block NCB00, and the other end of each of the normal word lines WL00-03 is connected to the normal decoder NDEC00. Other normal memory cell blocks NCB01-N
CB0n and other normal decoders NDEC01 to 0n are also connected by normal word lines (not shown in the figure).

In each normal decoder NDEC00-0n, the address signals XA0-3, XB0-3 corresponding to the address of the normal memory cell block to which the normal decoders NDEC00-NDEC0n are connected by the normal word lines WL00-03 ,. Any one of XC0 to XC3 is input, and further word line drive signals WDRV00 to 03 from the normal decoder control circuit NDC10 are input.

Normal decoder control circuit NDC
The redundancy instruction signal RSP00 from the redundancy memory cell block selection fuse circuit block FB00 and the memory cell array selection signal RSL0 are input to the memory cell 10.

Two redundant memory cell blocks SCB0
0, SCB01 have redundant word lines SWL00-03, S
One ends of WL04 to 07 are connected to each other, and the other ends of the redundant word lines SWL00 to 03 and SWL04 to 07 are connected to the redundant decoders SDEC300 and 301, respectively.

The redundant decoder SDEC300 has word line drive signals WDRV0 to WDRV3 and a redundant decoder selection signal S.
RSL0, the redundancy instruction signal RSP00 from the redundancy memory cell block selecting fuse circuit block FB00,
The memory cell array selection signal RSL0 is input.

The redundancy decoder SDEC301 has word line drive signals WDRV0 to WDRV3 and a redundancy decoder selection signal S.
RSL1, a redundancy instruction signal RSP00 from the redundancy memory cell block selecting fuse circuit block FB00,
The memory cell array selection signal RSL0 is input.

The connection relation of the uppermost stage portion of the block diagram has been described above, but each stage has the same connection relation.

Fuse circuit blocks FB00, FB10, FB2 for redundant memory cell block selection in FIG.
0 and FB30 have the same configuration as the redundant memory cell block selecting fuse circuit block according to the conventional example shown in FIG.

FIG. 6 is a circuit configuration diagram of the first redundant decoder SDEC300 in FIG.
The EC 310, SDEC 320, and SDEC 330 have the same configuration as the redundant decoder SDEC 300.

The first redundancy decoder SDEC300 has a redundancy decoder selection signal SRSL0 and a redundancy designating signal RSP.
00 and a signal from the NAND gate to which the memory cell array selection signal RSL0 is input are input through the inverter. The input signal is transmitted via N-type MOS transistors QN102, 105, 108 and 111 to N-type MOS transistors QN103, 106 and 106, respectively.
Controls 109 and 112, and N
Type MOS transistors QN104, 107, 110, 1
Control 13. Word line drive signal WDRV0,1,
2 and 3 are N-type MOS transistors QN103, respectively.
And QN104, QN106 and QN107, QN109 and QN110, QN112 and QN113, and redundant word lines SWL00, SWL01, SWL02, SW.
Control L03.

FIG. 7 is a circuit configuration diagram of the second redundant decoder SDEC301 in FIG.
The EC 311, SDEC 321, and SDEC 331 have the same configuration as the redundant decoder SDEC 301.

The second redundant decoder SDEC301 includes a redundant decoder selection signal SRSL1 and a redundancy instruction signal RSP.
00 and a signal from the NAND gate to which the memory cell array selection signal RSL0 is input are input through the inverter. The input signal is transmitted through N-type MOS transistors QN114, 117, 120 and 123 to N-type MOS transistors QN115, 118 and 118, respectively.
121 and 124 are controlled, and N is supplied via an inverter.
Type MOS transistors QN116, 119, 122, 1
Control 25. Word line drive signal WDRV0,1,
2 and 3 are N-type MOS transistors QN115, respectively.
And QN116, QN118 and QN119, QN121 and QN122, QN124 and QN125, and redundant word lines SWL04, SWL05, SWL06, SW.
Control L07.

Normal decoder control circuits NDC10 to NDC13 in FIG. 5 have the same structure as the normal decoder control circuit according to the first embodiment shown in FIG.

Normal decoder NDEC0 in FIG.
0-NDEC0n, NDEC10-NDEC1n, ND
EC20 to NDEC2n, NDEC30 to NDEC3n
Has the same configuration as the normal decoder according to the conventional example shown in FIG.

In FIGS. 5, 6 and 7, MCA0
Is a memory cell array, and includes normal memory cell blocks NCB00 to NCB0n and redundant memory cell block SC
BCA and SCB01, and MCA1 to MCA3 are other memory cell arrays having the same structure as the memory cell array MCA0. FB00, FB10, FB2
0, FB30 are redundant memory cell block selection fuse circuit blocks, SDEC300, SDEC301, SD
EC310, SDEC311, ..., SDEC331 are redundant decoders, NDEC00 to NDEC0n, NDEC1.
0-NDEC1n, NDEC20-NDEC2n, ND
EC30 to NDEC3n are normal decoders, NDC1
0, NDC11, NDC12, NDC13 are normal decoder control circuits, XA0-3, XB0-3, X
C0 to 3 are address signals, RSL0 to RSL3 are memory cell array selection signals, SRSL0 and SRSL1 are redundant decoder selection signals, WDRV0 to WDRV3 are word line drive signals, WDRV00 to WDRV03, WDRV10.
WDRV13, WDRV20 to WDRV23, WDRV
30 to WDRV33 are normal word line drive signals, WL
00, WL01, WL02, WL03, ... Are normal word lines, SWL00, SWL01, SWL02, SWL
03, SWL04, SWL05, SWL06, SWL0
7 is a redundant word line, RSP00, RSP10, RSP2
0, RSP30 is a redundancy instruction signal, PRCH is a signal, VC
C is the power supply voltage, VSS is the ground voltage, QN102 to QN1
Reference numeral 25 is an N-type MOS transistor.

As described above, according to the first embodiment, one address and the other address of two normal memory cell blocks, one of which is adjacent to the other, are X-addressed.
C and XB are the same, and two normal memory cell blocks that are adjacent to each other and are selected by an address that is a combination of which only the lowest address XA is different are set to the same address XC in one redundant memory cell block selecting fuse circuit block. And, two fuses commonly corresponding to XB and XB and two fuses corresponding to different addresses XA, respectively, are cut, so that a total of four fuses can be replaced with two redundant memory cell blocks.

On the other hand, in the configuration of the second embodiment, two adjacent addresses selected by an address in which one address and the other address have the same XC and XB but different only the lowest address XA. Not only the normal memory cell block but also two normal memory cell blocks adjacent to each other can be replaced by two redundant memory cell blocks by one redundant memory cell block selecting fuse circuit block. Is.

When there is only one normal memory cell block including a defective memory cell, the one normal memory cell block is replaced with any one of the two redundant memory cell blocks. Since this is the same as that of the first embodiment, hereinafter, in the configuration of the second embodiment, any two adjacent normal memory cell blocks are replaced by one redundant memory cell block selecting fuse circuit. A case in which two redundant memory cell blocks are replaced by blocks will be described.

In the second embodiment, the structure of the memory cell array is the same as that of the memory cell array according to the first embodiment shown in FIG.
A plurality of normal memory cell blocks each having four normal word lines and two redundant memory cell blocks each having four redundant word lines are provided. However, the input of the redundant decoder selection signal to the redundant decoder and the combination of one address and the other address of any two adjacent normal memory cell blocks are always two of XC, XB, and XA. The configuration in which the addresses assigned to the normal memory cell blocks are arranged so that they are the same and only one is different from the configuration of the first embodiment shown in FIG.

Regarding the structure of the memory cell array,
In the same manner as in the first embodiment, for example, in the memory cell array MCA0, the normal memory cell blocks NCB00 to NCB0 are included.
n and two redundant memory cell blocks SCB00, SC
It is equipped with B01. Also, as in the first embodiment and the conventional example, a normal decoder provided for each normal memory cell block controls four normal word lines connected to each normal memory cell block. A redundant decoder provided for each redundant memory cell block controls four redundant word lines connected to each redundant memory cell block. The word line drive signals WDRV0 to WDRV3 are partially decoded by the least significant bit A0R of the row address and the most significant bit A1R immediately after that, and set to 1 by the logical voltage of each of A0R and A1R.
A book is selected and has a predetermined word line potential. The address signals XA0-3 are based on their upper bits A2R and A3R, and the address signals XB0-3 are further higher bits A4R and A4R.
The address signal XC0-3 is further partially decoded by the higher bits A6R and A7R by the A5R. The memory cell array is selected by the memory cell array selection signals RSL0 to RSL3. The selection of the normal memory cell block in one memory cell array is performed by selecting the address signals XA0 to XA3 and XB0 to XB0.
This is performed by selecting the normal decoder with XC0-3. The normal word line in the selected memory cell block is selected by the word line drive signal WDRV.
0 to WDRV3 are connected to respective normal decoders via the normal decoder control circuit. Normal word line drive signals WDRV00 to WDRV03, WDR
V10 to WDRV13, WDRV20 to WDRV23,
It is performed by WDRV30 to WDRV33.

The above is the same as that of the first embodiment, but in the second embodiment, the redundant decoder selection signal SRSL0 is sent to the redundant decoder SDEC300.
The redundant decoder selection signal SRSL1 is input to each DEC301. Redundant decoder selection signal SRSL
One of 0 and SRSL1 becomes "H" according to the address of the normal memory cell block, and the normal memory cell blocks NCB00, NCB02, NCB04, NCB06, 6 arranged in the memory cell array are arranged.
When the address signal of ... Is input, SRSL0
Normal memory cell blocks NCB01, NCB03,
When the address signals of NCB05, NCB07, ... Are inputted, SRSL1 becomes "H".

Further, the arrangement of the addresses assigned to the normal memory cell block is characteristic of the second embodiment, which is different from the configuration of the first embodiment.

FIG. 8 is an explanatory view schematically showing the arrangement of addresses assigned to normal memory cell blocks in the semiconductor memory device according to the second embodiment, and FIG. 9 is for comparison with FIG. FIG. 3 is an explanatory diagram schematically showing an arrangement of addresses assigned to normal memory cell blocks in the first embodiment or the conventional semiconductor memory device.

Hereinafter, in the configuration of the second embodiment, two redundant normal memory cell blocks adjacent to each other are replaced with two redundant memory cell blocks by one redundant memory cell block selecting fuse circuit block. The possible arrangement of addresses assigned to the normal memory cell block will be described.

In the first embodiment of FIG. 9 or the conventional address arrangement mode, the allocated addresses are arranged such that all the addresses XC, XB and XA are 0, 1, It is repeatedly arranged as 2, 3, 0, 1, 2, 3, .... Therefore, two adjacent two
The combination of the addresses of the normal memory cell blocks is, for example, the combination of (XC0, XB0, XA2) and (XC0, XB0, XA3). Other than different, (X
C0, XB0, XA3) and (XC0, XB1, XA0)
Only XC is the same as the combination with and 2 of XB and XA
If the two are different, (XC0, XB3, XA3) and (XC0
1, XB0, XA0) and XC, XB,
There are three cases where all of the XAs are different. In the configuration of the first embodiment, the two normal memory cell blocks adjacent to each other can be replaced with the two redundant memory cell blocks by the one redundant memory cell block selecting fuse circuit block. Of the three combinations of addresses of the two normal memory cell blocks, two combinations of XC and XB are the same, and only when XA is different. Substitution is not possible in the case of a street.

On the other hand, in the address arrangement form of the second embodiment of FIG. 8, the allocation of the assigned addresses is the same as in FIG. 8 for all addresses XC, XB, and XA.
From the left side of the sequence, next to the arrangement of 0, 1, 2, 3 is 3, 2,
They are arranged as 1, 0, and next to the arrangement of 3, 2, 1, 0, they are arranged as 0, 1, 2, 3, and they are arranged sequentially according to this rule. Therefore, the combination of addresses of two normal memory cell blocks adjacent to each other is
No matter which combination you choose, XC, XB,
Two of the XAs are the same, and only one of them is different.

As a result, in the structure of the second embodiment, two normal memory cell blocks adjacent to each other are always replaced by two redundant memory cells by one redundant memory cell block selecting fuse circuit block. It is possible to substitute a cell block.

In the configuration of the second embodiment of the present invention as described above, for example, one normal memory cell block including a defective memory cell exists in the normal memory cell blocks provided in the memory cell array MCA0, When it is desired to replace it with either of the redundant memory cell blocks SCB00 and SCB01, the fuse corresponding to the address of the block including the defective memory cell in the redundant memory cell block selecting fuse circuit block FB00 is broken, and thus the defective memory cell is defective. The block including the memory cell is replaced with the redundant memory cell block, and the redundant memory cell block is used. At this time, the alternative destination is selected by the redundant decoder selection signal determined by the combination of the addresses of the block including the defective memory cell, and SR
If LS0 is "H", redundant memory cell block SCB
If 00 is SRLS1 "H", the redundant memory cell block SCB01 is used. At this time, the fuse blown in the redundant memory cell block selecting fuse circuit block FB00 is one of four fuses corresponding to the address signals XA0-3, one of four fuses corresponding to XB0-3, and XC0. 1 out of 4 corresponding to 3 to 3 in total.

In addition, two of which one and the other are adjacent to each other
Defective memory cells are included in each of the normal memory cell blocks, and two redundant memory cell blocks SCB0
In the case of using 0 and SCB01 for replacement, in the redundant memory cell block selecting fuse circuit block FB00, the fuses corresponding to the respective addresses of the two blocks including the defective memory cell are blown to cut those fuses. Two blocks including defective memory cells are redundant memory cell blocks SCB00 and SCB01, respectively.
Is replaced by. At this time, the fuses to be blown in the redundant memory cell block selecting fuse circuit block FB00 must have a combination of two addresses XC, XB,
Two of the XAs are the same and only one of them is different. Therefore, the fuse corresponding to the same address is one fuse out of four, and the fuses corresponding to different addresses from each other. Is a total of four out of four.

The detailed circuit operation of the semiconductor memory device adopting the alternative method of the defective memory cell according to the second embodiment will be described below with reference to FIGS. 5, 6, 7, 4, and 13. .

Here, the memory cell array is MCA0 to MCA.
It is assumed that MCA0 of CA3 is selected. First, in the redundant memory cell block selecting fuse circuit block FB00 shown in FIG. 13, the signal PRCH is "L", the P-type MOS transistor QP0 is turned on, and all the address signals XA0-3, XB0-3, and XC0-3. At "L", the N-type MOS transistors QN0 to QN11 are off, and the redundancy instruction signal RSP00 is "H". In addition, all memory cell array selection signals RSL0
~ RSL3 is "L", all word line drive signals WDR
V0 to WDRV3 are "L", and therefore redundant decoders SDEC300, shown in FIGS. 6 and 7, respectively.
In SDEC301, redundant word lines SWL00 to SWL
WL03 and redundant word lines SWL04 to SWL07 are "L".

First, the signal PRCH becomes "H" and the P-type M
The OS transistor QP0 is turned off. Then, the memory cell array selection signal RSL which was initially "L"
Of 0 to RSL3, RSL0 becomes "H". Further, at the beginning, one of the address signals XA0 to XA3, which is all "L", one of XB0 to 3 and one of XC0 to 3 becomes "H" and is selected. When the address of the memory cell block changes, twelve N-type MOS transistors QN0 to QN0-Q corresponding to the change of the address signal.
Three of N11 are turned on.

At this time, the combination of the addresses set to "H" is not the address of the block including the defective memory cell in the memory cell array MCA0, and the redundant memory cell block provided corresponding to the memory cell array MCA0. When the combination of the addresses corresponding to the blown fuses in the selection fuse circuit block FB00 does not match, the redundancy instruction signal RSP00 becomes "L". Therefore, even if the memory cell array selection signal RSL0 becomes "H" in either of the redundant decoders SDEC300 and SDEC301 shown in FIGS. 6 and 7, the N-type MOS transistors QN103 and QN10
6, QN109, QN112, QN115, QN11
8, QN121, QN124 are off, N-type MOS
Transistors QN104, QN107, QN110, Q
N113, QN116, QN119, QN122, QN
Since 125 is on, the word line drive signal WDRV0
To WDRV3, even if any one selected one has a predetermined word line potential, all redundant word lines SWL00
-SWL07 remains "L". That is, none of the redundant memory cell blocks SCB00 and SCB01 are selected.

However, the combination of the above-mentioned "H" addresses is the address of the block including the defective memory cell in the memory cell array MCA0 and corresponds to the address in the redundant memory cell block selecting fuse circuit block FB00. When all the fuses are blown, the redundancy instruction signal RSP00 remains "H". At this time, the redundancy decoder selection signal SRSL0 is "H" due to the combination of the above-mentioned "H" addresses.
And the redundant decoder SDEC300 shown in FIG.
When the memory cell array selection signal RSL0 becomes "H" at, the N-type MOS transistors QN103, QN10
6, QN109, QN112 are on, N-type MOS
Transistors QN104, QN107, QN110, Q
N113 turns off, and the word line drive signal WDR
When a selected one of V0 to WDRV3 has a predetermined word line potential, the potential is transferred to the corresponding redundant word line. That is, the redundant memory cell block SCB00 is selected.

Further, the redundant decoder selection signal SRSL1 is set to "H" due to the combination of the above-mentioned "H" addresses.
And the redundant decoder SDEC301 shown in FIG.
When the memory cell array selection signal RSL0 becomes "H" at, the N-type MOS transistors QN115, QN11
8, QN121, QN124 are turned on, and N-type MOS
Transistors QN116, QN119, QN122, Q
N125 is off. Therefore, when any one of the selected word line drive signals WDRV0 to WDRV3 has a predetermined word line potential, that potential is transferred to the corresponding redundant word line. That is, the redundant memory cell block SCB01 is selected.

When all the fuses corresponding to the address which has become "H" in the redundant memory cell block selecting fuse circuit block FB00 are blown, the redundancy instruction signal RSP00 is "H".
Normal decoder control circuit NDC1 shown in FIG.
0, the memory cell array selection signal RSL0 is "H"
Even if it becomes, N-type MOS transistors QN73, QN7
6, QN79, QN82 are off, and N-type MOS transistors QN74, QN77, QN80, QN83 are on. Therefore, the word line drive signals WDRV0-
All the normal word line drive signals WDRV00 to WDRV03 remain "L" even if any one selected from the WDRV3 has a predetermined word line potential, and all the normal memory cell drive signals WDRV00 to WDRV03 remain unchanged. The locks NCB00 to NCB0n are not selected.
As a result, the normal memory cell block selected by the combination of the above-mentioned "H" addresses is replaced by the redundant memory cell block selected by the redundant decoder selection signal determined according to the combination of the addresses. Will be done.

A semiconductor memory device adopting an alternative method of defective memory cells according to the third embodiment of the present invention will be described below with reference to FIGS.

FIG. 10 is a block diagram of a semiconductor memory device according to the third embodiment.

In the uppermost portion of the block diagram of FIG. 10, a plurality of normal memory cell blocks NCB00 to NCB are provided.
A memory cell array MCA20 having CB0n and one redundant memory cell block SCB00 is shown.

One end of the normal word lines WL00-03 is connected to the normal memory cell block NCB00, and the other end of the normal word lines WL00-03 is connected to the normal decoder NDEC00. Other normal memory cell blocks NCB01-N
CB0n and other normal decoders NDEC01 to 0n are also connected by normal word lines (not shown in the figure).

In each normal decoder NDEC00-0n, the address signals XA0-3, XB0-3 corresponding to the address of the normal memory cell block to which the normal decoders NDEC00-NDEC0n are connected by the normal word lines WL00-03 ,. Any one of XC0 to XC3 is input, and further, the word line drive signals WDRV00 to 03 from the normal decoder control circuit NDC10 are input.

Normal decoder control circuit NDC
Reference numeral 10 denotes a redundancy instruction signal RSP00 from the redundancy memory cell block selection fuse circuit block FB200,
The memory cell array selection signal RSL0 is input.

One end of each redundant word line SWL00-03 is connected to the redundant memory cell block SCB00, and the other end of each redundant word line SWL00-03 is connected to the redundant decoder SDEC00.

The word line drive signals WDRV0-3, the redundancy instruction signal RSP00 from the redundancy memory cell block selection fuse circuit block FB200, and the memory cell array selection signal RSL0 are input to the redundancy decoder SDEC00.

The connection relation of the uppermost stage portion of the block diagram has been described above, but each stage has the same connection relation.

FIG. 11 is a circuit configuration diagram of the redundant memory cell block selecting fuse circuit block FB200 in FIG. 10, and the redundant memory cell block selecting fuse circuit blocks FB210, FB220, FB230 are redundant memory cell block selecting fuse circuits. Block FB
It has the same configuration as 200.

In the redundant memory cell block selecting fuse circuit block FB200, the P-type MOS transistor QP2 controlled by the signal PRCH and the address signal /
N-type MOS transistor Q for controlling signals from N-type MOS transistors QN100, 101 controlled by A1R, A1R by address signals XA0-3, respectively.
N84-91, N-type MOS transistors QN92-95 controlled by address signals XB0-3, and N-type MOS transistors QN96-99 controlled by address signals XC0-3 are provided. A signal from the MOS transistor QP2 and each N-type M via the fuses FU12 to 27 and the inverter.
A P-type MOS transistor QP3 controlled by the signals from the OS transistors QN84 to 99 is provided. Therefore, the P-type MOS transistors QP2, 3
And a signal from the N-type MOS transistors QN84 to 99, the redundancy instruction signal RS which is an output signal of the redundancy memory cell block selecting fuse circuit block FB200.
P00 is controlled.

Redundant decoder SDEC0 in FIG.
0, SDEC10, SDEC20, SDEC30 are shown in FIG.
It has the same configuration as the redundant decoder according to the conventional example shown in FIG.

Redundant decoders SDEC00, 10, 20,
A signal from the NAND gate, to which the redundancy instruction signal RSP00 and the memory cell array selection signal RSL0 are input, is an input signal for the signal 30.
The input signals are N-type MOS transistors QN12, 15,
N-type MOS transistor Q via 18 and 21, respectively
N13, 16, 19, 22 are controlled, and N-type MOS transistors QN14, 17, 2 are controlled via an inverter.
0 and 23 are controlled. Word line drive signal WDRV0,
1, 2 and 3 are N-type MOS transistors QN1
3 and QN14, QN16 and QN17, QN19 and QN2
0, QN22 and QN23 are controlled, and the redundant word line S
It controls WL00, SWL01, SWL02, and SWL03.

Normal decoder control circuits NDC10 to NDC13 shown in FIG. 10 have the same structure as the normal decoder control circuit according to the first embodiment shown in FIG.

Normal decoder NDEC in FIG.
00 to NDEC0n, NDEC10 to NDEC1n, N
DEC20 to NDEC2n, NDEC30 to NDEC3
n has the same configuration as the normal decoder according to the conventional example shown in FIG.

In FIGS. 10 and 11, the memory cell array MCA20 is a normal memory cell block NCB.
00-NCB0n and redundant memory cell block SCB00
And MCA21 to MCA23 are other memory cell arrays having the same structure as the memory cell array MCA20. FB200, FB210, FB220, F
B230 is a fuse circuit block for selecting a redundant memory cell block, SDEC00, SDEC10, SDEC2
0, SDEC30 is a redundant decoder, NDEC00 to ND
EC0n, NDEC10 to NDEC1n, NDEC20
˜NDEC2n, NDEC30˜NDEC3n are normal decoders, NDC10, NDC11, NDC12, N
DC13 is a normal decoder control circuit, XA0
~ 3, XB0-3, XC0-3, / A1R, A1R are address signals, RSL0-RSL3 are memory cell array select signals, WDRV0-WDRV3 are word line drive signals,
WDRV00 to WDRV03, WDRV10 to WDRV
13, WDRV20 to WDRV23, WDRV30 to W
DRV33 is a normal word line drive signal, WL00, W
L01, WL02, WL03, ... Are normal word lines,
SWL00, SWL01, SWL02, SWL03 are redundant word lines, and RSP00, RSP10, RSP20, R.
SP30 is a redundancy instruction signal, PRCH is a signal, VCC is a power supply voltage, VSS is a ground voltage, and QP2 to QP3 are P-type MO.
S transistors, QN84 to QN101 are N-type MOS transistors.

In the third embodiment, when two normal memory cell blocks selected by an address having the same XC and XB but different XA among address combinations include a defective memory cell, the two normal memory cell blocks are selected. Of the four normal word lines connected to each of the memory cell blocks, the memory cell portion corresponding to a total of four normal word lines, two in total, is formed by one redundant memory cell block having four redundant word lines. It can be replaced.

In the third embodiment, each memory cell array is provided with a plurality of normal memory cell blocks each having four normal word lines, which is the same as the conventional example. Only one redundant memory cell block having four lines is provided, and the address signal / A1R, A1R is input to the redundant memory cell block selecting fuse circuit block for selecting the redundant memory cell block. And Fig. 12
Different from the conventional configuration shown in FIG. For example, in the memory cell array MCA20, the normal memory cell block NCB00
.About.NCB0n is the same as the conventional example, but only one redundant memory cell block SCB00 is provided and the redundant memory cell block selecting fuse circuit block FB is provided.
Address signals / A1R and A1R are input to 200. Further, one normal decoder provided for each normal memory cell block controls four normal word lines connected to each normal memory cell block, and one normal memory cell block is provided for each redundant memory cell block. One redundant decoder controls four redundant word lines connected to the redundant memory cell block.
The word line drive signals WDRV0 to WDRV3 are partially decoded by the least significant bit A0R of the row address and the immediately upper bit A1R thereof, and one of them is selected by a logical voltage of each of A0R and A1R to have a predetermined word line potential.
The address signals XA0-3 have upper bits A2R and A3.
By R, the address signals XB0-3 are further partially decoded by their upper bits A4R, A5R, and the address signals XC0-3 are further partially decoded by their higher bits A6R, A7R. The memory cell array is selected by the memory cell array selection signals RSL0 to RSL3. The selection of the normal memory cell block in one memory cell array is performed by address signals XA0 to XA0.
This is performed by selecting the normal decoder by 3, XB0 to 3, XC0 to 3. A normal word line is selected in the selected memory cell block by selecting the normal word line drive signals WDRV00 to WDRV in which the word line drive signals WDRV0 to WDRV3 are connected to the respective normal decoders via the normal decoder control circuit.
03, WDRV10 to WDRV13, WDRV20 to W
It is performed by the DRV 23 and WDRV30 to WDRV33.

In the configuration of the third embodiment of the present invention as described above, for example, two normal memories in the memory cell array MCA20, which are selected by a combination of addresses where XC and XB are the same and only XA is different. In the case where the redundant memory cell block SCB00 is used to replace the portion of the normal memory cells corresponding to a total of four normal word lines in each cell block with two normal word lines, the redundant memory cell block selecting fuse circuit block FB200 In, the fuses corresponding to the respective addresses of the two blocks including the defective memory cell are blown to be replaced by the redundant memory cell block, and the redundant memory cell block is used.

At this time, the fuses blown in the redundant memory cell block selecting fuse circuit block FB200 shown in FIG.
Since C and XB are the same and only XA is different, one of the four corresponding to the address signals XC0 to XC, X
One of the four corresponding to B0 to 3 and two of the eight corresponding to XA0 to 3 are four in total. The fuses corresponding to XA0 to 3 are cut by cutting A1R of the four normal word lines connected to the first normal memory cell block of the two normal memory cell blocks.
Of two normal word lines selected by "H", and the second
Of the four normal word lines connected to the normal memory cell block of / A1R when the two normal word lines selected by "H" are replaced together by the redundant memory cell block, the first on the A1R side Fuses corresponding to XA of the normal memory cell block and the second on the / A1R side
The fuse corresponding to XA of the normal memory cell block is cut.

Further, in the redundant memory cell block selecting fuse circuit block FB200, it is connected to the A1R side and / A side.
When the fuses corresponding to the same XA address on the 1R side are cut, one normal memory cell block controlled by one normal decoder is replaced with a redundant memory cell block as in the conventional case. .

The detailed circuit operation of the semiconductor memory device adopting the alternative method of the defective memory cell according to the third embodiment will be described below with reference to FIGS. 10, 11, 14 and 4.

Here, the memory cell array is MCA20-.
It is assumed that the MCA 20 of the MCAs 23 is selected. First, in the redundant memory cell block selecting fuse circuit block FB200 shown in FIG.
When the RCH is "L", the P-type MOS transistor QP2 is on, and the address signals A1R, / A1R, XA0-3, XB.
0 to 3 and XC0 to 3 are all "L", the N-type MOS transistors QN84 to QN101 are off, and the redundancy instruction signal RSP00 is "H". Further, all the memory cell array selection signals RSL0 to RSL3 are "L", all the word line drive signals WDRV0 to WDR.
V3 is "L", and therefore, in the redundant decoder SDEC00 shown in FIG. 14, the redundant word line SWL0
0 to SWL03 are "L".

First, the signal PRCH becomes "H" and the P-type M
The OS transistor QP2 is turned off. Then, one of / A1R and A1R of the address signal is "H".
And N-type MOS transistors QN100 and QN10
Either one of 1 is turned on. Further, the memory cell array selection signals RSL0 to RSL which were initially all “L”
RSL0 of SL3 becomes “H”. Further, at first, all of the address signals were "L". One of the address signals XA0-3, one of XB0-3, and one of XC0-3.
When the total of three books becomes "H" and the address of the memory cell block to be selected changes, four of the 16 N-type MOS transistors QN84 to QN99 are turned on.

At this time, the combination of the addresses that have become "H" is not the address of the word line including the defective memory cell in the memory cell array MCA20, but is blown in the redundant memory cell block selecting fuse circuit block FB200 in the memory cell array MCA20. If the combination of the addresses corresponding to the selected fuses does not match, the redundancy instruction signal RSP00 becomes "L", so that even if the memory cell array selection signal RSL0 becomes "H" in the redundancy decoder SDEC00 shown in FIG. N-type MOS transistors QN13, QN16, Q
N19 and QN22 are off, and N-type MOS transistors QN14, QN17, QN20 and QN23 are on. Therefore, the word line drive signals WDRV0 to WDR
All the redundant word lines SWL00 to SWL even if one selected one of V3 becomes a predetermined word line potential.
03 remains "L". That is, the redundant memory cell block SCB00 is not selected.

However, the combination of the above-mentioned "H" addresses is the address of the word line including the defective memory cell in the memory cell array MCA20, and the address in the redundant memory cell block selecting fuse circuit block FB200 is the address. When all the corresponding fuses are cut off, the redundancy instruction signal RSP00
Remains at "H", the memory cell array selection signal RSL in the redundant decoder SDEC00 shown in FIG.
When 0 becomes "H", the N-type MOS transistor QN1
3, QN16, QN19, QN22 are turned on, and N-type MOS transistors QN14, QN17, QN20, Q
N23 is turned off, and word line drive signals WDRV0-WDR
When a selected one of the DRV3 has a predetermined word line potential, that potential is transferred to the corresponding redundant word line. That is, the redundant memory cell block SCB00 is selected.

At this time, as described above, the redundancy instruction signal RS
Since P00 is "H", in the normal decoder control circuit NDC10 shown in FIG. 4, even if the memory cell array selection signal RSL0 becomes "H", the N-type MOS
Transistors QN73, QN76, QN79, QN82
Is off, and N-type MOS transistors QN74, QN
Since 77, QN80, and QN83 are on, all the normal word line drive signals WDRV00 to WDRV03 are "even if any one of the word line drive signals WDRV0 to WDRV3 has a predetermined word line potential. All normal memory cell blocks NCB00 to NCB of the memory cell array MCA20 are kept as L ″.
0n is not selected. Therefore, the normal word line selected by the combination of the above-mentioned "H" addresses is replaced by the redundant word line.

[0162]

As described above, according to the semiconductor memory device of the present invention, the increase in chip area can be suppressed and the redundancy efficiency can be increased.

[0163]

[0164]

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a first redundant decoder in the semiconductor memory device according to the first embodiment.

FIG. 3 is a circuit configuration diagram of a second redundant decoder in the semiconductor memory device according to the first embodiment.

FIG. 4 is a circuit configuration diagram of a normal decoder control circuit in the semiconductor memory device according to the first embodiment, the second embodiment, and the third embodiment.

FIG. 5 is a block configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a first redundant decoder in the semiconductor memory device according to the second embodiment.

FIG. 7 is a circuit configuration diagram of a second redundant decoder in the semiconductor memory device according to the second embodiment.

FIG. 8 is an explanatory diagram schematically showing the arrangement of addresses assigned to normal memory cell blocks in the semiconductor memory device according to the second embodiment.

FIG. 9 is an explanatory view schematically showing the arrangement of addresses assigned to normal memory cell blocks in the first embodiment or the conventional semiconductor memory device.

FIG. 10 is a block configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 11 is a circuit configuration diagram of a redundant memory cell block selecting fuse circuit block in a semiconductor memory device according to a third example.

FIG. 12 is a block configuration diagram of a semiconductor memory device according to a conventional example.

FIG. 13 is a circuit configuration diagram of a redundant memory cell block selecting fuse circuit block in the semiconductor memory device according to the first example, the second example, and the conventional example.

FIG. 14 is a circuit configuration diagram of a redundant decoder in a semiconductor memory device according to a third example and a conventional example.

FIG. 15 is a circuit configuration diagram of a normal decoder control circuit in a semiconductor memory device according to a conventional example.

FIG. 16 is a circuit configuration diagram of a normal decoder in the semiconductor memory device according to the first embodiment, the second embodiment, the third embodiment, and the conventional example.

[Explanation of symbols]

MCA memory cell array NCB normal memory cell block SCB redundant memory cell block WL normal word line SWL redundant word line NDEC normal decoder SDEC redundant decoder NDC normal decoder control circuit WDRV00-03, 10-13, 20-23, 30-
33 normal word line drive signal WDRV0 to 3 word line drive signal RSL memory cell array selection signal SRSL redundant decoder selection signals XA, XB, XC, A1R, / A1R address signal FB redundant memory cell block selection fuse circuit block RSP redundant instruction signal PRCH Signal VCC Power supply voltage VSS Ground voltage QP P-type MOS transistor QN N-type MOS transistor FU Fuse

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-192092 (JP, A) JP-A 1-229498 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 29/00

Claims (6)

(57) [Claims] 1. A memory cell array having a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, and a plurality of defective normal memory cell blocks among the plurality of normal memory cell blocks being the plurality of redundant memory cells. A redundant memory cell block selecting fuse circuit block having a plurality of fuses that are blown corresponding to addresses of the defective normal memory cell blocks in order to substitute some or all of the blocks; and the normal memory. A normal decoder for controlling access to the cell block; and a redundant decoder for controlling access to the redundant memory cell block, wherein the fuse is blown corresponding to addresses of the defective normal memory cell blocks. Redundant memory cell By inputting an address signal from the lock selection fuse circuit block to the redundant decoder, the defective normal memory cell blocks are replaced with a part or all of the redundant memory cell blocks, The signal is a signal of the lowest address in a normal memory cell block selection address set in the redundant memory cell block selection fuse circuit block. 2. The semiconductor memory device according to claim 1, wherein the two normal memories are one normal memory cell block and another normal memory cell block adjacent to the one normal memory cell block. When the cell block is replaced with two redundant memory cell blocks, one of the address of the one normal memory cell block and the address of the other normal memory cell block is
The common part of the addresses is selected by cutting a common fuse of one redundant memory cell block selecting fuse circuit block, and the different lowest addresses are two fuses corresponding to the lowest addresses. A semiconductor memory device, wherein the two normal memory cell blocks are replaced with the two redundant memory cell blocks by cutting and selecting. 3. A memory cell array having a plurality of normal memory cell blocks and a plurality of redundant memory cell blocks, and a plurality of defective normal memory cell blocks out of the plurality of normal memory cell blocks. A redundant memory cell block selecting fuse circuit block having a plurality of fuses that are blown corresponding to addresses of the defective normal memory cell blocks in order to substitute some or all of the blocks; and the normal memory. A normal decoder for controlling access to the cell block; and a redundant decoder for controlling access to the redundant memory cell block, wherein the fuse is blown corresponding to addresses of the defective normal memory cell blocks. Redundant memory cell By inputting the address signal from the lock selection fuse circuit block to the redundant decoder, the defective normal memory cell blocks are replaced by a part or all of the redundant memory cell blocks, The normal memory cell blocks of
It is a normal memory cell block in which a combination of a plurality of addresses is assigned to each normal memory cell block, and the arrangement form of the assigned addresses is a combination of addresses assigned to one normal memory cell block. And a combination of addresses assigned to other normal memory cell blocks adjacent to the one normal memory cell block, an address of any one of the plurality of addresses forming a combination of the respective addresses. A semiconductor memory device, wherein the combination of the addresses is arranged so that only the addresses are different from each other. 4. The semiconductor memory device according to claim 3, wherein a redundant decoder selection signal determined according to a combination of the addresses assigned to the normal memory cell block is input to the redundant decoder. A semiconductor memory device, wherein the defective normal memory cell blocks are replaced by a part or all of the redundant memory cell blocks. 5. The semiconductor memory device according to claim 4, wherein the two normal memories include one normal memory cell block and another normal memory cell block adjacent to the one normal memory cell block. When the cell block is replaced with two redundant memory cell blocks, one of the address of the one normal memory cell block and the address of the other normal memory cell block is
The common part of the addresses is selected by cutting a common fuse of one of the redundant memory cell block selecting fuse circuit blocks, and different addresses are cut by cutting two fuses corresponding to the different addresses. A semiconductor memory device, wherein the two normal memory cell blocks are replaced by the two redundant memory cell blocks by selecting. 6. The semiconductor memory device according to claim 1, wherein the number of the redundant memory cell block selecting fuse circuit blocks is smaller than the number of the redundant memory cell blocks. Memory device.