JP3482278B2 - Oscillation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to oscillator circuit technology,
For example, an oscillator circuit suitable for generating a system clock signal such as a flash memory (EEPROM), a low power consumption dynamic RAM (hereinafter abbreviated as DRAM), a semiconductor memory device using the oscillator circuit, and a computer system using the semiconductor memory device Related to effective technology.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in a DRAM as a semiconductor memory device, a self refresh cycle is generated at the time of self refresh so that M
A constant current circuit including an OSFET and a resistance element,
It is considered to use an oscillating circuit including a charge / discharge capacitive element and a differential amplifier circuit.

In this oscillator circuit, the constant voltage level generated in the constant current circuit is compared with the voltage level of the capacitive element by the differential amplifier circuit, and the capacitive element is charged or discharged according to the comparison result, and this capacitive element is charged. The element is oscillated by repeating charging and discharging of the element to generate an output signal having a predetermined oscillation cycle.

As a technique relating to a semiconductor memory device using such an oscillation circuit, for example, 1
It is described in documents such as "LSI Handbook" P485-P533, published by Ohmsha Co., Ltd. and edited by The Institute of Electronics and Communication Engineers, January 30th.

[0005]

However, in the oscillation circuit having the constant current circuit composed of the MOSFET and the resistance element as described above, a high resistance element of about 1 MΩ is provided in order to reduce the power consumption of the constant current circuit. As a result, the layout area of the resistance element, the constant current circuit, and further the oscillation circuit may be increased.

For example, in order to reduce the layout area, it is necessary to use a low resistance element, but if a low resistance element is used, power consumption increases. Further, if the steady-state current in the constant current circuit is reduced to reduce the power consumption, it can be considered that the rise time of the internal node voltage at the time of starting the oscillation circuit is delayed.

Therefore, an object of the present invention is to reduce the layout area by realizing a constant current circuit with a low resistance element in consideration of the layout area and power consumption, and increase the current by the low resistance element to a low voltage amplitude. An object of the present invention is to provide an oscillator circuit that can be offset by setting to reduce power supply voltage dependency, a semiconductor memory device using the oscillator circuit, which can achieve large capacity and low power consumption, and a computer system.

Another object of the present invention is to consider the rise time at the time of start-up and to add an additional booster circuit to shorten the rise time, and to increase the speed using the oscillator circuit. It is to provide a semiconductor memory device and a computer system.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the oscillating circuit of the present invention is oscillated by repeating the charging and discharging of the capacitive element connected between the constant current circuit and the differential amplifying circuit. The present invention is applied to an oscillator circuit that generates an output signal, and has a configuration in which a depletion type MOSFET and a low resistance element are combined and connected to the constant current circuit.

In this case, the voltage level of the capacitance element is set to a voltage amplitude lower than the power supply voltage, and a booster circuit for boosting the internal node of the constant current circuit is added.

Specifically, the constant current circuit includes a source of the depletion type first MOSFET and one end of the low resistance element, a drain of the first MOSFET and a drain of the enhancement type second MOSFET, and a second MOSF
ET gate and drain and enhancement type third MOSFET gate, third MOSFET drain and enhancement type fourth MOSFET drain, fourth MOSFET gate and drain and first MOSFET gate, 2nd and 3rd MOSF
ET source and power supply voltage, the other end of the low resistance element and the fourth
The MOSFET source and the ground voltage are connected to each other.

Then, a constant voltage level is generated at the connection node between the gate of the second MOSFET and the gate of the third MOSFET, and the output voltage of the booster circuit added to the constant current circuit is applied to the gate of the fourth MOSFET. Is applied to the connection node between the gate of the depletion type first MOSFET and the gate of the depletion type first MOSFET.

Further, the semiconductor memory device of the present invention has at least a system clock generating circuit having the oscillation circuit built therein, a memory array, and a decoder for selecting an arbitrary memory cell of the memory array, and writing to the selected memory cell is performed. The erase operation is controlled by the system clock signal output from the system clock generating circuit.

Further, the computer system of the present invention has at least a central processing unit and its peripheral circuits in addition to the semiconductor memory device.

[0017]

According to the above-described oscillation circuit, the semiconductor memory device using the same, and the computer system using this semiconductor memory device, the depletion type MOSFET and the low resistance element are connected to the constant current circuit in the oscillation circuit. As a result, a constant current circuit can be realized with a low resistance element by using the depletion type MOSFET, so that it is possible to reduce the power consumption and the layout area.

Further, by setting the voltage amplitude in the oscillation circuit to be low, the power supply voltage dependency of the operation can be reduced without being affected by the voltage fluctuation of the power supply voltage in the oscillation cycle.

Further, by using the booster circuit, it is possible to boost the internal node of the constant current circuit and shorten the rise time of the constant current circuit when the oscillator circuit is started.

As a result, the power consumption of the oscillator circuit is reduced, the layout area is reduced, and the power supply voltage dependency is reduced.
Further, the rise time at the time of startup can be shortened, and a semiconductor memory device and a computer system using this oscillation circuit can have a large capacity and low power consumption, and can be further speeded up.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an oscillator circuit which is an embodiment of the present invention, FIG. 2 is a circuit diagram showing a differential amplifier circuit which constitutes the oscillator circuit of the present embodiment, and FIG. 6 is a circuit diagram showing an oscillation circuit which is a comparative example studied in FIG. 4, FIG. 4 is a functional block diagram showing a semiconductor memory device using the oscillation circuit of this embodiment, FIG. 5 is a waveform diagram showing operation timing of the oscillation circuit, and FIG. FIG. 7 is a waveform diagram showing the operation timing of the booster circuit, and FIG. 7 is a functional block diagram showing a computer system using a semiconductor memory device incorporating the oscillator circuit of this embodiment.

First, the configuration of the oscillator circuit of this embodiment will be described with reference to FIG.

The oscillating circuit of this embodiment is an oscillating circuit that generates an output signal of a predetermined oscillation cycle by an oscillating operation by repeating charging and discharging of a capacitive element, and includes a depletion type first MOSFET Q1 and a resistance value. Low resistance R1 (low resistance element), enhancement type second,
A constant current circuit 1 composed of third and fourth MOSFETs Q2 to Q4 and enhancement type MOSFETs Q5 to Q5.
It is composed of Q7, a capacitor C1 (capacitance element), a differential amplifier circuit CMP2, a delay circuit Delay3, and a booster circuit 4.

In the constant current circuit 1, MOSFETQ
1 source and one end of resistor R1, drain of MOSFET Q1 and drain of MOSFET Q2, MOSFET Q2
Gate and drain of and the gate of MOSFET Q3,
MOSFET Q3 drain and MOSFET Q4 drain, MOSFET Q4 gate and drain and MO
The gate of the SFET Q1, the sources of the MOSFETs Q2 and Q3 and the power supply voltage Vcc, the other end of the resistor R1, and the MOSFET.
The source of TQ4 and the ground voltage are connected to each other, and a signal of a constant voltage level is output. The MOSFETs Q1 and Q4 have an N channel MOS structure, and the MOSFETs Q2 and Q3 are P channel MOS.
It is a structure.

At the connection node between the gate of the MOSFET Q2 and the gate of the MOSFET Q3 of the constant current circuit 1,
MOSFET Q5 whose source is connected to the power supply voltage Vcc
Is connected to the gate of the MOSFET Q6, and the drain of the MOSFET Q5 is connected to the source of the MOSFET Q6 and the MOSFET Q6.
Drain is MOSFET Q7 drain, MOSFE
The sources of TQ7 are each connected to the ground voltage.
Furthermore, the gate of MOSFET Q6 and MOSFET Q7
Is commonly connected to the output terminal of the delay circuit 3, and the drain of the MOSFET Q6 and the MOSFET are connected together.
The node connected to the drain of TQ7 is connected to one end of the capacitor C1 and the positive input terminal of the differential amplifier circuit 2, respectively.

The differential amplifier circuit 2 is, for example, as shown in FIG. 2, enhancement type MOSFETs Q8 to Q11.
And MOSFETs Q8 and Q10 are P-channel MO
S structure, MOSFETs Q9 and Q11 are n-channel MOS
It is made of structure. In the differential amplifier circuit 2, the sources of the MOSFETs Q8 and Q10 and the power supply voltage Vcc, the drains of the MOSFET Q8 and M
OSFET Q9 drain, MOSFET Q10 drain and MOSFET Q11 drain, MOSFET Q
9 and source of MOSFET 11 and ground voltage, MOS
The gate of the FET Q9 and the gate and drain of the MOSFET Q11 are connected to each other.

Further, the gate of the MOSFET Q8 is connected to the capacitor C1, the gate of the MOSFET Q10 is connected to the connection node between the MOSFET Q1 and the resistor R1 of the constant current circuit 1, and the output of the differential amplifier circuit 2 is MOSF.
The voltage is output from the connection node between the drain of the ETQ8 and the drain of the MOSFET Q9, the constant voltage level generated in the constant current circuit 1 is compared with the voltage level of the capacitor C1 by the differential amplifier circuit 2, and the voltage level of the capacitor C1 is compared. As a result, the capacitor C1 is charged or discharged.

The booster circuit 4 includes an inverter IV1 and enhancement type n-channel MOSFETs Q12 and Q13.
And a capacitor C2 and C3, and a start signal CLK
Is input and the boosted output voltage is the MO of the constant current circuit 1.
It is applied to a connection node between the gate of the SFET Q4 and the gate of the MOSFET Q1. In the booster circuit 4, the activation signal CLK is supplied to the inverter IV1 and the MOSF.
It is input to the gate of ETQ12 and this inverter IV1
Output terminal and one end of the capacitor C2, the other end of the capacitor C2 and the drain of the MOSFET Q12, the MOSFET Q
The gate and drain of the MOSFET 13, the source of the MOSFET Q13, and one end of the capacitor C3 are connected to each other.
The other end of is connected to the ground voltage.

The oscillation circuit configured as described above has an enhancement type M in FIG. 3 as compared with FIG. 3 which is a comparative example examined by the present inventor with respect to this embodiment.
OSFETs Q31 to Q41 and a resistor R31 (high resistance element) having a large resistance value of about 1 MΩ to achieve low power consumption.
Since the constant current circuit 1a is constituted by the above, there is a problem of the layout area. However, in the present embodiment, the constant current circuit 1 is formed by the resistor R1 having a small resistance value of about 5 kΩ by using the depletion type MOSFET Q1. Therefore, this problem can be solved.
Note that, in FIG. 3, the other circuit portions except the constant current circuit 1a have the same configuration as that in FIG.

Further, the oscillator circuit of this embodiment is used in a semiconductor memory device such as a flash memory (EEPROM) as shown in FIG. 4, for example, and the flash memory structure of this two-bank structure has a plurality of memory cells arranged in an array. Memory array arranged in a memory array, and a decoder S for selecting an arbitrary memory cell of this memory array
ub Decoder, Gj Decoder, Mai
n Decoder, Y-Decoder, sense amplifier having data sensing operation and data latch function &
Data latch circuit SA & Latch, erase (Eras
e) a control circuit Auto Control for controlling the rewriting operation of writing and programming, and a system clock generating system System C for generating a clock signal for the rewriting operation including the oscillation circuit of the present embodiment.
lock, data input / output buffer I / O buffer
r, address buffer Address Buffer,
Further, it is composed of other control circuits and peripheral circuits.

The basic operation of this flash memory is as follows: Main decoder Main Decoder, Gj decoder Gj via address buffer Address Buffer to which address signals A21 to A0 are input.
The X main system address is designated by the Decoder and the X gate system address is designated by the sub decoder Sub Decoder, while the address signal A is designated for the Y system address.
Address buffer Addre to which Y8 to AY0 are input
ss Buffer, Y decoder Y-Decoder specifies memory array Memory
Any memory cell in the Array is selected.

At the time of read operation, the X of the memory array Memory Array is specified by specifying the address.
System word line and Y system data line are specified, and the data of the memory cell selected by this is sense amplifier &
The data is sensed by the data latch circuit SA & Latch and read as output data I / O0 to 7 from the data input / output buffer I / O Buffer, and the input data from the data input / output buffer I / O Buffer at the time of rewriting operation by erasing and writing. I / O0-7
Thus, the data in the memory cell is rewritten, and the erase and write operations can be performed collectively.

For example, during an erase operation (Erase) and a write operation (Program), the system clock signal SYSCLK output from the system clock generation circuit System Clock is used to cause the pulse generator Pulse Generator to set the system clock signal SYSCLK at a predetermined cycle. The erase controller Erase Contro
l, Program Controller Program Cont
Enter each in roll.

Then, in each controller, an erase control signal ERAS for erase and write operations.
E, erase verify control signal EV, write control signal W
RITE, write verify control signal WV is generated,
Main decoder Main Decoder, Gj decoder Gj Decoder, sub-decoder Sub De
Memory array Memory Arra by coder
By designating an X-system address of y, the rewriting operation by erasing and writing of the memory cell selected by this is performed.

Next, with respect to the operation of this embodiment, the oscillating operation of the oscillating circuit will be described with reference to the circuit diagram of FIG. 1 and the operation timing chart of FIG.

In the operation of this oscillator circuit, first, in a stable state of operation, for example, the MOSFET Q7 is set up at a setup (discharge) time t1 when the output signal φ1 is at the high level.
When the electric charge of the capacitor C1 is discharged via the, the output signal φ1 changes from the high level to the low level. After that, at the charging time t2, the voltage level of the node N1 rises by charging the capacitor C1 with the current passing through the MOSFETs Q5 and Q6 output from the constant current circuit 1.

In the differential amplifier circuit 2, the voltage level of the capacitor C1 and the MOSFET Q of the constant current circuit 1
1 and the voltage level of the connection node N2 between the resistor R1 are compared, and when the voltage level of the node N1 reaches the constant voltage level of the node N2 generated in the constant current circuit 1, the differential amplifier circuit 2
Is activated to change the output signal φ1 from the low level to the high level.

The oscillation operation is performed by repeating the above operation. As a result, a predetermined oscillation cycle (t1
The output signal φ1 of + t2) can be generated.

This output signal φ1 is supplied to the system clock generating circuit System in the flash memory shown in FIG.
m Clock to system clock signal SYSCLK
Is output as this system clock signal SYSCL
K can be used to generate various control signals required for erase and write operations.

At this time, a low voltage amplitude is set in order to cancel the increase in current due to the use of the resistor R1 having a small resistance value, that is, the voltage level of the node N2 reduces the power supply voltage dependence of the oscillation period. For example, power supply voltage V
When cc is 3.3V, it is set to about 1V, which is lower than the power supply voltage Vcc.

As a result, in this oscillator circuit, about 5 kΩ
Since it can be realized by the resistor R1 having a small resistance value, the layout area can be made smaller than that of the comparative example of FIG. 3 in consideration of the layout area and the power consumption, and the current increase due to the resistor R1 having a small resistance value. However, the power supply voltage dependency can be reduced by setting the voltage amplitude as low as about 1V.

Next, the boosting operation by the boosting circuit 4 will be described with reference to the operation timing chart of FIG. It should be noted that this boosting operation is performed at startup before the oscillation operation of the oscillation circuit of FIG. 5 reaches a stable state.

That is, when the oscillation circuit is activated, the activation signal CLK changes from the Low level to the High level to activate the booster circuit 4, which outputs an output voltage that is gradually boosted by charging the capacitors C2 and C3. This voltage is applied to the gate of the MOSFET Q4 of the constant current circuit 1 and the MOS
It is applied to the connection node with the gate of the FET Q1, and the node N
By raising the voltage of 3, the rise time of the constant current circuit 1 can be shortened.

Therefore, according to the oscillator circuit of the present embodiment, by using the depletion type MOSFET Q1 and the resistor R1 having a small resistance value in combination in the constant current circuit 1, the resistance of the depletion type MOSFET Q1 is small. Since the constant current circuit 1 can be realized by R1, the power consumption can be reduced and the layout area can be reduced.

Further, by setting the voltage amplitude in the oscillation circuit to be low, it is possible to reduce the power supply voltage dependency of the oscillation cycle without being affected by the voltage fluctuation of the power supply voltage, and to increase the voltage of the booster circuit 4. By using
When the oscillator circuit is activated, the internal node of the constant current circuit 1 can be boosted to shorten the rise time of the constant current circuit 1.

When this oscillation circuit is used in a semiconductor memory device such as a flash memory, it can be used as a control signal during a rewriting operation by erasing and writing, so that a large capacity and low power consumption are required. It is possible to realize a high speed semiconductor memory device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the oscillator circuit of this embodiment has been described for use in a flash memory, but the present invention is not limited to the above embodiment,
The present invention can be widely applied to other semiconductor memory devices such as DRAM, and is particularly applicable to semiconductor memory devices that require large capacity and low power consumption.

The resistance value of the resistance element is about 5
The resistance is not limited to kΩ, but can be changed according to the characteristics of the MOSFET, and it is particularly preferable to use a resistance element having a small resistance value in consideration of the layout area.

Further, it is not limited to the case of being used in the unit of a storage device such as a flash memory, but is widely used as a storage device of various systems such as a computer system, a digital still camera system and an automobile system, and as an example, FIG. The computer system will be described below.

In FIG. 7, this computer system is a memory for accessing a central processing unit CPU as an information device, an I / O bus built in an information processing system, a Bus Unit, a high speed memory such as a main memory or an extended memory. Control unit Memory Control
A unit, a DRAM as a main memory, a ROM storing a basic control program, a keyboard controller KBDC having a keyboard connected to its tip, and the like. In addition, Display as a display adapter
y Adapter is connected to the I / O bus, and the Di
Display D at the tip of the spray adapter
The display is connected.

Then, the I / O bus is converted into a parallel port Parallel Port I / F, a serial port Serial Port I / F such as a mouse, a floppy disk drive FDD, and an HDD I / F from the I / O bus. Buffer controller HDD
Buffer is connected. Further, an expansion RAM and a DRAM as a main storage memory are connected by being connected to the bus from the memory control unit Memory Control Unit.

The operation of this computer system will now be described. When the power is turned on and the operation is started, the central processing unit CPU first accesses the ROM through the I / O bus to perform initial diagnosis and initial setting. Then, the system program is loaded from the auxiliary storage device into the DRAM as the main storage memory. In addition, the central processing unit CPU sends the HD through the I / O bus.
It operates to access the HDD to the D controller.

When the loading of the system program is completed, the processing is advanced according to the processing request from the user. It should be noted that the user may use the keyboard controller KBDC or the display adapter Display Ad on the I / O bus.
Work is performed while inputting and outputting the processing by the adapter. And if necessary, parallel port Parallel
el Port I / F, serial port Serial
Utilize the input / output device connected to the Port I / F.

DR as a main memory on the main body
When the main memory capacity of the AM is insufficient, the main memory is supplemented by the expansion RAM. When the user wants to read or write a file, the user requests access to the auxiliary storage device assuming that the HDD is the auxiliary storage device. And
The flash file system constituted by the flash memory of the present invention receives it and accesses the file data.

As described above, the semiconductor memory device such as the flash memory of the present invention can be widely applied as a flash file system of a computer system.

[0058]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). By connecting the depletion type MOSFET and the low resistance element in combination to the constant current circuit in the oscillation circuit, the constant current circuit can be realized with the low resistance element by using the depletion type MOSFET.
It is possible to reduce the layout area as well as the power consumption.

(2) By setting the voltage level of the capacitive element to a voltage amplitude lower than the power supply voltage, it is possible to cancel the increase in current due to the use of the low resistance element.
It is possible to reduce the power supply voltage dependency in the operation without being affected by the fluctuation of the power supply voltage in the oscillation cycle.

(3) Since the output voltage of the booster circuit can be applied to the constant current circuit by adding a booster circuit for boosting the internal node of the constant current circuit, the constant current at the time of starting the oscillation circuit is increased. The rise time of the circuit can be shortened.

(4) Due to the above (1) to (3), it is possible to reduce the power consumption in the oscillator circuit, reduce the layout area, reduce the power supply voltage dependency, and shorten the rise time at startup. It is possible to realize a semiconductor memory device using an oscillator circuit, a large capacity and low power consumption of a computer system, and higher speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an oscillator circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a differential amplifier circuit that constitutes the oscillator circuit of the present embodiment.

FIG. 3 is a circuit diagram showing an oscillator circuit which is a comparative example examined with respect to the present embodiment.

FIG. 4 is a functional block diagram showing a semiconductor memory device using the oscillation circuit of this embodiment.

FIG. 5 is a waveform diagram showing the operation timing of the oscillator circuit in the present embodiment.

FIG. 6 is a waveform chart showing the operation timing of the booster circuit in the present embodiment.

FIG. 7 is a functional block diagram showing a computer system using a semiconductor memory device having an oscillation circuit according to the present embodiment.

[Explanation of symbols]

1,1a constant current circuit 2 differential amplifier circuit 3 delay circuit 4 Booster circuit Q1 MOSFET (depletion type) Q2-Q13 MOSFET (enhancement type) R1 resistance (low resistance element) C1 to C3 capacitors (capacitive elements) IV1 inverter Q31 to Q41 MOSFET (enhancement type) R31 resistance (high resistance element) Memory Array Memory Array Sub Decoder Sub Decoder GJ Decoder Gj Decoder Main Decoder Main Decoder Y decoder Y-Decoder SA & Latch sense amplifier & data latch circuit Auto Control control circuit System Clock System clock generation circuit I / O Buffer Data input / output buffer Address Buffer Address Buffer

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatsugu Kubo 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra LSI Engineering Co., Ltd. (56) References 55-88423 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 3/0231

Claims (4)

(57) [Claims] 1. A capacitive element is connected between a constant current circuit and a differential amplifier circuit, and a constant voltage level generated in the constant current circuit and a voltage level of the capacitive element are compared by the differential amplifier circuit. An oscillator circuit that charges or discharges the capacitance element according to a comparison result by the differential amplifier circuit, and oscillates by repeating charging and discharging of the capacitance element to generate an output signal of a predetermined oscillation cycle. An oscillation circuit is characterized in that a depletion type MOSFET and a low resistance element are combined and connected to the constant current circuit. 2. The oscillator circuit according to claim 1, wherein the voltage level of the capacitive element is set to a voltage amplitude lower than a power supply voltage. 3. The oscillation circuit according to claim 1, wherein the constant current circuit in which the depletion type MOSFET and the low resistance element are connected in combination is the depletion type first MOSFET and the low resistance circuit. Resistance element and enhancement type second, third and fourth MO
A first MOSFET, a source of the first MOSFET, one end of the low resistance element, and the first MOSFET.
Drain and the drain of the second MOSFET, the gate and drain of the second MOSFET and the third
MOSFET gate, the drain of the third MOSFET and the drain of the fourth MOSFET, the fourth
Gate and drain of the MOSFET and the first M
The gate of the OSFET is connected to each other, and the second
And the source of the third MOSFET is connected to the power supply voltage, the other end of the low resistance element and the source of the fourth MOSFET are connected to the ground voltage, respectively, and the second MOSFE is connected.
An oscillation circuit, wherein the constant voltage level is generated at a connection node between the gate of T and the gate of the third MOSFET. 4. The oscillator circuit according to claim 3, further comprising a booster circuit for boosting an internal node of the constant current circuit,
The output terminal of the booster circuit is connected to the fourth M of the constant current circuit.
The output voltage of the booster circuit is connected to a connection node between the gate of the OSFET and the gate of the first MOSFET, and the output voltage of the booster circuit is connected to the gate of the fourth MOSFET and the first MOSFET.
An oscillating circuit which is applied to a connection node with a gate of T.