JP3467286B2 - Logical evaluation system - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is directed to a functionally complete family of self-timed logic circuits by application number 07 / 684,720, Jeffry Yetter, filed April 12, 1991. A FUNCTIONALLY COMPLETE FA
MILY OF SELF-TIMED LOGIC CIRCUITS) ". Cross-reference with related applications 1. Application number 07 / 684,720 filed on April 12, 1991
Jeffrey Yetter's "A FUNCTIONALLY COMPLETE FAMILY OF SELF-TIMED LOG
IC CIRCUITS), ”and application number 07 / 684,63, filed April 12, 1991.
7. "UNIVERSAL PIPELINE LATCH FOR MOUSETRAP LOGIC CIR" by Jeffry Yetter
CUITS) ".

The present invention relates generally to dynamic logic in computers, and more particularly to automatic time adjustment for time controlling logic blocks with cascaded automatic timed dynamic logic gates, eg, "mouse trap" logic gates. The present invention relates to an automatically timed clock system for a dynamic logic circuit.

[0003]

2. Description of the Related Art Recently, a functionally complete family of self-timed dynamic logic gates was developed by Jeffry Yetter of Hewlett-Packard Company of Fort Collins, Colorado, USA. These self-timed dynamic logic gates are configured to implement a vector logic system. In the proposed vector logic system, more than two valid logic states propagate through the logic. In addition, the mouse trap logic gate precharge is used to achieve a monotonic progression of logic evaluation.

In monotonic progression, consider a logical transition in only one direction. For example, in the mousetrap logic gate,
Consider only the logic transition from logic low to logic high, not the logic transition from logic high to logic low. As a result of performing a monotonic progression, the problems associated with static hazards are gone.

Further, since the vector logic states in the present invention are encoded in a physical manner that takes into account invalid states, and because the dynamic precharge method is implemented, it consists of one or more cascaded mousetrap logic gates. The output from the mousetrap logic block can be "self-timed", that is, configured to operate synchronously with respect to the clock source that provides the precharge signal. In other words, the clock or other charging signal is only used to precharge the mousetrap logic gate, and the clock does not direct the progress of logic evaluation by the cascade mousetrap logic gate. Each individual mousetrap logic gate is triggered by a smooth logic evaluation performed by the corresponding logic associated with the mousetrap logic gate. Therefore, using a vector logic system with mousetrap logic gates, two important features can be obtained from each vector output. (1) When the vector output is valid, the need for a traditional valid clock signal is eliminated. And (2) the value of the vector output when it is valid.

When the mousetrap logic gates are cascaded in series, the vector inputs are automatically timed to advance through the gates. Each subsequent gate will evaluate its vector input once it has validated its corresponding vector input. Moreover, cascaded mousetrap logic gates can be precharged in parallel by a clock,
A logical evaluation can then be made on the vector.

[0007]

However, the clock system must be constructed so that the logical evaluation is given sufficient time to proceed completely through the cascade network. Further, the clock system must be configured to give sufficient time to precharge all the cascade gates. As a result of the above requirements,
The vector output of the cascade gate often has to wait for an edge of the clock before it can proceed to another mousetrap logic block. Therefore, a lot of time is wasted. As a result, there is a need for an automatically timed clock system and method that optimally takes advantage of the automatically timed nature of mousetrap logic gates and other dynamic logic gates that have the property of automatically timed.

The present invention optimizes the speed of logic evaluations performed on logic blocks consisting of cascaded self-timed dynamic logic gates. The present invention is particularly applicable to a family of self-timed dynamic logic gates known as "mouse trap" logic gates.

[0009]

SUMMARY OF THE INVENTION In a first embodiment of the invention, logic blocks are precharged in parallel and a comprehensive self-timed logic evaluation is performed on vector inputs to obtain vector outputs. It has a cascading automatic timed dynamic logic block. The evaluation run detector is configured to monitor the output of the logic block to ensure that the vector output is valid. Finally, the logic block clock generator is set by the trigger signal and reset by the evaluation run detector. The logic block clock generator provides a precharge signal to the logic blocks, thereby defining each precharge period and providing an evaluation period for self-timed logic evaluation within the logic block.

The second embodiment of the present invention comprises all of the same components as the first embodiment, but the second embodiment further comprises a precharger which sets the trigger signal which sets the logic block clock generator. -Different in that it has a run detector.

[0011]

The operation of the first embodiment is as follows. First, the precharge is started to prepare the cascaded timed dynamic logic blocks in parallel. The cascaded auto-timed dynamic logic block can thus perform a logic evaluation on the vector input to obtain the vector output. Once the vector output has been validated by the evaluation run detector,
Another precharge of the cascaded auto-timed dynamic logic block is started immediately.

The operation of the second embodiment is generally self-timed and asynchronous to all other clock sources, including the system clock. Still other features and advantages of the present invention will be apparent to one of ordinary skill in the art in view of the following drawings and detailed description.

[0013]

【Example】

Description of the preferred embodiment table of contents I Logical system A. Vector logic B. Mousetrap logic gate 1. Construction 2. motion 3. Inclusive OR gate 4. Adder predecoder gate 5. Carry transmission gate 6. Shared ladder logic 7. Exclusive OR gate

II. Self-timed clock system A. First embodiment B. Second embodiment

I. Logic System The present invention provides, among other things, a system for time controlling a mousetrap logic block comprising a cascaded self-timed dynamic logic block, such as, but not limited to, a "mousetrap" logic gate. Purpose. Mouse trap logic gate, April 1991
Parent application number 07 / 684,720 filed on 12th, "A functionally complete family of self-timed logic circuits (A FUNCTIONAL
LY COMPLETE FAMILY OF SELF-TIMED LOGIC CIRCUITS
) ”Is the main subject matter. For a clear understanding of the invention, a brief discussion of mousetrap logic gates follows.

A. Vector Logic Typically, computer logic is encoded in binary values for one logical path, which is often just a wire or a semiconductor path. By definition, a high signal level, usually a voltage or current, indicates a high logic state ("1" in the signal of the program). In addition, a low signal level indicates a low logic state ("1" in the programming language).

The present invention contemplates implementing "vector logic" by cascading mouse trap gates. Vector logic is a logical structure capable of propagating more than two valid logic states through the logic gates of a computer. Unlike traditional binary logic, where there are two (high, low) valid logic states defined by one logic path,
The vector logic of the present invention allows for invalid logic states by providing more than one logic path for each valid logic state.

For example, according to one embodiment, in a vector logic system that requires two valid logic states:
Two logical paths are needed. If the two logic paths are both logic low, ie , "0,0", then there is an invalid logic state by definition. Moreover, a logic high that is exclusively present in either of the two logic paths, ie, "1,0" or "0,1", corresponds to two valid logic states of the vector logic system. Finally, the scenario when both logic paths are high, ie , "1,1", is an undefined logic state in a vector logic system.

In a vector logic system that requires three logic states according to another embodiment, three logic paths are required. The same applies below. In conclusion, according to the previous embodiment, a logic system with n valid logic states and one invalid state has n logic paths.

Further, encoding of vector logic states can be handled by defining valid vector logic states by logic highs on more than one logic path, but invalid when all paths exhibit low logic signals. The state is still defined. In other words, vector logic states are not mutually exclusive.

For example, in a vector logic system that uses a pair of logic highs to define each valid vector logic state, the following logic mechanism can be implemented. Using three logic paths, "0,1,1" represents vector logic state 1, "1,0,1" represents vector logic state 2 and "1,1,0" represents vector logic state 3. Can point. In the case of four logic paths, six effective vector logic states can be specified. In particular, "0,0,
"1,1" is the vector logic state 1, "0,1,0,1"
Is a vector logic state 2, "1,0,0,1" is a vector logic state 3, "0,1,1,0" is a vector logic state 4, and "1,0,1,0" is a vector Logic state 5
And “1,1,0,0” can refer to vector logic state 6. Using 5 logic paths, up to 10 valid logic states can be specified. The same applies below.

As another example, a vector logic system in which three logic paths define each valid vector logic state can be obtained in accordance with the present invention. In conclusion, as is well known to those skilled in the art, the above-mentioned vector mechanism can be summarized by mathematical formulas. The formula of the combination is as follows.

[0023]

[Equation 1]

Here, the variable n is the number of logical paths (vector components), and the variable m is the number of logical paths that define the effective vector logic states (ie, the logic height must be given to specify a particular vector logic state). The number of logical paths that must be present) and the variable i is the number of possible vector logic states.

B. Mouse Trap Logic Gates FIG. 1 is a high level block diagram of a family of "mouse trap" logic gates according to the present invention. The mousetrap logic gate, which we will discuss in more detail below, is capable of fast vector logic, is functionally complete, and is self-timed to avoid static hazards when connecting each stage in a chain. It is not subject to the adverse logical reaction that occurs.

As shown in FIG. 1, each input to the mousetrap logic gate 100 of the present invention is a vector input I,
J, ..., K (future vector variables will be shown in bold)
Is the vector that is marked. Vector input I, J, ...
.., There is no limit on the number of K.

Further, each of the vector inputs I, J, ..., K can be specified by any number of vector components, each vector component being I0 to I in FIG.
It has dedicated logic paths labeled N, J0-JM, and K0-KS.

In effect, each vector input specifies a vector logic state. As mentioned above, the vector input I,
An invalid vector logic state for any of J, ..., K has all its corresponding vector components, I, respectively.
Present by convention when 0-IN, J0-JM, and K0-KS are logic lows.

The output of the general mousetrap logic gate 100 is also a vector, labeled vector output O. The vector output O is composed of vector components O0 to OP. The vector components O0-OP are mutually exclusive and are independent functions of the vector inputs I, J, ..., K. Further, vector components O0-OP have dedicated mousetrap gate components 102-106 within mousetrap logic gate 100, respectively. By definition, in the present invention, only one of O0-OP and one is in a logic high state for a particular aging.

Moreover, there is no limit as to the number of vector components O0-OP that can be associated with the output vector O. The number of vector components O0-OP, and thus the number of mousetrap gate components 102-106, is a logical function to be performed on vector inputs individually or as a whole,
Besides the number of required vector output components, it also depends on other considerations regarding the logic purpose of mousetrap logic gate 100.

1. Structure Referring to FIG. 1, each mousetrap gate component 102-106 of mousetrap logic gate 100 includes:
It consists of a readiness mechanism 108, a ladder logic 110, and an inversion buffer mechanism 112. Preparation and maintenance mechanism 1
18 prepares the mousetrap logic gate 100,
It is a precharge means for resetting, that is, an urging means.

The servicing mechanism 108 acts essentially as a switch, thereby selectively applying the voltage V0 defining the logic state of line 116 when excited by the clock signal (high or low) on line 114. As will be appreciated by those skilled in the art, any type of switching element or buffer that selectively applies voltage based on a clock signal can be used. Further, when the logic of the computer system is based on current levels rather than voltage levels, the servicing mechanism 108 can be a switchable current source, which is also well known to those skilled in the art. All embodiments that perform the required switching functions as the readiness mechanism 108 are intended to be incorporated here.

The ladder logic 110 uses vector inputs I, J,
... Performs a logical function for K. Ladder logic 1 corresponding to each mousetrap gate component 102-106
10 is each mouse trap gate constituent element 102-106
It can change depending on the purpose of. In the preferred embodiment, the ladder logic 110 is a substantially simple logic gate, such as a logical O.
A combination of R gates and / or logical AND gates, which are connected in series and / or in parallel. It should be noted that the ladder logic 110 is configured in the present invention to be a logic high at some sample of one and only one of the vector output components O0-OP. Specific embodiments of ladder logic 110 are described below with respect to the illustrations of FIGS.

The ladder logic 110 is different from the ready maintenance mechanism operating by preparing establish a first mousetrap gate components, but are on the critical logic paths, the data passes through the mousetrap gate components to Nawa
Then , since it temporarily enters a rest state while actually flowing through the critical logic path, it must operate at high speed. Moreover, since the ladder logic 110 sits on a critical logic path that is effectively provided with logic intelligence, multiple logic gates are generally required to perform the required logic functions.

Also on the logical path is the inversion buffer mechanism 112. The inverting buffer mechanism 112 primarily acts as an inverter because it must have the inverting function in the critical logic path to perform the full logic function in the mousetrap logic gate 100. In addition, the inverting buffer mechanism 112 provides gain to the signal on line 114, and the mousetrap logic gate component 102 ...
Isolate between each of the other possible stages of the mouse trap gate component similar to 106. The feature of the inverting buffer mechanism 112 is that the input impedance is high and the output impedance is low. Inversion buffer mechanism 11
All buffer implementations such as 2 are intended to be incorporated here.

It is also worth noting that the readiness mechanism 108, the ladder logic 110, and the inverting buffer mechanism 112 are all one integrated circuit (IC) in one embodiment.
For example, it can be mounted on an application specific integrated circuit (ASIC) or microprocessor chip.

2. Operation The operation of mousetrap logic gate 100 is described below at a high conceptual level for mousetrap gate component 102 only for simplicity. To reduce this description is to use various mousetrap components 102-106.
Is sufficiently redundant, except for their corresponding ladder logic functions performed by the ladder logic 110, 120, and 130, there is good reason. Therefore, the following description is equally applicable to the remaining mousetrap gate components 104 and 106.

In operation, the readiness mechanism 108 pulls up when excited by the clock CK on line 114,
That is, the output 116 of the ladder logic 110 is a logic high. At the same time, the servicing mechanism 108 brings the input to the inverting buffer mechanism 112 on line 114 to a logic high. As a result, the corresponding vector component O0 on line 117 maintains a logic low state, which is defined as an invalid state in the present invention. In the above-mentioned initial state, the mouse trap logic gate 1
00 can be said to be similar to a "mouse trap" in the traditional sense of the word, it is set and waiting to be triggered by vector inputs I, J, ..., K.

The mousetrap logic gate 100 remains in the ready state with the vector component O0 in the invalid state until triggered by the ladder logic 110. The mousetrap logic gate 100 is line 117
Triggered upon receipt of enough valid vector inputs I, J, ..., K to unambiguously determine the correct state of the vector component O0 at. In some configurations of ladder logic 110, it is not necessary to consider all inputs in order to produce an output signal on line 116, and thus line 117. The number of vector inputs I, J, ..., K required to clearly determine the output state and the timing of the decision is defined by the contents and configuration of the simple logic gates inside the ladder logic 110. To be done.

Once the vector component O0 is available on line 117, the vector component O0 is passed to the next stage of logic (not shown). The mousetrap logic gate component 102
It does not perform any further function until it is reset, re-prepared, or refreshed by the servicing mechanism 108. In a sense, the gate-to-gate timing as well as the mousetrap gate component to the mousetrap gate component is determined by the encoded data itself. In other words, the mousetrap gate component is "self-timed."

The mousetrap logic gate according to the present invention directly performs the inverting and non-inverting functions. Therefore, in contrast to conventional dynamic logic gates, mousetrap logic gates can perform multiplications and additions that require inversion of logic at extremely high speeds.

Finally, mousetrap logic gate 100
It should be noted that the family of can be electrically connected in series, i.e. cascaded, to obtain a combinatorial logic gate that performs the logic function as a whole. Therefore, the mousetrap gate component consisting of the readiness mechanism, ladder logic, and the inversion buffer mechanism can be conceptualized as the smallest sub-portion of the mousetrap logic gate.
Moreover, various mousetrap gate components can be connected in series and / or in parallel to obtain multiple logic gates.

However, if the mousetrap logic gates are linked together as a long chain (probably with three or more mousetrap gate components in series), precharging the chain requires an undesirably long time. Become. The reason is that the mousetrap gate component cannot pull its output low (disable) until its input is pulled low. As a result, the mousetrap gate components will charge in sequence from beginning to end of the chain, undesirably slowing the precharge of the entire chain. Therefore, there is a need for a method of precharging the mousetrap gate components of a chain in parallel rather than sequentially.

Parallel precharge can be done in several different ways. The preferred method is to provide a clock-triggered n-channel MOSFET to provide the ladder logic 110 of FIG.
Disable 120, and 130 during precharge of the mousetrap gate component. In other words, the push-pull situation is realized. The mousetrap gate component prep mechanism raises (precharges) the input to the inverting buffer mechanism high while n is inserted.
The channel MOSFET pulls the ladder logic low.

It should be noted that the n-channel MOSFET slows the operation of the mousetrap gate component slightly. However, it should be emphasized that an n-channel MOSFET need not be implemented for each mousetrap gate component. It need only be inserted in series every two or three mousetrap gate components.
Moreover, in certain logic circuits, such as multiplication, logic operations can be used in parallel to reduce the number of n-channel MOSFETs required.

The above-described embodiment of performing parallel precharge has advantages. It requires almost no extra power consumption. Moreover, if desired, it can be applied uniformly to all mousetrap gate components for simplicity.

Another preferred method for parallel precharging mousetrap gate components connected in series is to periodically insert a mousetrap AND gate into the critical logic path. The mousetrap AND gate receives (1) the output vector component from the previous mousetrap gate component and (2) the precharge clock.
The output of the mousetrap AND gate is input to the next mousetrap gate component in series.

3. Inclusive OR Gate FIG. 2 shows a low level block diagram of an example of a two input OR mousetrap logic gate 200 according to the present invention of FIG.
The OR mousetrap logic gate 200 can be used in a vector logic system with two logic states and one invalid logic state.

As shown, OR mousetrap logic gate 200 has two mousetrap gate components 2
There are 02 and 204. The mousetrap gate component 202 comprises a readiness mechanism 208, ladder logic 210, and an inversion buffer mechanism 212. The mouse trap gate component 204 is the preparatory maintenance mechanism 21.
8, ladder logic 220, and inversion buffer mechanism 222
It consists of Note that the reference numerals are similar for the other figures that follow in addition to FIG.

The OR mousetrap logic gate 200 and, in particular, the servicing mechanisms 208 and 218 are serviced by the instruction of the clock NCK ("N" is active at logic low) on lines 214 and 224, respectively. In the preferred embodiment of the present invention, the servicing mechanisms 208 and 218 are p-channel metal oxide semiconductor field effect transistors (MOSFETs), as shown in FIG. 2, which are well known to those skilled in the art and are commercially available. Available. The n-channel MOSFET can be used instead of the p-channel MOSFET, but the clock is clearly the exact opposite.

With reference to FIG. 2, the MOSFETs comprising servicing mechanisms 208 and 218 act essentially as switches and, when excited by the low clock NCK signal on respective lines 214 and 224, apply a voltage V0 to respective lines 216 and 226. Apply. Any type of voltage related switching element can be used, as will be further known to those skilled in the art.

In addition, in the preferred embodiment, ladder logic 210
The simple logic by 220 and 220 is implemented in an n-channel MOSFET as shown. n-channel MOSFET
The rationale for using is as follows. N-channel MOSFETs have better drive capability, space requirements, and load specifications than comparable p-channel MOSFETs. A typical n-channel MOSFET can generally switch about 50% faster than an equivalent p-channel MOSFET with similar specifications.

Further, in the preferred embodiment, the inverting buffer mechanisms 212 and 222 are static CMOS FEs, as shown in FIG.
A T inverter, which is well known to those skilled in the art and is commercially available. CMOSFET inverters are used for several reasons. As mentioned above, inversion must be carried out in the critical theoretical path in order to be functionally complete. The inversion that must be done in the critical theoretical path is the p-channel MOSFET pull-up 215 and the n-channel MO.
This can be done by judiciously operating the configuration (gain) of a conventional MOSFET inverter consisting of both SFET pulldowns 219. In other words, due to the presence of the known monotonic progression, the ratio of the widths of the MOSFET gates is unidirectional .
That is , high (1) to low (0) or low (0) to high (1)
The "he" can be configured to facilitate at the expense of other directions.

In particular, the particular CMOSFETs contemplated by the present invention
In the inverter, the component p-channel MOSFET 215
Is wider than the gate width of the component n-channel MOSFET 219. Therefore, the output of the CMOSFET inverter is from logic low (0; mouse trap ready state) to logic high (1; mouse trap unmaintained state).
Switch very quickly to. Logic High to Logic Low CMOSFET
The speed of inverter output switching is not critical, as the mousetrap gate 200 is precharged during this period. Therefore, the mousetrap logic gate 20
0 can be configured to exhibit excellent performance and size specifications in one direction, which significantly increases the speed of data transfer and reduces the size specification of mousetrap logic gate 200.

In operation, the truth table for OR mousetrap logic gate 200 is shown in Table A below.

Table A a b o AH AL BH BL OH OL inv inv inv 0 0 0 0 0 0 0 inv 0 inv 0 0 0 1 0 0 0 inv inv 0 1 0 0 0 0 0 1 x 1 1 0 x x x 1 0 x 1 1 x x x 1 0 1 0

In Table A above, "x" indicates an irrelevant or "don't care" situation, "inv" indicates an invalid logic state, "1" indicates a high logic state, and "0" is a low logic state. Indicates.

As shown in Table A and illustrated in FIG.
Vector input a and vector input b are operated by OR mousetrap logic gate 200 to obtain vector output o. For purposes of explanation, it is worth noting that vector input a, vector input b, and vector output o correspond to vector input I, vector input J, and vector output o of FIG. 1, respectively.

Vector input a specifies a vector logic state defined by two vector components AH and AL.
Vector input b specifies the vector logic state defined by the other two vector components BH and BL. The vector output o specifies the vector logic state defined by the two vector components OH and OL, which describes the inclusive separation (OR function) of the vector inputs a and b.
In vector notation, as shown in the figure, a = <AH, AL>, b
= <BH, BL>, and o = <OH, OL> = a + b.

4. Additive Predecoder Gate FIG. 3 illustrates a low level block diagram of the 2-input adder predecoder mousetrap logic gate 300 of FIG. 1 in accordance with the present invention. As is well known to those skilled in the art, a predecoder is the logic primarily used in arithmetic logic units (ALUs) that perform arithmetic functions, especially additions. In general, the predecoder helps parallel processing and helps control the carry bit path.

As shown, the predecoder 300 comprises three mousetrap gate components 305-306. Each of the three mousetrap gate components 302-306 is comprised of: (1)
Preparation and maintenance mechanism 308, ladder logic 310, and buffer 312, (2) Preparation and maintenance mechanism 308, ladder logic 32
0, and buffer 322; and (3) preparatory maintenance mechanism 3
28, ladder logic 330, and buffer 332. A truth table describing the operation of add predecoder logic gate 300 is shown in Table B below.

Table B a b o AH AL BH BL P KG inv x inv 0 0 x x 0 0 0 0 x inv inv x x 0 0 0 0 0 0 0 0 0 kill 0 1 0 1 0 1 1 0 0 1 prop 0 1 1 0 1 0 0 1 1 0 prop 1 0 0 1 1 1 0 0 1 1 1 gen 1 0 1 1 0 0 0 1

The OR mousetrap logic gate 20 of FIG.
Like 0, the vector input a specifies a vector logic state defined by two vector components AL and AL.
Vector input b specifies the vector logic state defined by the other two vector components BH and BL. But,
In contrast to the mousetrap logic gate of FIG. 2, the vector output o has three vector components P, described in detail below.
Specifies the vector logic state defined by K and G. In vector notation, as shown in the figure, a ＝ ＜ AH, AL
>, B = <BH, BL>, and o = <P, K, G>.

Traditional predecoders are usually arranged so that the output exhibits only one of two logic states. In many embodiments, should the traditional pre-decoder "propagate" the carry (indicated by "P")?
Or indicates that the carry bit should be "killed" (indicated by "K"). In other embodiments, the predecoder indicates whether the carry should be "propagated" or the carry bit should be "generated" (denoted by "G").

In the present invention, the vector output o, as noted in Table B, has four logic states, an invalid state and three valid states: stop, propagate and occur.
Can be any of the following:

Further, the addition predecoder logic gate 300
Must perform an exclusive OR function as part of the overall predecoder function. Traditionally, dynamic logic gates are
The EXCLUSIVE-OR function could not be performed because of the logic error resulting from the static hazard. Static hazards arise in combinatorial logic configurations due to propagation delays. Since the mousetrap logic gate of the present invention is self-timed, it is not adversely affected by static hazards. There are no valid vector output components except when all the vector inputs needed to explicitly define the output of the ladder logic are valid as shown in Table B.

5. Carry Propagate Gate FIG. 4 shows a low level block diagram of a carry propagate gate 400 according to the present invention. As is well known to those skilled in the art, a carry propagate logic gate is often used in series with an add predecoder logic gate, as described above, to control the carry bit path in the ALU. In particular, the carry propagate gate 400 works in series with the add predecoder logic gate 300 of the preferred embodiment to provide a high performance carry bit path.

The carry propagation gate 400 comprises two mousetrap gate components 402 and 404. The mousetrap gate component 402 comprises a readiness mechanism 408, ladder logic 410, and an inversion buffer mechanism 412. The mousetrap gate component 404 includes a preparatory mechanism 418, ladder logic 420,
And an inversion buffer mechanism 422.

To further clarify the function of the carry propagation gate 400, a truth table for the carry propagation gate 400 is shown in Table C below.

Table C I CIN COUT P K G CINH CINL COUTH COUTL inv x inv 0 0 0 x x x 0 0 x x inv inv x x x x 0 0 0 0 kill x 0 0 0 1 0 x x 0 0 1 prop 0 0 1 0 0 0 1 0 1 prop 1 1 1 1 0 0 1 1 0 1 0 gen x 1 0 0 0 1 x x x 1 0

6. Shared Ladder Logic FIG. 5 shows a high-level block diagram of one embodiment of a mousetrap logic gate, in this embodiment a number n of ladder logic 510 to mousetrap gate components.
520 is associated with a single mousetrap logic gate 500A. A plurality of vectors I, J, ... K, and / or parts thereof are input to the mousetrap logic gate 500A. Instead, the mouse trap logic gate 500A has a plurality of vector output components <O1 to On>.
, Which may define vectors and / or subvectors.

Practically, the logical function that generated the vector output component <On> is the vector output components <O1> to <On>.
It is a subset of all logical functions that get up to -1>.
More specifically, the vector output component <O1> is determined by the ladder logic 510, 520, while the vector output component <On> is determined by the ladder logic 520 alone. As is apparent from FIG. 5, this configuration saves hardware and cost. More outputs can be obtained with less ladder logic.

7. Exclusive OR Gate A specific example of FIG. 5 is shown in FIG. FIG. 6 shows a low level block diagram of a 3-input exclusive-OR (XOR) mousetrap logic gate 500B. The exclusive-OR mousetrap logic gate 500B can be used for fast sum calculations in either full adders or half adders and is not adversely affected by static hazards. Summing logic gates are well known to those skilled in the art. This gate is particularly useful in adder and multiplier logic circuits.

Exclusive OR Mouse Trap Logic Gate 50
The 0A includes two mousetrap gate components and also includes reversal buffer mechanisms 532 and 542 in addition to their respective servicing mechanisms 538 and 548.
However, as indicated by virtual line block 550, the ladder logic associated with each of the two mousetrap gate components is not completely separate in hardware and remains mutually exclusive in a logical sense. Has become. Therefore, as a general proposition, the ladder logic of each mousetrap gate component of the mousetrap logic gate uses the same type of gate, ie, an n-channel MOSFET, so that sometimes their logic functions require the same hardware. They can be shared, which reduces the total number of gates and reduces the physical assets of the computer used.

Exclusive OR Mouse Trap Logic Gate 50
A truth table showing the operation of OB is shown in Table D below.

Table D a b c s AH AL BH BL CH CL SH SL inv x x inv 0 0 x x x x x 0 0 x inv x inv x x 0 0 0 x x 0 0 0 x x x inv inv x x x x x 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 0

As shown in Table D and illustrated in FIG. 6, vector input a specifies a vector logic state defined by two vector components AH and AL. Vector input b
Specifies the vector logic state defined by the other two vector components BH and BL. Vector input c specifies the vector logic state defined by the two vector components CH and CL. Furthermore, the vector output s has two outputs SH
And specify the vector logic state defined by SL. In vector notation, as shown in the figure, a ＝ ＜ AH, AL
>, B = <BH, BL>, c = <CH, CL>, and s = <S
H, SL>.

Another specific example of FIG. 5 is shown in FIG. FIG. 7 shows a low level block diagram of a 3-input exclusive-OR (XOR) logic gate 500C in combination with a 2-input exclusive-OR (XOR) logic gate. Vector input is a = <AH, AL>, b = <B
H, BL>, and c = <CH, CL>. In addition to the XOR logical function of the vectors a and b defined by the vector output components <O0, O1>, the vector output includes the vectors a, b defined by the vector output components <On-1, On>, and It is an XOR logic function of c. The vector output components <O0, O1> are determined by the ladder logics 560 to 590, but the vector output components <On-1, On> are determined only by the ladder logics 580, 590. It is worth noting that FIG. 7 shows mousetrap logic with multiple vector inputs and multiple vector outputs.

II. The self-timed clock system of the present invention A. First Embodiment FIG. 8 shows a first embodiment of the present invention. As shown in FIG. 8, the first embodiment is an automatic timed dynamic logic block 60.
2, an evaluation execution detector 604, a logic block clock generator 606, and an optional edge detector 608. The present invention implements an automatic timed clock system 600 to more fully utilize the automatic timed nature of the automatic timed dynamic logic block 602.
In essence, the evaluation execution detector 604 detects the completion of the logic evaluation performed by the self-timed dynamic logic block 602 to immediately start another precharge period without having to wait for another clock edge. To do. In this way, the precharge period is automatically adjusted by the dynamic logic block 6
02 automatically timed.

The auto-timed dynamic logic block 602 includes a number of cascaded auto-timed logic gates, eg,
A mouse trap logic gate 100 is provided. Moreover, the self-timed dynamic logic block 602 can comprise a number of cascaded logic branches. In other words, a number of vector inputs 610 can be operated on the self-timed dynamic logic block 602 to obtain a number of vector outputs 612.

FIG. 9 shows a low level block diagram of the evaluation run detector 604. As shown in FIG. 9, vector output components I0 to IN, J0 of the respective vector outputs I, J, K
-JM, K0-KS, for example, each O
It operates with R logic gates 702, 704, and 706. OR
The output of each of the logic gates 702-706 is whether or not the respective vector output has been received from the self-timed dynamic logic block 602, or in other words,
Indicates whether the self-timed dynamic logic block 602 has completed its logic evaluation of each vector output I, J, K so that it is valid. Moreover,
The logical AND operation produces an evaluation execution detector output 616 which reflects whether all vectors have been fully evaluated by the self-timed dynamic logic block 602, so that the AND gate 718 produces an OR gate output. 71
2 to 716.

Vector output components I0-IN, J0 which must be considered at the input of the evaluation run detector 604.
In order to minimize the number of ~ JM, K0 ~ KS, only representative subsets can be input to the OR gates 702-706 of the evaluation execution detector 604. The representative subset should have a vector component path that ensures that all outputs have been evaluated and are valid. Therefore, OR gates 702-70
6 can minimize the consumption time and physical assets.

Returning to FIG. 8, logic block clock generator 606, in the preferred embodiment, has a set (S) input that receives trigger signal 614, a reset (R) input that receives evaluation run detector output 616, and an automatic time adjustment. It can be a traditional flip-flop memory device with the generator output (Q) being passed to the dynamic logic block 602.
Logic block clock generator 606 can also provide an inverted output (-Q; not shown) to self-timed dynamic logic block 602 if desired.

The optional edge detector 608 of FIG. 8 is a trigger signal 6 for the logic block clock generator 606.
14 is generated. In essence, the edge detector 608, in the preferred embodiment, provides a set signal 614 to the logic block clock generator 606 when a rising edge or falling edge is detected by the incoming periodic timing signal 620. It is a state machine. Periodic timing signal 6
20 is a certain arbitrary periodic signal. In the preferred embodiment, the periodic timing signal is the system clock so that vector output 612 is synchronous with the system clock. However, many other types of periodic timing signals, even those that are not synchronized to the system clock, can be utilized, as will be further described with respect to the second embodiment of the present invention. Finally, it should be emphasized that the edge detector 608 and its associated periodic timing signal 620 are merely optional and that other mechanisms may be utilized to generate the trigger signal 614. .

The operation of the first embodiment shown in FIG. 8 will now be described with reference to FIG.
The timing diagram 800 shown in FIG. Referring to FIG. 10, the duty cycle is about 50.
% Periodic timing signal 620 is shown as an example. As indicated by reference arrow 801 (step 1),
The rising edge of periodic timing signal 620 causes edge detector 608 to generate a trigger signal 614 indicating a logic high. This logic high causes the logic block clock generator 6
06, as indicated by the reference arrow 802 (step 2),
A logic high logic block clock signal 618 is provided to the self-timed dynamic logic block 602. Moreover, the transition of the logic block clock signal 618 to a logic high removes the trigger signal 614 from the edge detector 608, as indicated by reference arrow 803 (step 3).

Next, the automatic time adjustment dynamic logic block 60.
2 has a vector input 61 to obtain a vector output 612
0 can be evaluated logically. When the self-timed dynamic logic block 602 finishes its logical evaluation of the vector input 610, the evaluation execution detector 604 is shown in FIG.
A logic high is provided to the logic block clock generator 606, as indicated by arrow 804 (step 4) at zero. As a result, the logical block clock signal 618 is removed.

Finally, the logic block clock signal 618
After transitioning to a logic low (precharge), the evaluate execution detector is cleared as indicated by the reference arrow (step 5). The clearing of the evaluation run detector 604 is due to the precharge in the self-timed dynamic logic block 602 causing all of the vector outputs 612 to be logic low or disabled.

As a result of using the system clock in the first embodiment, the self-timed dynamic logic block 602 can operate synchronously with the system block and at twice the frequency of the system clock. But,
The self-timed dynamic logic block 602 is the second part of the present invention.
As described below with respect to the embodiment of FIG. 1, it can operate asynchronously to the system clock and much faster.

B. Second Embodiment FIG. 11 shows a second embodiment of the present invention. In the second embodiment, the precharge execution detector 904 is made to generate a trigger signal 620 which sets the logic block clock generator 606, as described with respect to the first embodiment. In essence, the precharge execution detector 904 detects that the self-timed dynamic logic block 602 has completed its parallel precharge of the self-timed dynamic logic gates it comprises. After precharging, the evaluation period can begin immediately with the self-timed dynamic logic block 602. Therefore, the second embodiment provides a fully self-timed clock system in which both the evaluation period and the precharge period are self-timed events.

Precharge execution detector 904 is essentially similar in structure to the evaluation execution detector as shown and described with respect to FIG. However, it should be noted that the precharging of the self-timed dynamic logic block 602 is done in parallel. Vector components I0 to IN, J which must be considered at the input of the precharge execution detector 904.
In order to reduce the number of 0 to JM and K0 to KS as much as possible, only the typical subset is precharged by the precharge execution detector 90.
4 OR gates 702-706. The representative subset should have a vector component path that consumes the maximum amount of time to precharge. As a result, the consumption time and assets required by the OR gates 702 to 706 can be minimized.

The foregoing description of the first and second embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously numerous modifications and variations are possible in light of the above teaching.

[0092]

As described in detail above, according to the present invention, the automatic time adjustment operation pre-charged in parallel by the logical block clock signal set by the trigger signal and output from the logical block clock generator. Dynamic logic block performs a comprehensive timed logic evaluation of the vector input and outputs the vector output, which is monitored by the evaluation execution detector without waiting for other clock edges to make the vector output valid. Then, the logic block clock generator is reset so that the precharge period of the automatic timed dynamic logic block is regulated. There is an effect that the speed of the logical evaluation performed in 1 can be optimized.

[Brief description of drawings]

FIG. 1 shows a high level block diagram of a family of dynamic logic gates referred to as "mouse trap" logic gates that can be transmitted according to the present invention.

2 shows a low-level block diagram of a 2-input inclusive OR mousetrap logic gate according to FIG.

FIG. 3 shows a low-level block diagram of the two-input add predecoder damus trap logic gate according to FIG.

4 shows a low level block diagram for use in series with the carry propagate mousetrap logic gate according to FIG. 1 and the add predecoder of FIG.

FIG. 5 shows a high level block diagram of a mousetrap logic gate with split ladder logic.

FIG. 6 shows a low level block diagram of a 3-input exclusive-OR mousetrap logic gate according to FIG.

FIG. 7 is a combination 2-input / 3-input exclusive O according to FIG.
FIG. 3 shows a low level block diagram of the R Mousetrap Logic Gate.

FIG. 8 shows a high level block diagram of a first embodiment of the present invention.

9 shows a high-level block diagram of the evaluation run detector of FIG.

10 shows a timing diagram of the first embodiment of FIG.

FIG. 11 shows a high level block diagram of a second embodiment of the present invention.

[Explanation of symbols]

100,200 mousetrap gate 102,104,106 402,404 mousetrap gate component 300 additive predecoder mousetrap logic gate 302,304,306 additive mousetrap gate component 400 digits Up Propagation Gate 500A Mouse Trap Logic Gate Components 500B, 500C 3 Input Exclusive OR Logic Gate 600 Automatic Timed Clock System 602 Automatic Timed Dynamic Logic Block 604 Evaluation Execution Detector 606 Logic Block Clock Generator 608 Edge detector 904 Precharge execution detector

─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Glen Dee Colon-Bonnet Fort Collins, Colorado, United States Oxford Lane 745 (72) Inventor Robert Jay Martin Timnas, Colorado, USA 5300 (56) References Japanese Patent Laid-Open No. 5-233214 (JP, A) Japanese Patent Laid-Open No. 3-139916 (JP, A) Special Table 1-501749 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) ) H03K 19/096 G06F 7/00

Claims (3)

(57) [Claims] 1. Automatically timed movement in cascade.
System for speeding up logic evaluation of dynamic logic gates
A is, are pre-charged to the gate parallel, a logic block having a cascaded dynamic logic gates may issue a collectively executed by vector output logic evaluation adjusted automatically time for vector input An evaluation run detector configured to monitor the output of the logic block and determine when the vector output is valid; a first signal set by a trigger signal to a first logic level; A logic block clock generator for outputting a clock signal that is reset to two logic levels, the logic block clock generator being adapted to provide the clock signal to the logic block, the clock signal of the second logic level, define respective precharge period, the first logic level of the clock signal , The respective system configured to define the evaluation period for the logic evaluation, adjusted the automatic time in the logic block. 2. A system for speeding up logic evaluation of a self-timed dynamic logic block having a precharge period and an evaluation period, the system having inputs and outputs and precharging during the precharge period. A logic block having a cascaded dynamic logic gate for performing an automatic timed logic evaluation of the input during the evaluation period to output the output; and a logic block connected to the output for sensing the output. Is connected to the evaluation execution detector for determining when the logic block has completed the logic evaluation and ending the evaluation period, and the logic block and the evaluation execution detector.
Function for receiving a periodic timing signal, the evaluation period
The function of terminating the interval, the logical block being the logical evaluation
And then add a precharge to the logic block.
By starting the precharge period
No. by stopping the application of the precharge
A function to end the precharge period and the periodic
The evaluation period is set for each change in the logic state of the timing signal.
A means having the function of initiating . 3. A system for using an automatically timed dynamic logic block having a precharge period and an evaluation period at a rate twice as high as the system clock while maintaining a synchronous operation with the system clock. And a output, and comprising a cascaded dynamic logic gate that is precharged during a precharge period and that performs an automatic timed logic evaluation on the input during the evaluation period to output the output. A block, an evaluation execution detector connected to the output for determining when the logic block has completed the logic evaluation by sensing the output, and ending the evaluation period; the logic block and the logic block; A function of receiving a system clock connected to an evaluation execution detector, a function of ending the evaluation period; A function of starting the precharge period by applying a precharge to the logic block after the charge is completed, a function of ending the precharge period by stopping the application of the precharge, and a logic of the system clock. A unit having a function of starting the evaluation period each time the state changes.