JP3420165B2 - Nonvolatile semiconductor memory device, manufacturing method thereof, and data storage method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, a method of manufacturing the same, and a data storage method. More specifically, the present invention can non-volatilely store fixed information that needs to be permanently retained and semi-fixed information that is determined and stored afterwards in the same memory area. Semiconductor memory device, manufacturing method thereof, and data storage method.

[0002]

2. Description of the Related Art A non-volatile semiconductor memory can hold information without supplying power and does not require a driving part such as a motor. Therefore, it will rapidly spread in the future as a storage medium for portable information devices and information home appliances. It is expected that. In most information devices, the factory default information is stored in ROM (Re
ad only memory). The user who purchases the information device first starts the information device by using the factory settings. Then, at the time of initial setting or thereafter, user-specific settings are made as necessary. After that, when it is necessary to restore the factory settings, the user-specific settings are erased or the user-specific information is temporarily not read.

In the specification of the present application, for example, permanent information which is already written in the nonvolatile semiconductor memory device at the time of factory shipment and is not rewritten thereafter is referred to as "fixed information". Information that can be appropriately written and rewritten can be referred to as “semi-fixed information”.

Conventionally, in order to store both fixed information and semi-fixed information in a non-volatile manner, a non-writable fixed ROM area for holding information at the time of factory shipment and an EEPROM (Electrically) for writing user-specific settings. Erasa
ble Programmable ROM) and the area of the same chip, or it was necessary to be mounted on the information equipment as a separate chip.

A mask ROM is used as the fixed ROM.

FIG. 14 is a conceptual diagram for explaining the principle of the mask ROM. That is, the mask ROM is, for example, an FET (feild) formed on the surface of the p-type semiconductor substrate 1.
effct transistor) as a basic structure, and information is written depending on the presence or absence of the source n + diffusion layer 6. For example, in FIG.
As shown in (a), the case where the source n + diffusion layer 6 exists and the electron current flows is “information: 1”, and the source n + diffusion layer 6 does not exist as shown in FIG. The case where no current flows corresponds to "information: 0". For writing such information, the source n + diffusion layer 6 and the drain n +
It is realized by a pattern of a mask for ion implantation when forming the diffusion layer 7.

On the other hand, as a ROM in which the user can write semi-fixed information, there is an EEPROM.

FIG. 15 is a conceptual diagram for explaining the principle of the EEPROM. That is, the EEPROM has a basic structure of an FET formed on the semiconductor substrate 1, and further has a gate having a first gate insulating film 2, a floating gate (charge storage layer) 3, a second gate insulating film 4, It has a double gate structure including the control gate 5.

The EEPROM can store information depending on the presence or absence of electrons in the floating gate 3. For example, as shown in FIG. 15A, there is no electron in the floating gate 3 and the threshold value is low, so that an electron current flows, “information: 1”, and as shown in FIG. It is possible to correspond to “information: 0” when the electron current does not flow because the electron exists in 3 and the threshold value is high.

To write electrons into the floating gate 3, for example, the source electrode 10 and the p-type semiconductor substrate 1 are grounded or low, and the control gate 5 and the drain electrode 11 are provided with 10 electrons.
A voltage of about 20 V is applied to generate channel thermoelectrons. Alternatively, the p-type semiconductor substrate 1 and the source electrode 10 are opened, the drain electrode 11 is grounded or low, a voltage of 10 to 20 V is applied to the control gate 5, and the drain n + diffusion layer 7 to the floating gate 3 are applied. To F
Writing can also be performed by generating an NT (Fowler-Nordheim Tunneling) current. Alternatively, the p-type semiconductor substrate 1 is grounded or low, and the source electrode 10
And the drain electrode 11 is opened and the control gate 5 has 10
It is also possible to apply a voltage of 20 V and write from the p-type semiconductor substrate 1 to the floating gate 3 with an FNT current.

In actual application, in the memory area for writing the semi-fixed information peculiar to the user, EEPRO of FIG.
The user can perform the above-described write operation for M. When the user erases data, the source electrode 10
And the drain electrode 11 are opened, the p-type semiconductor substrate is grounded or low, and the control gate 5 is -10 to -20.
By applying a voltage of V, the electrons in the floating gate 3 can be erased by the tunnel phenomenon with the first gate insulating film.

The EEPROM may be used as a fixed information holding area at the time of factory shipment as an area in which writing and erasing cannot be performed by the user.

[0013]

However, in the prior art, in order to hold the fixed information at the time of factory shipment and the semi-fixed information determined by the user afterwards, the individual information as shown in FIG. 14 and FIG. Had to be provided on the same chip or as separate chips. As a result, there is a problem that the area occupied by the memory becomes large and the configuration becomes complicated.

The present invention has been made based on the recognition of such problems. That is, the purpose thereof is a non-volatile semiconductor memory device capable of non-volatilely storing fixed information that needs to be permanently retained and semi-fixed information that is determined and stored afterwards in the same memory area. And a manufacturing method thereof and a data storage method.

[0015]

In order to achieve the above object, a nonvolatile semiconductor memory device of the present invention has a plurality of gates formed on a semiconductor layer of the first conductivity type, each of which has a charge storage region. A nonvolatile semiconductor memory device provided, comprising: a second conductivity type low resistance drain region formed in the semiconductor layer adjacent to the gate, wherein the gate is provided for each of the plurality of gates. Fixed information is stored at the time of manufacture depending on whether a portion of the source region that faces the low resistance drain region and is adjacent to the gate is a low resistance region or a high resistance region for the second conductivity type charge. It is possible to store semi-fixed information after manufacturing depending on whether or not charges are stored in the charge storage region.

That is, in the EEPROM array having silicide in the source / drain regions, the information at the time of factory shipment is written depending on the presence / absence of ion implantation of the source diffusion layer. No charge is written to the floating gate when shipped from the factory. At the time of reading information, the drain electrode and the control gate are set to high potential (high), and the source electrode is set to ground or low potential (low). When the user writes unique information, the drain electrode and the control gate are set to a potential higher than the voltage level for reading, and the source electrode is set to the ground or low potential. At this time, even in the cell having no source diffusion layer, charges are written in the floating gate by the thermal carrier injection from the Schottky junction between the silicide and the semiconductor substrate. When reading user-specific information, the drain electrode is set to ground or low potential, and the source electrode and control gate are set to high potential. When reading the information at the time of factory shipment, the electric charge of the floating gate is erased, the drain electrode and the control gate are set to high potential, and the source electrode is set to ground or low potential. The writing of charges may be performed by FNT from the drain diffusion layer or the semiconductor substrate.

It is also possible to use Si3N4 for the gate insulating film and polycrystalline silicon for the control gate, and use the interface state between them as the charge storage region. Further, the gate insulating film may be made of a ferroelectric substance, and the user may write unique information by polarization thereof.

The source side silicide may be used as the high resistance region of the low concentration diffusion layer.

In the structure having silicide on the source side, the barrier height may be adjusted so as to suppress the leakage current of majority carriers between the source / substrate of the Schottky junction. A buried oxide film may be provided in the semiconductor substrate 1 to suppress the leakage current of majority carriers between the source and the substrate. A diffusion layer having a conductivity type opposite to that of the semiconductor substrate may be provided at a position where the depletion layer surrounds the Schottky junction end in contact with the gate electrode to suppress leakage current of majority carriers between the source and the substrate.

[0020]

According to the present invention, the information at the time of factory shipment can be held by the presence / absence of one side of the source / drain diffusion layer of the EEPROM. That is, the fixed information can be stored by a method similar to that of the mask ROM. Further, user-specific information can be written by injection of thermal carriers from the Schottky junction or FNT from the diffusion layer even in a cell having no diffusion layer.
That is, the semi-fixed information can be stored by a method similar to the EEPROM.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing the configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention. That is, the nonvolatile semiconductor memory device of the present invention has a memory area in which two types of memory cells C0 and C1 are arranged in a matrix. Each of the memory cells C0 and C1 is connected to the bit line B and the word line W, and data can be read and written. And the factory default information, that is, the fixed information that needs to be maintained permanently, is
It is stored as a pattern of arrangement of the memory cells C0 and C1. The array pattern shown in FIG. 1 is merely an example, and the array pattern of the memory cells C0 and C1 changes depending on the content of the fixed information to be stored.

These memory cells C0 and C1 are provided with storage elements T0 and T1 having different configurations.

Next, the memory elements T0 and T1 will be described in detail.

FIGS. 2A and 2B are conceptual diagrams illustrating the configurations of the memory elements T1 and T0, respectively. The memory cell C1 may be composed of only the storage element T1 shown in the drawing, or may be combined with a circuit element such as another transistor not shown in the drawing. The same applies to the storage element T0 included in the memory cell C0.

Each of the memory elements T1 and T0 has a structure similar to that of an FET, and a source silicide 8 and a drain silicide 9 are formed in the source / drain regions on the surface of the p-type semiconductor substrate 1. In addition, the gate is the first
Gate insulating film 2, floating gate (charge storage layer) 3, second
Has a double gate structure including the gate insulating film 4 and the control gate 5.

The memory element T1 has the source n + diffusion layer 6 formed as shown in FIG. 2A, while the memory element T0 has the source n + diffusion layer 6 as shown in FIG. 2B. No diffusion layer is formed. Such a source n +
Fixed information can be written depending on the presence or absence of the diffusion layer 6. The presence / absence of the source n + diffusion layer 6 can be determined by the mask pattern at the time of forming the diffusion layers 6 and 7, as in the case of the mask ROM described above with reference to FIG.
That is, in the present invention, the fixed information can be written in the semiconductor memory device by the mask pattern when the diffusion layers 6 and 7 are formed. This manufacturing method will be described later in detail with reference to the drawings.

Next, the operation for reading the fixed information thus written will be described.

That is, assuming that no electrons are written in the floating gate 3 in any of the storage elements,
In the structure of FIG. 2A, the gate voltage Vg and the drain voltage V
When d is made high, a current flows from the source n + diffusion layer 6 toward the drain n + diffusion layer 7. The state in which this current flows can be determined as, for example, "fixed information: 1".

On the other hand, in the structure of FIG. 2B, since the tunnel probability for the electron current from the source silicide 8 to the p-type semiconductor substrate 1 is low, almost no electrons flow into the channel region below the floating gate 3. The state in which this current does not flow can be determined as, for example, "fixed information: 0".

By arranging the two kinds of memory cells corresponding to each bit of the digital data in this way, fixed information such as factory settings and programs is source n + diffusion layer 6
It is possible to write to the nonvolatile semiconductor memory device depending on the presence or absence of. Specifically, the mask ROM illustrated in FIG.
In the same manner as in the above case, the permanent fixed information can be written by the pattern of the ion implantation mask when forming the source n + diffusion layer 6 and the drain n + diffusion layer 7.

Next, the operation in the case where the user later writes the unique semi-fixed information will be described.

The memory element T1 shown in FIG. 2 (a) has substantially the same structure as a normal EEPROM. Therefore, the gate voltage Vg and the drain voltage Vd are 10 to 10 respectively.
When a voltage of about 20 V is applied and the source voltage is set to ground or low, the electrons traveling from the source n + diffusion layer 6 are overheated, and thermal electrons are written in the floating gate 3 near the drain n + diffusion layer 7. .

On the other hand, in the case of the memory element T0 shown in FIG. 2B, an electron tunnel current from the Schottky junction between the source silicide 8 and the p-type semiconductor substrate 1 is used.

FIG. 3 is a conceptual diagram for explaining a data writing method in the memory element T0. Storage element T0
In FIG. 3, when a voltage of about 10 to 20 V is applied as the gate voltage Vg and a drain voltage Vd and the source voltage is set to ground or low, an energy band structure as shown in FIG. 3A is formed. . Then, thermoelectrons are emitted from the source silicide 8 due to the tunnel phenomenon.
It is injected into the mold semiconductor substrate 1. The injected thermoelectrons are written in the floating gate 3 as shown in FIG. 3B by the positive potential of the gate voltage Vg. The semi-fixed information thus written is non-volatile as in the case of the conventional EEPROM, and can be semi-permanently retained without using a backup power source or the like.

As described above, according to the present invention, fixed information and semi-fixed information can be written in the same storage element.

Next, the operation of reading the semi-fixed information written by the user in this way will be described.

FIG. 4 is a conceptual diagram showing the operation when reading semi-fixed information. That is, (a) and (c) of FIG.
Represents the memory element T1, and FIGS. 7B and 7D represent the memory element T0.

When reading semi-fixed information written by a user or the like in these storage elements, the source voltage Vs is set high and the drain voltage Vd is grounded, contrary to the case of reading fixed information at the time of factory shipment. Or low (lo
w)

When no electrons are written in the floating gate 3, as shown in FIGS. 4A and 4B, when the gate voltage Vg and the source voltage Vs are set to high, the drain n + diffusion layer 7 is formed. The electrons flow from the source diffusion layer 6 toward the source diffusion layer 6. Therefore, such a case where electrons flow can be determined as "semi-fixed information: 1".

On the other hand, when electrons are written in the floating gate 3, the threshold voltage of the transistor operation becomes high in any of the memory elements shown in FIGS. 4C and 4D, so that the gate voltage is increased. Vg and source voltage Vs are high (hi
gh), but no electrons flow. Therefore, it is possible to determine the case where the electrons do not flow in this way as "semi-fixed information: 0".

As described above, the semi-fixed information written in the same memory element can be read by applying the voltage in the opposite direction to the case of reading the fixed information.

Next, the operation of erasing the semi-fixed information written by the user will be described.

In order to erase the semi-fixed information, the source electrode 10 and the drain electrode 11 are opened and the p-type semiconductor substrate 1 is opened.
To ground or low, and control gate 5 to -10
A voltage of -20V is applied. In this way, the electrons written in the floating gate 3 pass through the first gate insulating film 2 by the tunnel phenomenon and flow out to the semiconductor substrate 1 to be erased.

After erasing the semi-fixed information in this way, new semi-fixed information can be written in the memory element by the operation described above with reference to FIG.

After erasing the semi-fixed information, the gate voltage Vg and the drain voltage Vd are set to high to determine the presence or absence of electron flow. Information can also be read.

Next, a method of manufacturing the nonvolatile semiconductor memory device of the present invention will be described.

FIG. 5 is a process sectional view showing an essential part of the method for manufacturing a nonvolatile semiconductor memory device of the present invention. That is,
The figure shows a manufacturing process of the diffusion layers 6 and 7 in the memory elements T1 and T0, in other words, a conceptual diagram showing a process of writing fixed information.

First, as shown in FIG. 5A, a first gate insulating film 2, a floating gate (charge storage layer) 3, a second gate insulating film 4 are formed on a p-type semiconductor substrate 1. A double gate structure consisting of the control gate 5 is formed.

Next, as shown in FIG. 5B, one side of the memory element T0 is masked by a mask M1 such as a resist. Then, arsenic (A
The source n + type diffusion layer 6 and the drain n + diffusion layer 7 are formed by introducing an n-type dopant such as s) and performing heat treatment as appropriate. At this time, the source n + type diffusion layer 6 is not formed in the portion covered with the mask M1. By selectively introducing the n-type dopant with the mask M1 in this manner, the memory elements T1 and T0 can be formed separately. That is, the semiconductor memory device can be manufactured while writing the fixed information by the mask M1.

Next, as shown in FIG. 5C, the mask M1 is removed and a metal layer ME such as cobalt (Co) is deposited.

Then, as shown in FIG. 5D, heat treatment is applied to alloy the metal layer ME with the semiconductor substrate 1, thereby forming a source silicide 8 and a drain silicide made of cobalt silicide (CoSi 2). Silicide 9
Can be formed. The remaining portion of the metal layer ME where the silicide is not formed is removed by etching or the like.

Thereafter, an electrode layer (not shown), an interlayer insulating layer,
A nonvolatile semiconductor device is completed by sequentially forming wiring layers and the like.

As described above, according to the present invention, by separately forming the memory elements T1 and T0 according to the pattern of the mask M1, it is possible to manufacture the semiconductor memory device while writing the fixed information.

Next, a modified example of the present invention will be described.

First, as a first modification, a specific example of writing semi-fixed information by FNT (Fowler-Nordheim Tunneling) will be described.

That is, in FIG. 3, the operation of writing semi-fixed information by the user is illustrated by thermoelectrons, but the present invention is not limited to this. For example, writing is performed using FNT. You can also

FIG. 6 is a conceptual diagram showing the operation of writing semi-fixed information to the memory element T0 by FNT.

As shown in the figure, the p-type semiconductor substrate 1 and the source electrode 10 are opened, the drain electrode 11 is grounded or low, and a voltage of 10 to 20 V is applied to the control gate 5. Then, an FNT current is generated from the drain n + diffusion layer 7 to the floating gate 3, and electrons can be written.

Alternatively, the p-type semiconductor substrate 1 and the drain electrode 11 are grounded or made low, the source electrode 10 is opened, and a voltage of 10 to 20 V is applied to the control gate 5. Then, the p-type semiconductor substrate 1 and the drain n + diffusion layer 7 are formed.
FNT current is generated from the floating gate 3 to the electrons, and electrons can be written.

In the memory element T1 having the source n + diffusion layer 6, electrons can be written by the same method.

Next, as a second modification of the present invention, a structure in which charge trapping is used as a charge storage region instead of the floating gate 3 will be described.

FIG. 7 is a conceptual diagram showing a memory element using charge trapping.

For example, in the figure, the control gate 5 is formed of polycrystalline silicon, and the silicon nitride (Si3N4) film 13 is formed under the control gate 5. In such a laminated structure, the control gate 5 and the gate insulating film 13 are
An interface level IL is likely to be formed between and. Then, semi-fixed information is written by trapping electrons in the interface state IL. As a method to capture electrons,
A thermoelectron tunneling a Schottky junction from the silicide 8 is used. That is, a voltage of about 10 to 20 V is applied as the gate voltage Vg and the drain voltage Vd, and the other terminals are grounded or low. Then, electrons are injected from the source silicide 8 into the p-type semiconductor substrate 1 by the tunnel phenomenon, and the electrons are written in the interface state by the positive potential of the gate voltage Vg.

FIG. 7 exemplifies the memory element without the source n + diffusion layer 6, but in the case of the memory element having the source n + diffusion layer 6, if the same bias as that described above is applied, the source n + diffusion layer 6 is also applied. It is possible to write the thermoelectrons having a high energy in the vicinity of the drain n + diffusion layer 7 traveling from the above to the interface state.

Further, FNT may be used instead of using thermoelectrons.

FIG. 8 is a conceptual diagram showing a method of writing electrons in the interface state IL using FNT. In this case, the p-type semiconductor substrate 1 and the source electrode 10 are opened, and the drain electrode 11 is grounded or low. Further, a voltage of 10 to 20 V is applied to the control gate 5. Then, from the drain n + diffusion layer 7 to the interface state IL, FNT
An electric current is created and electrons can be written.

Alternatively, the p-type semiconductor substrate 1 and the drain electrode 11 are grounded or low, the source electrode 10 is opened, and a voltage of 10 to 20 V is applied to the control gate 5. Then, the p-type semiconductor substrate 1 and the drain n + diffusion layer 7 are formed.
To generate an FNT current in the interface state IL, and electrons can be written.

These methods can be similarly applied to the structure having the source n + diffusion layer 6 to write electrons.

Also in the modified example using the charge trap described above, the reading of the fixed information at the time of factory shipment and the reading of the semi-fixed information written by the user are performed with reference to FIGS.
Can be done by methods similar to those described above with respect to.

Further, the charge trapped in the interface level IL can be erased in the same manner as the above-mentioned method.

Next, as a third modification of the present invention, a structure in which a ferroelectric material is used for the gate insulating film will be described.

FIG. 9 is a conceptual diagram showing a memory element using a ferroelectric film.

That is, a laminated structure composed of the ferroelectric film 14 and the control gate 5 is formed on the semiconductor substrate 1. In the case of this memory element, the p-type semiconductor substrate 1 and the drain electrode 11 are grounded or low, the source electrode 10 is opened, and a voltage of 10 to 20 V is applied to the control gate 5. Then, the ferroelectric film 14 is polarized, so that the threshold value is increased and information can be written. Information can be written by a similar method even in the structure having the source n + diffusion layer 6.

Also in this modification, the reading of the fixed information and the reading of the semi-fixed information can be performed in the same manner as the method described above with reference to FIGS. Further, the polarization of the ferroelectric film 14 is eliminated by applying a voltage having a polarity opposite to that at the time of writing.

Next, as a fourth modified example of the present invention, a structure in which a high resistance diffusion layer is provided instead of the source silicide will be described.

FIG. 10 is a conceptual diagram showing a memory element of this modified example. That is, (a) of the figure corresponds to the memory element T1, and (b) of the figure corresponds to the memory element T0.
In this modified example, no silicide is provided, and instead, a low-concentration high-resistance diffusion layer 15 having a low impurity concentration is selectively formed on the source side of the memory element T0. Even if the high resistance diffusion layer 15 is provided in this manner, the above-described operation can be realized.

Next, as a fifth modified example of the present invention, a structure for suppressing current leakage by forming a Schottky junction on the source side of the memory element will be described.

FIG. 11 is a conceptual diagram showing an energy band structure when a Schottky junction is formed on the source side of the memory element. In the figure, φB is the barrier height also shown in FIG. 3, and ε _gap is the band gap of the semiconductor substrate 1. As shown in FIG. 11, φB <ε
_{When gap} / 2 is set, the barrier for holes is higher than that for electrons as shown in FIG. 9A than that for electrons as shown in FIG. As a result, it is possible to suppress the leakage current of holes between the source and the substrate when writing and reading the semi-fixed information.

Next, as a sixth modification of the present invention, a structure for suppressing the leak current on the source side by providing a buried insulating film will be described.

FIG. 12 is a conceptual diagram showing a memory element provided with a buried insulating film. That is, in the memory elements T1 and T0, the buried insulating film 16 is provided in the p-type semiconductor substrate 1, and the leak current of holes between the source and the substrate is suppressed. Such a structure using the embedded insulating film 16 can be realized by using an SOI (silicon on insulator) technique or the like.

Next, as a seventh modified example of the present invention, a structure in which a depletion layer is used to suppress a leakage current will be described.

FIG. 13 is a conceptual diagram showing the structure of the storage element according to this modification. That is, the storage element T of FIG.
1 has a structure similar to that illustrated in FIG.
The memory element T0 of 3 (b) has an n + diffusion region 1 on the source side.
7 is provided away from the gate. More specifically, the n + diffusion layer 17 is provided so that the depletion layer extending from the n + diffusion region 17 encloses the Schottky junction end in contact with the gate insulating film 2. Even in this case, the leakage current of holes between the source and the substrate can be suppressed.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

For example, the configuration of the semiconductor memory device illustrated in FIG. 1 is merely an example, and those skilled in the art may appropriately change the design of the arrangement of the memory cells C0 and C1 or the connection relationship with the bit lines and word lines. The same effect can be obtained.

The configuration of the memory element illustrated in FIG. 2 and the like is also merely an example, and for example, those skilled in the art can appropriately change the conductivity type and material of each part to obtain the same effect. For example, pMOSF instead of nMOSFET
You may comprise using ET. Furthermore, multi-valued storage in which data other than “0” and “1” can be stored can be similarly implemented by changing the laminated structure of the gate portion or by using a plurality of charge amounts and polarization amounts.

[0087]

As described in detail above, according to the present invention,
It is possible to store fixed information such as factory settings and semi-fixed information that is determined afterwards in the same memory cell. Therefore, it is not necessary to separately provide the ROM area, the chip area can be reduced, and the complication of the configuration due to the embedded memory can be solved.

Further, the semi-fixed information can be erased / rewritten at any time, and the convenience can be ensured.

As described above, according to the present invention, it is possible to realize a non-volatile semiconductor device having a function equal to or higher than that of the conventional one, which is smaller and lighter than that of the conventional one, and to be applied to various portable and other information devices. When applied, the industrial advantages are enormous.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2A and FIG. 2B respectively show a memory element T.
It is a conceptual diagram which illustrates the structure of 1 and T0.

FIG. 3 is a conceptual diagram for explaining a data writing method in a storage element T0.

FIG. 4 is a conceptual diagram showing an operation when reading semi-fixed information.

FIG. 5 is a process cross-sectional view illustrating the main part of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 6 is a conceptual diagram showing an operation of writing semi-fixed information to a storage element T0 by FNT.

FIG. 7 is a conceptual diagram showing a memory element using charge trapping.

FIG. 8 is a conceptual diagram showing a method of writing electrons in an interface state IL using FNT.

FIG. 9 is a conceptual diagram showing a memory element using a ferroelectric film.

FIG. 10 is a conceptual diagram showing a memory element of a modified example of the present invention.

FIG. 11 is a conceptual diagram showing an energy band structure when a Schottky junction is formed on the source side of a memory element.

FIG. 12 is a conceptual diagram showing a memory element provided with a buried insulating film.

FIG. 13 is a conceptual diagram showing a configuration of a storage element according to a modified example of the present invention.

FIG. 14 is a conceptual diagram for explaining the principle of a mask ROM.

FIG. 15 is a conceptual diagram for explaining the principle of the EEPROM.

[Explanation of symbols]

1 p-type semiconductor substrate 2 First gate insulating film 3 Charge storage layer 4 Second gate insulating film 5 control gates 6 Source n + type diffusion layer 7 Drain n + diffusion layer 8 Source silicide 9 Drain / silicide 10 Source electrode 11 drain electrode 12 Mask ROM gate electrode 13 Si3N4 film 14 Ferroelectric film 15 Low concentration source n-type high resistance diffusion layer 16 buried insulating film 17 Source n + diffusion layer for depletion layer formation

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/788

Claims (15)

(57) [Claims] 1. A non-volatile semiconductor memory device comprising a plurality of gates formed on a semiconductor layer of a first conductivity type, each of which is provided with a charge storage region, the semiconductor layer being adjacent to the gate. A second conductive type low resistance drain region formed, and, for each of the plurality of gates, a portion of the source region facing the low resistance drain region across the gate and adjacent to the gate. Fixed information can be stored at the time of manufacturing by setting a low resistance region or a high resistance region for the second conductivity type charge, and semi-fixed information can be stored after manufacturing depending on whether the charge is stored in the charge storage region. A non-volatile semiconductor memory device characterized by being storable. 2. A non-volatile semiconductor memory device comprising a first conductive type semiconductor layer and a plurality of first memory elements and a plurality of second memory elements provided on the semiconductor layer. In the first memory element, both the source region and the drain region adjacent to the gate having the charge storage region are low resistance regions, and the second memory element is adjacent to the gate having the charge storage region. The source region is a high resistance region and the drain region is a low resistance region, and fixed information is stored by the arrangement of the first and second memory elements on the semiconductor layer. 2. A non-volatile semiconductor memory device capable of storing semi-fixed information depending on whether charge is accumulated in the charge accumulation region of the second memory element. 3. A non-volatile semiconductor memory device comprising a semiconductor layer of a first conductivity type, and a plurality of first memory elements and a plurality of second memory elements provided on the semiconductor layer. The first memory element includes a gate having an insulating layer provided on the semiconductor layer and a charge storage region provided on the insulating layer, and sources on both sides of the gate adjacent to the gate. A second conductive type low resistance region provided in each of the region and the drain region, and the second memory element is provided on the insulating layer provided on the semiconductor layer and on the insulating layer. A high resistance region provided adjacent to the gate in its source region and a second resistance type low resistance region provided in its drain region adjacent to the gate. And having the first on the semiconductor layer. And fixed information is stored by the arrangement of the second storage element, and semi-fixed information can be stored depending on the presence / absence of charge storage in the charge storage regions of the first and second storage elements. Semiconductor memory device. 4. The source region is grounded or has a low potential,
4. The fixed information can be read by making the drain region and the gate high potential and discriminating the magnitude of the amount of current detected in the drain region. 1. The nonvolatile semiconductor memory device described in 1. 5. The semi-fixed information can be read by identifying the magnitude of the amount of current detected in the source region by setting the source region to a high potential and the drain region and the gate to ground or a low potential. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is enabled. 6. A conductor for forming a Schottky junction with the semiconductor layer is provided on a surface of the source region adjacent to the gate.
A nonvolatile semiconductor memory device according to item 4. 7. The non-volatile according to claim 6, wherein said Schottky junction has a higher Schottky barrier for a first conductivity type charge than a Schottky barrier for a second conductivity type charge. Semiconductor memory device. 8. A second conductivity type impurity diffusion region is formed in a part of the source region, and a depletion layer extending from the impurity diffusion region toward the semiconductor layer extends over the Schottky junction and under the gate. 8. The non-volatile semiconductor memory device according to claim 6, wherein the non-volatile semiconductor memory device can be extended up to. 9. The low resistance region contains a second conductivity type impurity at a high concentration, and the high resistance region contains a second conductivity type impurity at a low concentration. 5. The nonvolatile semiconductor memory device according to any one of items 5 to 5. 10. A floating gate as the charge storage region, wherein the gate and the drain region have a high potential, the source region has a ground potential or a low potential, and the second conductivity type charge is diffused or tunneled from the source region. Is injected into the channel region of the semiconductor layer below the gate, and the second conductivity type charge is heated by the electric field applied to the channel region to write to the floating gate, or the semiconductor layer and the source Region and open the drain region to ground or low potential, to set the gate to high potential, to write charges to the floating gate by tunnel current from the drain region, or to ground the semiconductor layer and the drain region Alternatively, the source region is opened to a low potential, the gate is set to a high potential, and the semiconductor layer and the drain are The semi-fixed information is stored by writing a charge to the floating gate by a tunnel current from a region, the drain region is grounded or at a low potential, the source region and the gate are at a high potential, and the drain region is detected. The semi-fixed information is read by identifying the magnitude of the amount of current to be applied, the source region and the drain region are grounded or at a low potential or open, and the semiconductor layer is grounded or at a low potential,
The semi-fixed information is erased by applying a potential having a sign opposite to the high potential at the time of storage to the gate to erase the charge written in the floating gate by a tunnel phenomenon. The non-volatile semiconductor memory device according to claim 1. 11. An interface level formed at an interface between silicon and silicon nitride is used as the charge storage region, the gate and the drain region are set to a high potential, and the source region is set to a ground or a low potential, and the source is set. The second conductivity type charge is injected into the channel region of the semiconductor layer under the gate from the region by diffusion or tunnel, and the second conductivity type charge is heated by the electric field applied to the channel region to form the interface. Writing to a level, or opening the semiconductor layer and the source region to make the drain region grounded or at a low potential, making the gate at a high potential, and causing a tunnel current from the drain region to charge the interface state. Or the semiconductor layer and the drain region are grounded or at a low potential to open the source region and the gate is electrically charged to a high potential. And storing the semi-fixed information by writing a charge to the interface state by a tunnel current from the semiconductor layer and the drain region, setting the drain region to ground or low potential, and connecting the source region and the gate to each other. The semi-fixed information is read by setting a high potential to identify the magnitude of the amount of current detected in the drain region, and the source region and the drain region are grounded or low potential or open, and the semiconductor layer is grounded or low potential. West,
The semi-fixed information is erased by applying a potential having a sign opposite to the high potential at the time of storage to the gate to erase the charges written in the interface state by a tunnel phenomenon. The non-volatile semiconductor memory device according to claim 1. 12. The ferroelectric layer, wherein the gate includes a ferroelectric layer, and the semiconductor layer and the drain region are grounded or at a low potential to open the source region so that the gate is at a high potential. The semi-fixed information is stored by polarizing the semi-fixed information.
10. The non-volatile semiconductor memory device according to any one of items 1 to 9. 13. The nonvolatile semiconductor memory device according to claim 1, further comprising an insulating layer provided below the semiconductor layer. 14. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the fixed information is stored when the source region and the drain region are formed. A method for manufacturing a characteristic nonvolatile semiconductor memory device. 15. Data storage, characterized in that the fixed information is stored when the source region and the drain region of the nonvolatile semiconductor memory device according to claim 1 are formed. Method.