JP3392122B2 - Hierarchical transmission digital demodulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical transmission digital demodulator for demodulating a digital modulated wave that is modulated by a plurality of modulation methods and time-multiplexed and transmitted.

[0002]

2. Description of the Related Art Hierarchical transmission method in which digital modulated waves transmitted by a plurality of modulation methods, for example, 8PSK modulated wave, QPSK modulated wave, BPSK modulated wave are combined every time and repeatedly transmitted every frame is known. Are known. In such a layered transmission system, since the BPSK modulation wave has a wide pull-in range and synchronization acquisition is easy, when the synchronization acquisition is performed, the BPSK modulation wave is received and the synchronization acquisition is performed. The respective signals of the input BPSK modulated wave, QPSK modulated wave, and 8PSK modulated wave are demodulated (also referred to as continuous demodulation) according to the input order.

[0003]

However, if the received C / N value deteriorates during continuous demodulation as described above, 8P
There is a problem that the reception state of the SK modulated wave deteriorates, carrier slip occurs in the section of the 8PSK modulated wave, the frame synchronization of the system is lost, and the receiving operation becomes unstable.

It is an object of the present invention to provide a layered transmission digital demodulator capable of stable synchronization acquisition and stable demodulation.

[0005]

A layered transmission digital demodulator according to the present invention comprises a BPSK, QPSK and 8PSK.
In a layered transmission digital demodulator for demodulating a transmission wave in which each of the modulated waves is time-multiplexed, the transmission wave is BPSK.
The modulated wave is multiplexed in at least the header section and the burst section inserted in the QPSK modulation section and the 8PSK modulation section, and the synchronization of the transmission wave is captured.
Before capturing, at least based on the demodulated output of BPSK modulated wave.
Based on the carrier regeneration,
After capturing synchronization, BPSK modulated wave and QPSK modulated wave
And 8PSK modulated wave demodulation output or 8PS
Based on either demodulation output excluding the K modulation wave,
It is characterized in that it is provided with a carrier reproducing means for performing rear reproduction .

According to the hierarchical transmission digital demodulator of the present invention , at least before the synchronization of the transmission wave is captured,
Carrier regeneration is performed based on the demodulated output of the BPSK modulated wave.
As a result, reliable carrier regeneration is performed. Career regeneration
Once the synchronization is captured by, the BPSK modulated wave and Q
Either demodulation output of PSK modulated wave and 8PSK modulated wave, or demodulation output excluding 8PSK modulated wave
The carrier is reproduced based on this . Therefore, the carrier can be surely reproduced.

Further, the layered transmission digital demodulator according to the present invention comprises means for detecting out-of- sync,
Before capturing the synchronization of the transmitted wave in response to the detection of disconnection
At least based on the demodulated output of the BPSK modulated wave
Carrier reproduction is performed .

According to the layered transmission digital demodulator of the present invention, the synchronization loss of the transmission wave is obtained after the synchronization of the transmission wave is acquired.
In response to the detection of the loss of synchronization by the detecting means, the transmission
At least BPSK before capturing transmission synchronization
Carrier regeneration is performed based on the demodulated output of the modulated wave.
Therefore, reliable carrier reproduction can be performed.

The layered transmission digital demodulator according to the present invention is a layered transmission digital demodulator for demodulating a transmission wave in which modulated waves of BPSK, QPSK, and 8PSK are time-multiplexed, wherein the transmitted wave is a BPSK modulated wave. Is multiplexed in at least the header section and the burst section inserted in the QPSK modulation section and the 8PSK modulation section, and is small before the synchronization of the transmission wave is captured.
Based on the demodulated output of at least the BPSK modulated wave
After playing live and once capturing synchronization by carrier regeneration
Is BPSK modulated wave, QPSK modulated wave and 8PSK modulated wave
Carrier reproduction based on each demodulation output
It is characterized by having a rear reproduction means .

According to the layered transmission digital demodulator of the present invention , at least the BPS is required until the synchronization is acquired.
Carrier reproduction is performed based on the demodulated output of the K modulated wave, and reliable carrier reproduction is performed. On the other hand, after acquisition synchronization, the carrier reproduction is performed on the basis of B PSK modulated wave and QPSK signal and 8PSK modulation waves respective demodulated output. Therefore, reliable carrier reproduction can be performed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A layered transmission digital demodulator according to the present invention will be described below with reference to embodiments.

FIG. 1 is a block diagram showing the structure of a hierarchical transmission digital demodulator according to an embodiment of the present invention.

Before describing the hierarchical transmission digital demodulator according to the embodiment of the present invention, the frame structure of the hierarchical transmission system will be described. FIG. 2A is a diagram showing an example of a frame structure in the hierarchical transmission system. One frame consists of one header 192 symbols and plural pairs of 203 symbols and 4 symbols are formed in 399.
It consists of 36 symbols.

More specifically, frame synchronization pattern (BPSK) 32 symbols, TMCC (Transmission and Multiplexing Configurati) for transmission multiplexing configuration identification.
on Control) pattern (BPSK) 128 symbols, superframe identification information pattern 32 symbols, main signal (TC8PSK) 203 symbols, burst symbol signal (BPSK) 4 symbols (denoted as BS in FIG. 2A), main Signal (TC8PSK) 203 symbols, burst symbol signal 4 symbols, ..., Main signal (QPSK) 203 symbols, burst symbol signal 4
The symbols, the main signal (QPSK) 203 symbols, and the burst symbol signal 4 symbols are formed in this order. Here, 8 frames are referred to as superframes, and the superframe identification information pattern is information for superframe identification. The 192 symbols from the frame synchronization pattern to the end of the superframe identification information pattern are also called a header.

Returning to the layered transmission digital demodulator according to the embodiment of the present invention, description will be made. The hierarchical transmission digital demodulator includes an arithmetic circuit 1, a numerically controlled oscillator 2 (NC
O), a raised cosine characteristic roll-off filter 3 including a digital filter, a frame synchronization timing circuit 4, a transmission mode determination circuit 5, a carrier reproduction phase error detection circuit 6, a carrier filter 7 including a low-pass digital filter, and a gain control circuit 8. , An automatic frequency control (AFC) circuit 9, a CNR measuring circuit 10 and a logic gate circuit 11.

As shown in FIG. 3, the AFC circuit 9 latches the outputs of the cumulative adder 91 and the cumulative adder 91, and outputs the latched output to the cumulative adder 91 for addition to add them.
It has and. As shown in FIG. 3, the numerically controlled oscillator 2 receives a latch output of a latch circuit 92 and outputs sine wave data 23a and 23b of opposite polarities, and a sine wave table 23 that receives a latch output of the latch circuit 92 and receives a cosine. Cosine wave table 24 for outputting wave data 24a, 24b, and sine wave data 23a, 23b and cosine wave data 2 of opposite polarities based on the output of the latch circuit 92.
4a and 24b are output to output a sine wave signal and a cosine wave signal having mutually opposite polarities that cooperate with the AFC circuit 9 to substantially form a reproduction carrier.

As shown in FIG. 3, the arithmetic circuit 1 includes a quasi-coherently detected I-axis baseband signal i and sine wave data 23.
The multiplier 1a that multiplies a by a, the multiplier 1b that multiplies the baseband signal i by the cosine wave data 24a, and the sine wave data 23b having the opposite polarity to the quasi-coherently detected Q-axis baseband signal q. A multiplier 1d for multiplying, a multiplier 1e for multiplying the baseband signal q and the cosine wave data 24b,
An adder 1c for adding the output of the multiplier 1b and the output of the multiplier 1d to output as a baseband signal I; and a multiplier 1
An adder 1f for adding the output of a and the output of the multiplier 1e and outputting as a baseband signal Q is provided, the baseband signals i and q are frequency-tuned, and the baseband signal I which is the frequency-tuned output is provided. , Q are sent to the roll-off filter 3, respectively.

The frame synchronization timing circuit 4 outputs the baseband signal ID output from the roll-off filter 3.
Upon receiving the QD, the TMCC pattern is sent to the transmission mode determination circuit 5. The transmission mode determination circuit 5 uses the hierarchical combination shown in FIG. 4 based on the result of decoding the TMCC pattern, and the 8PSK signal which is a high hierarchical signal (the demodulated output obtained by demodulating the 8PSK modulated wave is referred to as an 8PSK signal) and the low hierarchical signal A certain QPSK signal (a demodulated output obtained by demodulating a QPSK modulated wave is referred to as a QPSK signal), an 8PSK signal and a QP
The SK signal, the 8PSK signal, and the BPSK signal (the demodulated output obtained by demodulating the BPSK modulated wave is referred to as the BPSK signal) are sent to the frame synchronization timing circuit 4 as a 2-bit transmission mode signal.

The transmission mode signal is 8P as shown in FIG.
00 for SK signal, 0 for QPSK signal
1〃, 10〃 for 8PSK signal and QPSK signal,
It is "11" for 8PSK signal and BPSK signal.

The frame synchronization timing circuit 4 receives the baseband signals ID and QD, detects a synchronization pattern and outputs a frame synchronization signal FSYNC, and also receives a transmission mode signal to receive a high potential in the header section and burst symbol signal section. Of the signal A1 shown in FIG.
The signal A0 shown in FIG. 2C having a high potential in the K signal section is output.

The carrier reproduction phase error detection circuit 6 receives the baseband signals ID and QD and the signals A1 and A0, detects a phase error, and outputs a phase error voltage based on the phase error. More specifically, the carrier reproduction phase error detection circuit 6 has a demodulation ROM table shown in FIG. 5, a phase error table for the BPSK signal shown in FIG. 7, a phase error table for the QPSK signal shown in FIG. 8 and 8PSK shown in FIG. A phase error table for a signal is provided, a transmission mode is discriminated based on the signals A1 and A0, a phase error table is selected based on the discriminated transmission mode, and a phase is determined from the signal point arrangement of the baseband signals ID and QD. Then, the phase error voltage for the phase is calculated and transmitted.

In the carrier reproduction phase error detection circuit 6, for example, the transmission mode is a BPSK signal (signals A1 and A0).
When it is discriminated that is 〃 1, 0 〃), the reference position of the signal point of the BPSK signal is 0 (2π) radians and π radians, and the phase error table shown in FIG. 7 is selected and the phase is 3π. When the phase increases from / 2 radian or more to 0 (2π) radian, the phase is shown in FIG.
When the negative phase error voltage shown in (a) is in a decreasing direction from less than π / 2 radians to 0 (2π) radians, the positive phase error voltage shown in FIG. Is output and the phase is in the increasing direction from π / 2 radians to π radians, the phase is shown in FIG.
When the negative phase error voltage shown in is a phase in the decreasing direction from less than 3π / 2 radians to π radians, the positive phase error voltage shown in FIG. 7A is output with respect to the phase. In this case, the phase error voltage has a maximum value in the + direction or − when the phase is 3π / 2 radians and π / 2 radians.
It is the maximum value in the direction.

In the carrier reproduction phase error detection circuit 6, for example, the transmission mode is a QPSK signal (signals A1 and A0).
8 is selected and the reference position of the signal point of the QPSK signal is π / 4 radians, 3π / 4 radians, 5π /
4 radians and 7π / 4 radians. In this case, the phase error voltage is 0 (2π) radians, π / 2 radians, π radians, and 3π / 2 radians in the + direction maximum value or the − direction maximum value. Therefore, it is 1/2 of the maximum value in the case of the BPSK signal. Transmission mode is QPS
The description of the transmission of the phase error voltage when it is determined to be the K signal is omitted, but it will be easily understood from the description when the transmission mode is the BPSK signal.

The transmission mode is 8PSK signal (signal A1, A
When 0 is determined to be “0, 0”, the phase error table shown in FIG. 9 is selected, and the reference position of the signal point of the 8PSK signal is 0 (2π) radian, π / 4 radian, π
/ 2 radians, 3π / 4 radians, π radians, 5π /
4 radians, 3π / 2 radians and 7π / 4 radians, where the phase error voltage has a phase of π / 8
Radians, 3π / 8 radians, 5π / 8 radians, 7π
/ 8 radian, 9π / 8 radian, 11π / 8 radian, 13π / 8 radian, 15π / 8 radian is the maximum value in the + direction or the maximum value in the − direction, and is 1 with respect to the maximum value in the case of the BPSK signal. / 4. The description of the transmission of the phase error voltage when it is determined that the transmission mode is the 8PSK signal is omitted, but the transmission mode is BPS.
It will be readily understood from the description for the K signal.

The phase error voltage output from the carrier reproduction phase error detection circuit 6 is supplied to the carrier filter 7 which is a digital low pass filter to smooth the phase error voltage. In this case, the CNR code and the signals A1 and A0 output from the logic gate circuit 11 described later.
The filter operation is selectively performed by the carrier filter control signal (CRFLGP) according to the mode obtained by.

The output from the carrier filter 7 is supplied to the gain control circuit 8 and the gain control circuit 8 outputs a high C / N from a logic gate circuit 11 which will be described later.
Value, the gain control signal (G
6, when the gain control signal (GCONT) has a high potential, the output of the carrier filter 7 is controlled to a high gain by doubling the gain control signal (GCONT), and the gain control signal (GCONT) has a low potential. Sometimes, the output of the carrier filter 7 is controlled to a low gain such that it is output as it is, and the output from the gain control circuit 8 is adjusted to AF.
In order to add the scanning step frequency generated by the AFC circuit 9 to the voltage value that determines the scanning step frequency, the C circuit 9 is supplied to the cumulative adder 91 of the AFC circuit 9 and the oscillation frequency of the numerically controlled oscillator 2 Accelerate change.

The CNR measuring circuit 10 uses the baseband signal I
Receiving D and QD, the variance value of the signal point arrangement data obtained from the baseband signal ID and QD is obtained, the variance value is compared with a predetermined threshold value, and the number of occurrences of the variance value exceeding the threshold value in a predetermined unit time (DSMS) is counted, the C / N value is obtained by referring to the table shown in FIG. 10 obtained by the experiment based on the number of occurrences (DSMS), and is output as a 2-bit CNR code. This CNR code is, for example, as shown in FIG.
As shown in, when it is 9 dB or more, the high CNR is set to 0.
It is set as 0〃, and when it is 4 dB or more and less than 9 dB, it is set as 〃 01〃 as a medium CNR and when it is less than 4 dB, it is set as 〃 10〃 as a low CNR.

The logic gate circuit 11 receives the signals A1 and A0 output from the frame synchronization timing circuit 4 and the CNR code output from the CNR measuring circuit 10, and receives the carrier filter control signal (CRFLGP) and the gain control signal (GCONT). ) Is output.

More specifically, as shown in FIG. 12, the logic gate circuit 11 receives the CNR code and outputs a high C /
Upon receiving NAND gates 111, 112, 113 and signals A1, A0 which output signals based on N, medium C / N and low C / N, as shown in FIG. 2D, a BPSK signal, a burst symbol signal, or a QPSK signal. OR gate 114 that outputs a signal G that generates a high potential output when, a inverter 115 that generates a high potential output when C / N is high, and a medium C /
AND gate 116 for sending signal G when N, low C /
An AND gate 117 that sends out the signal A1 when N, an OR gate 118 that outputs a carrier filter control signal (CRFLGP) with the output of the inverter 115, the output of the AND gate 116 and the output of the AND gate 117 as inputs;
It is composed of a NAND gate 119 which outputs a high potential gain control signal (GCONT) at the time of high CNR or low CNR.

Therefore, from the logic gate circuit 11 to the high C
/ N, regardless of the identification mode (header period, burst symbol signal period, QPSK signal period, 8PSK
The high potential carrier filter control signal (CRFLGP) is output during any of the signal periods, and the medium C / N
, Header period, burst symbol signal period, Q
A high potential carrier filter control signal (CRFLGP) is output in any of the PSK signal period periods,
When the C / N is low, the high-potential carrier filter control signal (CRFLGP) is output in any of the header period and the burst symbol signal period. At other times, a low potential carrier filter control signal (CRFLG
P) is output. Further, the logic gate circuit 11 outputs a high potential gain control signal (GCONT) when the C / N is high or medium C / N, and outputs a low potential gain control signal (GCONT) when the C / N is low. It

High potential carrier filter control signal (CR
When FLGP) is output, the carrier filter 8 performs a filtering operation, and the phase error voltage is smoothed and output. Low potential carrier filter control signal (CRFL
When GP) is output, the carrier filter 8 stops the filter operation, and the output immediately before that is held and output. High potential gain control signal (GCON
When T) is output, the gain control circuit 8 doubles the output from the carrier filter 7 and sends it. When the low potential gain control signal (GCONT) is output, the gain control circuit 8 outputs the output from the carrier filter 7 as it is.

In the hierarchical transmission digital demodulator according to the present invention configured as described above, the baseband signals i and q are multiplied by the orthogonal reproduction carrier output from the numerically controlled oscillator 2 in the arithmetic circuit 1 to obtain the base. The band signals i and q are frequency-tuned, and the baseband signal ID,
The QD is sent to the frame synchronization timing circuit 4 via the roll-off filter 3. The TMCC pattern from the frame synchronization timing circuit 4 to the transmission mode determination circuit 5
And the TMCC pattern is decoded and the transmission mode signal is sent to the frame synchronization timing circuit 4.

A frame synchronization pattern is detected from the frame synchronization timing circuit 4 which receives the baseband signals ID, QD and the transmission mode signal to detect the frame synchronization signal FS.
YNC and signals A1 and A0 are transmitted. The frame synchronization signal FSYNC is sent to the gain control circuit 8,
The operation of the gain control circuit 8 is reset every time frame synchronization is detected. The signals A1 and A0 are sent to the carrier reproduction phase error detection circuit 6 and the logic gate circuit 11.

The baseband signals ID, QD and the signal A1,
In the carrier reproduction phase error detection circuit 6 that has received A0, the phase error table is selected based on the baseband signal and the signals A1 and A0, the phase error voltage is detected, and the detected phase error voltage is the carrier filter. 7 and is smoothed. On the other hand, baseband signal ID, QD
In response to the received CNR measurement circuit 10, the baseband signal I
The DSMS is counted based on the signal point arrangement of D and QD, the C / N value is obtained based on the counted DSMS, and CN
It is output in R code.

In the logic gate circuit 11 receiving the CNR code and the signals A1 and A0, high C / N, medium C / N, low C
/ N is detected, and when high C / N or medium C / N is detected, a gain control signal (GCONT) is sent to the gain control circuit 8, and the gain control circuit 8 controls to high loop gain. The phase error voltage output from the carrier filter 7 is doubled and sent out. When the logic gate circuit 11 detects low C / N, the gain control circuit (GCONT) controls the gain control circuit 8 to a low loop gain, and the phase error voltage output from the carrier filter 7 is sent as it is.

In response to the output from the gain control circuit 8, the AFC circuit 9 outputs to the output voltage from the gain control circuit 8 a voltage value which determines the scanning step frequency generated in the AFC circuit 9 in the cumulative adder 91. By cumulative addition, the oscillation frequency from the numerically controlled oscillator 2 is changed, the frequency scanning width is changed, and the reproduction carrier frequency is changed.

Next, the operation of the hierarchical transmission digital demodulator according to the present invention configured as above will be described with reference to FIG.
It will be described based on the flowchart shown in FIG.

When the power is turned on, frequency scanning is performed based on the operation of the AFC circuit 9 to change the reproduced carrier frequency (step S1), the gain control circuit 8 is controlled to a low loop gain, and the frame synchronization is performed. The process is repeated from step S1 until a pattern is detected and the frame synchronization pattern is detected (step S1).
2). When the frame synchronization pattern is detected, the burst demodulation mode is set and the BPSK signal and the burst symbol signal are demodulated (step S3). Step S
After 3, the received C / N is measured (step S4).

Following the measurement of the received C / N value in step S4, it is checked whether or not the frame synchronization signal FSYNC has been continuously detected a plurality of times (step S5).
If the frame synchronization signal FSYNC is not detected a plurality of times in succession in step S5, it is determined that the frame synchronization has not been established and the process is executed again from step S1. If the frame synchronization signal FSYNC is detected a plurality of times in succession in step S5, it is determined that the frame synchronization has been completed,
Following step 5, the transmission mode is decoded based on the decoded output of the TMCC pattern (step S6).

Following step S6, the received C / N is high C
/ N value is checked (step S
7). When it is determined that the C / N value is high in step S7, demodulation by layer, that is, continuous demodulation is performed following step S7 (step S8), and then the gain of the gain control circuit 8 is set to a high loop gain. (Step S9), and then step S4 is executed.

In steps S7 to S9, the high potential signal output from the inverter 115 is sent out as the carrier filter control signal (CRFLGP), the carrier filter 7 is controlled to the operating state, and the header section, burst symbol signal section, and QPSK are controlled. Signal section and 8PSK
The signal sections are sequentially demodulated in the order of input. In this case, the high potential signal from the NAND gate 119 is the gain control signal (GCO
NT) and the gain control circuit 8 is controlled to a high gain state.

In step S7, the received C / N is high C / N.
When it is determined that the value is not the N value, it is checked whether or not the value is the medium C / N value (step S10). When it is determined in step S10 that the C / N value is not the middle value, step S1
After 0, the process is executed again from step S2. When it is determined in step S10 that the C / N value is not the middle C / N value, the low potential signal is sent from the NAND gate 119 as the gain control signal (GCONT), and the gain control circuit 8 becomes low. Controlled to gain state.

Further, when the C / N value is low, the high potential signal output from the AND gate 117 is sent out as the carrier filter control signal (CRFLGP), the carrier filter 7 is controlled and output in the operating state, and the header section and The burst symbol signal section, that is, the BPSK signal section (including the burst symbol signal section) will be demodulated.

In step S10, the received C / N is medium C
When it is determined that the value is the / N value, it is checked after step S10 whether or not the low hierarchy signal is the QPSK signal (step S11). When it is determined in step S11 that the low hierarchy signal is the QPSK signal, the high potential signal output from the AND gate 116 is sent as the carrier filter control signal (CRFLGP), and the carrier filter 7 is controlled to the operating state and output. Then, the header section, the burst symbol signal section and the QPSK signal section, that is, the G timing section shown in FIG. 2D is sequentially demodulated (step S13).

Following step S13, the NAND gate 1
A high potential signal is sent from 19 as a gain control signal (GCONT), the gain control circuit 8 is controlled to a high gain state, and then step S4 is executed (step S14).

In step S11, the low hierarchy signal is QP.
When it is determined that the signal is not the SK signal, it is the 8PSK signal, the low potential carrier filter control signal (CRFLGP) is output from the OR gate 118, the filter operation of the carrier filter is stopped, and the NAND gate 11
A high-potential signal is sent from 9 as a gain control signal (GCONT), the gain control circuit 8 is controlled to a high gain state, and then the process is executed from step S4 (step S12).

As described above, according to the layered transmission digital demodulator according to the embodiment of the present invention, the carrier is reproduced based on the demodulation output of the period header section and the burst section until the synchronization acquisition is determined. Done,
Carriers are reliably reproduced with good capture performance. On the other hand, after the synchronization acquisition based on the reproduction of the carrier by the first means, the reproduction of the carrier based on the continuous demodulation output of each of the BPSK modulated wave, the QPSK modulated wave and the 8PSK modulated wave by the second means, or the third method. 8PSK by means
The carrier is reproduced based on the demodulated output excluding the modulated wave. Therefore, the carrier can be surely reproduced.

Further, according to the hierarchical transmission digital demodulator according to the embodiment of the present invention, B by the second means is used.
After synchronous acquisition by carrier reproduction based on continuous demodulation outputs of PSK modulated wave, QPSK modulated wave, and 8PSK modulated wave, or by synchronous reproduction by carrier reproduction based on demodulated output excluding 8PSK modulated wave by the third means At a later time, the first means is re-selected in response to the detection of out-of-sync. Therefore, the carrier can be surely reproduced.

Further, according to the layered transmission digital demodulator according to the embodiment of the present invention, the demodulated output is obtained by demodulating the modulated waves in the header section and the burst section by the first means until the synchronization acquisition. Carrier regeneration is performed based on this, and reliable carrier regeneration is performed. On the other hand, after the synchronization acquisition based on the carrier reproduction by the first means, the carrier reproduction based on the continuous demodulation output of each of the BPSK modulated wave, the QPSK modulated wave and the 8PSK modulated wave by the second means is performed. Therefore, the carrier can be surely reproduced.

[0050]

As described above, according to the layered transmission digital demodulator of the present invention, the carrier can be surely reproduced during the period until the frame synchronization is acquired, and the continuous demodulation output is used after the synchronization acquisition. Since the carrier is reproduced, the effect of preventing the occurrence of jitter can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a hierarchical transmission digital demodulation circuit according to an embodiment of the present invention.

FIG. 2 is a frame configuration diagram and waveform diagrams of signals A1 and A0 in the hierarchical transmission system according to the exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing configurations of an arithmetic circuit, a numerically controlled oscillator, and an AFC circuit in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 4 is a diagram showing the relationship between the transmission mode of the transmission mode determination circuit and the hierarchical combination in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a demodulation ROM table in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the loop gain and the logic of the gain control circuit in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram of a phase error table (for a BPSK signal) in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram of a phase error table (for a QPSK signal) in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 9 is an explanatory diagram of a phase error table (for an 8PSK signal) in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 10 is a characteristic diagram for explaining CNR measurement in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 11 is an output CNR of the CNR measurement circuit in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.
It is a figure which shows the relationship between a code and a C / N value.

FIG. 12 is a block diagram showing a configuration of a logic gate circuit in the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

FIG. 13 is a flowchart for explaining the operation of the hierarchical transmission digital demodulation circuit according to the embodiment of the present invention.

[Explanation of symbols]

1 arithmetic circuit 2 Numerically controlled oscillator (NCO) 3 roll-off filter 4 frame synchronization timing circuit 5 Transmission mode judgment circuit 6 Carrier reproduction phase error detection circuit 7 Carrier filter 8 Gain control circuit 9 AFC circuit 10 NCR measurement circuit 11 Logic gate circuit

Front page continuation (72) Inventor Shoji Matsuda 1-14-6 Dogenzaka, Shibuya-ku, Tokyo Kenwood Co., Ltd. (72) Inventor Hisakazu Kato 1-1-10 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Technical Research Institute (72) Inventor Hashimoto Specified 1-10-11 Kinuta, Setagaya-ku, Tokyo Broadcasting Technology Research Laboratories, Japan Broadcasting Corporation (56) Reference JP-A-10-215291 (JP, A) JP-A-5-308253 (JP, A) JP 8-97877 (JP, A) JP 11-163957 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27 / 38 H04L 7/00

Claims (3)

(57) [Claims] 1. A hierarchical transmission digital demodulator for demodulating a transmission wave in which modulated waves of BPSK, QPSK, and 8PSK are time-multiplexed, wherein the transmission wave includes at least a header section, a QPSK modulation section, and a BPSK modulated wave. The 8PSK modulation section is multiplexed with the inserted burst section, and is at least BPSK before the synchronization of the transmission wave is captured.
Carrier regeneration is performed based on the demodulated output of the modulated wave,
After capturing the synchronization by rear playback, change the BPSK
Demodulation of harmonic, QPSK modulated wave and 8PSK modulated wave respectively
Output or demodulation output excluding 8PSK modulated wave
Carrier regenerating means for regenerating carrier based on deviation
Hierarchical transmission digital demodulator characterized by comprising a. 2. The hierarchical transmission digital demodulator according to claim 1, further comprising means for detecting out-of-sync, and in response to the detection of out-of-sync, the synchronization of the transmitted wave is captured.
Demodulate at least BPSK modulated wave before capturing
A layered transmission digital demodulator characterized by performing carrier regeneration based on force . 3. A layered transmission digital demodulator for demodulating a transmission wave in which modulated waves of BPSK, QPSK, and 8PSK are time-multiplexed, wherein the transmission wave includes at least a header section, a QPSK modulation section, and a BPSK modulation section. The 8PSK modulation section is multiplexed with the inserted burst section, and is at least BPSK before the synchronization of the transmission wave is captured.
Carrier regeneration is performed based on the demodulated output of the modulated wave,
After capturing the synchronization by rear playback, change the BPSK
Demodulation of harmonic, QPSK modulated wave and 8PSK modulated wave respectively
Carrier regeneration means that performs carrier regeneration based on the output
A layered transmission digital demodulator characterized in that it is provided.