JP3333853B2 - Diode simulation circuit - Google Patents
Diode simulation circuitInfo
- Publication number
- JP3333853B2 JP3333853B2 JP5843095A JP5843095A JP3333853B2 JP 3333853 B2 JP3333853 B2 JP 3333853B2 JP 5843095 A JP5843095 A JP 5843095A JP 5843095 A JP5843095 A JP 5843095A JP 3333853 B2 JP3333853 B2 JP 3333853B2
- Authority
- JP
- Japan
- Prior art keywords
- diode
- effect transistor
- circuit
- simulation circuit
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、例えば半導体電力変
換回路が負荷機器として接続された電力系統の挙動を解
析するためのアナログシミュレータに関し、特に半導体
電力変換回路に使用されるダイオードの模擬回路に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog simulator for analyzing, for example, the behavior of a power system in which a semiconductor power conversion circuit is connected as a load device, and more particularly to a diode simulation circuit used in a semiconductor power conversion circuit. .
【０００２】[0002]
【従来の技術】半導体電力変換回路をアナログシミュレ
ータに組み込むときには、半導体電力変換回路に使用さ
れる電力用半導体デバイスを理想化して模擬する必要が
ある。例えば、電力用半導体デバイスが有する順方向電
圧降下を極力小さくし、この電力用半導体デバイスの動
作を市販されている標準化された電子部品を使用した回
路で模擬し、この模擬回路の動作電圧を数〜数１０ボル
トの電圧としてアナログシミュレータに組み込めること
が望まれている。2. Description of the Related Art When a semiconductor power conversion circuit is incorporated in an analog simulator, it is necessary to ideally simulate a power semiconductor device used in the semiconductor power conversion circuit. For example, the forward voltage drop of the power semiconductor device is minimized, and the operation of the power semiconductor device is simulated by a circuit using standardized electronic components that are commercially available. It is desired that the voltage can be incorporated into an analog simulator as a voltage of up to several tens of volts.
【０００３】図２は、この種のダイオードの模擬回路の
従来例を示す回路構成図である。図２において、１は交
流電源、２はダイオードの模擬回路、３は負荷である。
ダイオードの模擬回路２は、演算増幅器４、主ダイオー
ド５、補助ダイオード６演算増幅器４の正側直流電源
７、演算増幅器４の負側直流電源８から構成されてい
る。FIG. 2 is a circuit diagram showing a conventional example of this kind of diode simulation circuit. In FIG. 2, 1 is an AC power supply, 2 is a simulation circuit of a diode, and 3 is a load.
The diode simulation circuit 2 includes an operational amplifier 4, a main diode 5, an auxiliary diode 6, a positive DC power supply 7 of the operational amplifier 4, and a negative DC power supply 8 of the operational amplifier 4.
【０００４】ダイオードの模擬回路２の動作を以下に説
明する。交流電源１の発生電圧が正のときは、演算増幅
器４の出力も正となって主ダイオード５が導通状態とな
り、主ダイオード５のカソードから演算増幅器４へのフ
ィードバックにより電圧フォロアの動作をし、交流電源
１の電圧がそのまま負荷３に加えられる。また交流電源
１の発生電圧が負のときは、演算増幅器４の出力も負と
なって主ダイオード５が不導通状態となり、交流電源１
の負の電圧に無関係に負荷３に加わる電圧は零となる。
このとき演算増幅器４の出力は補助ダイオード６により
ほぼ零となる。The operation of the diode simulation circuit 2 will be described below. When the voltage generated by the AC power supply 1 is positive, the output of the operational amplifier 4 is also positive and the main diode 5 is turned on, and a voltage follower operates by feedback from the cathode of the main diode 5 to the operational amplifier 4, The voltage of the AC power supply 1 is applied to the load 3 as it is. When the voltage generated by the AC power supply 1 is negative, the output of the operational amplifier 4 is also negative, and the main diode 5 is turned off.
The voltage applied to the load 3 becomes zero regardless of the negative voltage.
At this time, the output of the operational amplifier 4 becomes almost zero by the auxiliary diode 6.
【０００５】[0005]
【発明が解決しようとする課題】上記従来のダイオード
の模擬回路によると、演算増幅器４が有するスルーレー
ト特性、周波数特性により模擬回路を高速動作させると
きには応答遅れが生ずるという問題があった。また、交
流電源１の瞬時値が、正側直流電源７または負側直流電
源８の電圧を越えるときには模擬回路が異常動作をする
恐れがあった。According to the conventional diode simulation circuit described above, there is a problem that a response delay occurs when the simulation circuit is operated at high speed due to the slew rate characteristic and frequency characteristic of the operational amplifier 4. Further, when the instantaneous value of the AC power supply 1 exceeds the voltage of the positive DC power supply 7 or the negative DC power supply 8, the simulation circuit may operate abnormally.
【０００６】この発明の目的は、上記問題点を解決する
ダイオードの模擬回路を提供することにある。An object of the present invention is to provide a simulation circuit for a diode which solves the above-mentioned problems.
【０００７】[0007]
【課題を解決するための手段】この発明は、アナログシ
ミュレータに使用されるダイオードの模擬回路におい
て、ダイオードを内蔵するＮチャンネルＭＯＳ形電界効
果トランジスタと、前記電界効果トランジスタのソース
の電位を基準電位とし、ドレイン−ソース間の電圧を増
幅した値が基準電位に対して負のときは該電界効果トラ
ンジスタのゲートにオン信号を与え、前記増幅した値が
基準電位に対して正のときは前記電界効果トランジスタ
のゲートにオフ信号を与える制御回路とを備える。According to the present invention, there is provided a diode simulating circuit used in an analog simulator, wherein an N-channel MOS field effect transistor having a built-in diode and a source potential of the field effect transistor are used as reference potentials. When the value obtained by amplifying the voltage between the drain and the source is negative with respect to the reference potential, an ON signal is supplied to the gate of the field effect transistor. When the amplified value is positive with respect to the reference potential, the field effect transistor is used. A control circuit for providing an off signal to the gate of the transistor.
【０００８】[0008]
【作用】この発明は、ダイオードを内蔵するＮチャンネ
ルＭＯＳ形電界効果トランジスタのゲート−ソース間電
圧ＶGSを正にバイアスすることにより、該電界効果トラ
ンジスタの電流は両方向同じように流れ、通常のダイオ
ードより順方向電圧降下を小さくできることを作用とし
ている。According to the present invention, by biasing the gate-source voltage V GS of an N-channel MOS field effect transistor having a built-in diode positively, the current of the field effect transistor flows in the same direction in both directions. The effect is that the forward voltage drop can be further reduced.
【０００９】また前記電界効果トランジスタは、順方向
電圧降下を小さくでき、高速のスイッチング特性を有
し、高耐圧の特性も備えている。The field effect transistor can reduce the forward voltage drop, has high-speed switching characteristics, and has high withstand voltage characteristics.
【００１０】[0010]
【実施例】図１は、この発明の実施例を示すダイオード
の模擬回路の回路構成図である。図１において、１は交
流電源、２０はダイオードの模擬回路、３は負荷であ
り、ダイオードの模擬回路２０は、ダイオードを内蔵す
るＮチャンネルＭＯＳ形電界効果トランジスタ２１（以
下、単に電界効果トランジスタ２１と称する）、増幅器
２２、コンパレータ２３、インバータ素子２４、増幅器
２２とコンパレータ２３の正側直流電源２５、増幅器２
２とコンパレータ２３の負側直流電源２６と図示しない
インバータ素子２４の電源とから構成されている。FIG. 1 is a circuit diagram of a diode simulation circuit showing an embodiment of the present invention. In FIG. 1, 1 is an AC power supply, 20 is a simulated diode circuit, and 3 is a load. The simulated diode circuit 20 is an N-channel MOS type field effect transistor 21 having a built-in diode (hereinafter simply referred to as a field effect transistor 21). , The amplifier 22, the comparator 23, the inverter element 24, the positive side DC power supply 25 of the amplifier 22 and the comparator 23, the amplifier 2
2, a negative DC power source 26 of the comparator 23, and a power source of the inverter element 24 (not shown).
【００１１】ダイオードの模擬回路２０の動作を以下に
説明する。交流電源１の発生電圧が正のときは、電界効
果トランジスタ２１のソースの電位を基準電位として、
ドレイン−ソース間の微小電位差を増幅器２２で増幅
し、この増幅した値が基準電位に対して負となり、その
結果コンパレータ２３の出力はロウレベルとなりインバ
ータ素子２４の出力はハイレベルとなって、電界効果ト
ランジスタ２１のゲート−ソース間電圧ＶGSを正にバイ
アスすることとなり、電界効果トランジスタ２１は導通
状態となり、このため、内蔵ダイオードの順方向電圧降
下が小さくなる。The operation of the diode simulation circuit 20 will be described below. When the voltage generated by the AC power supply 1 is positive, the potential of the source of the field-effect transistor 21 is used as a reference potential,
The minute potential difference between the drain and the source is amplified by the amplifier 22, and the amplified value becomes negative with respect to the reference potential. As a result, the output of the comparator 23 becomes low level, and the output of the inverter element 24 becomes high level. The gate-source voltage V GS of the transistor 21 is positively biased, and the field-effect transistor 21 is turned on, thereby reducing the forward voltage drop of the built-in diode.
【００１２】また、交流電源１の発生電圧が負のとき
は、同様に電界効果トランジスタ２１のドレイン−ソー
ス間の微小電位差を増幅器２２で増幅し、この増幅した
値が基準電位に対して正となり、その結果コンパレータ
２３の出力はハイレベルとなりインバータ素子２４の出
力はロウレベルとなって、電界効果トランジスタ２１は
不導通となる。When the voltage generated by the AC power supply 1 is negative, a small potential difference between the drain and source of the field effect transistor 21 is similarly amplified by the amplifier 22, and the amplified value becomes positive with respect to the reference potential. As a result, the output of the comparator 23 becomes high level, the output of the inverter element 24 becomes low level, and the field effect transistor 21 becomes non-conductive.
【００１３】例えば、この模擬回路６組を図示のＡをダ
イオードのアノード、図示のＫを該ダイオードのカソー
ド端子として３相ブリッジ結線することにより、３相全
波整流回路が模擬できる。For example, a three-phase full-wave rectifier circuit can be simulated by connecting the six sets of the simulating circuits to three-phase bridges with A shown in the figure as the anode of the diode and K shown in the figure as the cathode terminal of the diode.
【００１４】[0014]
【発明の効果】この発明によれば、ダイオードを内蔵す
るＮチャンネルＭＯＳ形電界効果トランジスタは、順方
向電圧降下を小さくでき、高速のスイッチング特性を有
し、高耐圧の特性も備えているので、アナログシミュレ
ータの動作電圧を広い範囲で設定でき、さらに順方向電
圧降下を小さくしたいときには、前記電界効果トランジ
スタを並列接続すればよく、また回路電流を大きくとる
ことも容易である。According to the present invention, an N-channel MOS field effect transistor having a built-in diode can reduce the forward voltage drop, has a high-speed switching characteristic, and has a high breakdown voltage characteristic. The operating voltage of the analog simulator can be set in a wide range, and when it is desired to further reduce the forward voltage drop, the field effect transistors may be connected in parallel, and it is easy to increase the circuit current.
【図１】この発明の実施例を示すダイオードの模擬回路
の回路構成図FIG. 1 is a circuit configuration diagram of a simulated diode circuit showing an embodiment of the present invention.
【図２】従来例を示すダイオードの模擬回路の回路構成
図FIG. 2 is a circuit configuration diagram of a simulation circuit of a diode showing a conventional example.
１ 交流電源 ２ ダイオードの模擬回路 ３ 負荷 ４ 演算増幅器 ５ 主ダイオード ６ 補助ダイオード ７ 正側直流電源 ８ 負側直流電源 ２０ ダイオードの模擬回路 ２１ ダイオード内蔵ＮチャンネルＭＯＳ形電界効
果トランジスタ ２２ 増幅器 ２３ コンパレータ ２４ インバータ素子 ２５ 正側直流電源 ２６ 負側直流電源REFERENCE SIGNS LIST 1 AC power supply 2 Diode simulation circuit 3 Load 4 Operational amplifier 5 Main diode 6 Auxiliary diode 7 Positive DC power supply 8 Negative DC power supply 20 Diode simulation circuit 21 N-channel MOS field effect transistor with built-in diode 22 Amplifier 23 Comparator 24 Inverter Element 25 Positive DC power supply 26 Negative DC power supply
Claims (1)
ードの模擬回路において、 ダイオードを内蔵するＮチャンネルＭＯＳ形電界効果ト
ランジスタと、 前記電界効果トランジスタのソースの電位を基準電位と
し、ドレイン−ソース間の電圧を増幅した値が基準電位
に対して負のときは該電界効果トランジスタのゲートに
オン信号を与え、 前記増幅した値が基準電位に対して正のときは前記電界
効果トランジスタのゲートにオフ信号を与える制御回路
とを備えたことを特徴とするダイオードの模擬回路。1. A diode simulation circuit used in an analog simulator, comprising: an N-channel MOS field-effect transistor having a built-in diode; a source potential of the field-effect transistor as a reference potential; When the amplified value is negative with respect to the reference potential, an on signal is given to the gate of the field effect transistor. When the amplified value is positive with respect to the reference potential, an off signal is given to the gate of the field effect transistor. A simulation circuit for a diode, comprising: a control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5843095A JP3333853B2 (en) | 1995-03-17 | 1995-03-17 | Diode simulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5843095A JP3333853B2 (en) | 1995-03-17 | 1995-03-17 | Diode simulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08254561A JPH08254561A (en) | 1996-10-01 |
| JP3333853B2 true JP3333853B2 (en) | 2002-10-15 |
Family
ID=13084174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5843095A Expired - Lifetime JP3333853B2 (en) | 1995-03-17 | 1995-03-17 | Diode simulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3333853B2 (en) |
-
1995
- 1995-03-17 JP JP5843095A patent/JP3333853B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08254561A (en) | 1996-10-01 |
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