JP3330877B2 - Superposition modulation device, superposition demodulation device, data relay device and liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superposition modulator for compressing and modulating a serial bit stream in the form of an amplitude signal. Further, the present invention relates to a superposition demodulation device for demodulating a superposition-modulated amplitude signal. Further, the present invention relates to a data repeater using superimposition modulation and demodulation, and a liquid crystal display device using the repeater.

[0002]

2. Description of the Related Art Since voice information began to be transmitted, text information transmitted through a transmission medium (Text Informatio).
n) and the amount of video information (Video Information) are larger than those of audio information. In particular, the amount of video information is increasing in order to satisfy the user's desire for high-quality video. At the same time, recent information is transmitted at high speed so that users can use it at an appropriate time. As a result, the frequency band in which information is occupied only increases with the amount of information.

In practice, as shown in FIG. 1, a liquid crystal display (Li
In the case of a computer system using a quid Crystal Display (hereinafter referred to as "LCD"), a video card (12) in the computer body (10)
The video data transmitted from the LCD to the LCD (20) has a higher frequency as the resolution mode of the image becomes higher, that is, as the number of pixels increases.
To explain this in detail, the image resolution mode is
By replacing the VGA mode with the XGA or SXGA mode, a liquid crystal panel (Liquid Crystal Panel) (2
In the case of 2), since more pixels and the like are included, the amount of video data for one image increases. Thereby, the video card (1) of the computer body (10) is
The frequency of video data transmitted from 2) to the LCD (20) increases. As the frequency of the video data increases, electromagnetic interference (hereinafter, referred to as "EMI") in the LCD (20) becomes severe, and a timing error often occurs. At the same time, LCDs are capable of responding to high-frequency signals.
Circuit (hereinafter "D-IC") (24) and controller (26) must be used.

In order to lower the response frequency of the D-IC or the like (24), there has been proposed a method of duplicating the bus line between the D-IC or the like (24) and the controller (26) as shown in FIG. Has been adopted. In this case, a main bus line (11) consisting of 18 bit lines is connected between the video card (12) and the controller (26), and the controller (26) and the D-IC are connected.
And the like (26), the first and second sub-bus lines (21, 23) each composed of 18 bit lines or the like.
Will be connected. First sub bus line (21)
Is commonly connected to the odd-numbered D-ICs (24A), and the second
The sub bus line (23) is commonly connected to the even-numbered D-ICs (24B). A main clock line (13) is connected between the video card (12) and the controller (26), and a sub clock line (25) is connected between the controller (26) and the D-IC or the like (24). It is connected. Controller (2
In 6), 18 bits of video data are input from the main bus line (11) every half cycle of the data clock (DCLK) on the main clock line (13).
The odd-numbered D-ICs (24A) pass through the sub clock line (25) from the controller (26), and 18 bits from the first sub bus line (21) at every rising edge of the applied data clock (DCLK). On the other hand, the even-numbered D-IC (24B) receives 18-bit data from the second sub bus line (23) every falling edge of the data clock (DCLK) on the sub clock line (25). Input video data. With such a double bus line, the response frequency of the D-IC or the like (24) is lowered.

[0005]

However, in such a double bus line structure, the number of signal lines is increased.
Not only is the design of the LCD limited, but also the manufacturing costs of the LCD are increased. Further, in the LCD having the dual bus line structure, the frequency of the video data supplied to the controller and the D-IC is still high, so that the EMI and the timing error do not decrease. Therefore, a modulation technique suitable for transmitting a large amount of data at a low frequency signal is required, and a relay technique suitable for transmitting a large amount of data at a low frequency is also required.

Accordingly, it is an object of the present invention to provide a superposition modulation apparatus suitable for modulating high frequency data into a low frequency signal.

Another object of the present invention is to provide a superimposition demodulation device suitable for demodulating high frequency data from a low frequency signal modulated by the modulation device.

Another object of the present invention is to provide a data relay device suitable for relaying high-frequency data to low-frequency data.

Another object of the present invention is to provide a liquid crystal display device suitable for inputting high-frequency video data from a computer main body in the form of a low-frequency signal.

[0010]

In order to achieve the above object, a superposition modulation apparatus according to the present invention comprises: an input means for inputting a data bit stream synchronized with a data clock;
Key clock generating means for generating a key clock having a frequency lower than the data clock, data arranging means for arranging at least two bits or more of data in a data bit stream in parallel by the key clock, and at least two or more bits of enumerated data To an analog signal.

The superimposition demodulator according to the present invention has at least two
Input means for inputting one analog signal in which data of at least bits are compressed and a key clock synchronized with the signal, quantizing means for quantizing the analog signal from the input means, and a quantized analog signal Encoding means for restoring the parallel data of at least two bits or more, and reverse sorting means for aligning the parallel data of at least two bits or more in one row by the key clock.

A data relay device according to the present invention comprises a superposition modulation means for superimposing at least two bits of a data bit stream from a data source and modulating the data bit stream into an analog signal, and at least an analog signal from the superposition modulation means installed in a data terminal. And superimposing and demodulating means for demodulating a data bit stream by expanding the data into two or more bits.

The liquid crystal display device according to the present invention has at least two components.
A D-IC or the like for dividing and driving the liquid crystal panel with video data of bits or more, and signal inputting means for externally inputting one analog signal in which a data bit stream is superimposed and modulated by at least 2 bits or more, A superimposition demodulation means is provided which demodulates a data bit stream by expanding an analog signal from the signal introducing means into data of at least 2 bits and supplies the bit stream to the D-IC or the like.

With the above configuration, in the superposition modulator of the present invention, two-bit data adjacent on the time axis is superimposed in the form of an amplitude signal, so that the frequency of transmission data is lowered and the data is consumed in data transmission. Power is close to 1/4
To become smaller. This reduces EMI in the superimposed modulated signal generated by the superimposed modulator according to the present invention. Also, in the repeater according to the present invention using a superimposition modulator and a superimposition demodulator, at least two bits or more data on the time axis is transmitted in a state of being superimposed in the form of an amplitude signal, so that the transmission frequency band is reduced. In addition, power consumption is reduced. This makes the data transmitted by the repeater according to the invention almost immune to EMI. Similarly, in the LCD according to the present invention using the above-described repeater, the data transmission frequency band is reduced, and the power consumed for data transmission is reduced. As a result, the LCD according to the present invention can minimize EMI effects. In addition to this, in the LCD according to the present invention, the data transmission line (3)
6) When the key transmission line is commonly connected to the D-IC, the video data transmitted from the video card to the D-IC
Not only the EMI effect is minimized, but also the wiring structure is simplified.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 2, there is shown a computer system to which a superposition modulation type repeater according to an embodiment of the present invention is applied. This computer system is connected to a computer main body (30) containing a video card (32) and a superimposed modulator (34), and to the superimposed modulator (34).
An LCD or the like (40) is provided. The video card (32) has a function of converting information including text and video into video data so that the information is displayed as an image on the LCD (40). The video data generated by the video card (32) includes red (Red, hereinafter referred to as "R"), green (Green, hereinafter referred to as "G"), and blue (Blue, hereinafter "B") for each pixel constituting the screen. ″) Data. Each of these R, G, B data and the like has a length of 6 bits, so that the video data has a length of 18 bits for each pixel. Such video data (V
D) is supplied to the superimposition modulator (34) via the first bus line (31) formed of 18 bit lines and the like. At this time, the video data (VD) is a data clock (DCLK) supplied from the video card (32) to the superimposing modulator (34) via the first clock line (33).
Will be transmitted in time. Superposition modulator (34)
Is the data clock (DCL) from the clock line (33).
K) is divided to generate at least one or more divided clocks. At least one or more frequency-divided clocks have a frequency that changes by 1 / 2n times the data clock (DCLK). The superposition modulator (34) is connected to the first bus line (3
Video streams sequentially input through the bit lines are superimposed and modulated using at least one or more frequency-divided clocks for each of the bit lines and the like constituting 1). To explain this in detail, the superimposition modulator (34) is provided for every half cycle of the clock divided by two,
That is, the data on the time axis of at least 2 bits per data clock (DCLK) cycle, that is, the multi-bit data including the current bit data and at least one bit data is converted into an amplitude so that the superimposed modulation signal is converted. Will occur. The amplitude of the superimposed modulation signal changes in accordance with the logic value of the multi-bit date for each half cycle of the clock divided by two. By such superimposition modulation, the superimposition modulator (34) generates 18 superimposition modulation signals (hereinafter, referred to as "superimposition modulation data"). Will be provided as. The superimposed modulated data generated by the superimposed modulator (34) is transmitted through a data transmission line (36) formed of 18 bit transmission lines or the like. The superimposition modulator (34) demodulates the superimposed modulation signal of the clock divided by 2, but is used.
Key transmission line as key clock (KCLK) "(38)
To be transmitted through. This key clock (KCL
K) indicates the data period of the superimposed modulation signal. In order to generate the eighteen superimposed modulation signals, the superimposition modulator (34) is connected to the first bus line (31).
, And 18 superimposed modulation cells connected to each of the 18 bit lines and the like.

The LCD (40) shares a key clock (KCLK) from a key transmission line (38) with a number of D-ICs (44) for dividing and driving pixels on a liquid crystal panel (42). It is composed of an input superimposition demodulator (46) and a controller (48). The superimposition demodulator (46) is connected to the data transmission line (3).
From 6), superimposed modulation data including 18 superimposed modulation signals and the like is input. In order to demodulate such superimposed modulation data, the superimposition demodulator (46) includes 18 superimposition demodulation cells and the like (not shown) that respond individually to the 18 superimposition modulation signals constituting the superimposition modulation data. Each of the superimposed demodulation cells and the like quantizes the superimposed modulation signal, encodes the quantized superimposed modulation signal into a multi-bit signal of at least two bits, and uses the key clock (KCLK) to convert the multi-bit signal. A video bit stream is generated by listing the bit stream format. The demodulated video bit stream has a frequency at least twice as high as the superimposed modulation signal and a frequency corresponding to twice the key clock frequency. By collecting the 18 video bit streams demodulated by the 18 superimposed demodulation cells and the like, 1
8-bit data is configured. The high-frequency video data thus demodulated is commonly supplied to a number of D-ICs (44) via a second bus line (41) formed of 18 bit lines or the like. . On the other hand, the key clock (KCLK) is transmitted from the key transmission line (38).
A controller (48) for inputting a key clock (KCLK) generates a control signal (CTLS) for sequentially inputting a number of D-ICs (44) using a key clock (KCLK). Become. This control signal (CTLS) is commonly supplied to a number of D-ICs (44) via the control line (43). A large number of D-ICs (44) sequentially input video data from the second bus (41) by a constant amount according to a control signal (CTLS) from a control line (43). One line of video data distributed and input by a fixed amount to each of a large number of D-ICs (44) is simultaneously supplied to the liquid crystal panel (42) to drive one line of pixels and the like. Such an operation of the D-IC or the like (44) and the liquid crystal panel (42) is repeated by the number of pixel lines of the liquid crystal panel (42), whereby one image is displayed.

As described above, at least two bits of data arranged on the time axis are superimposed in the form of an amplitude signal by the superimposition modulator (34), so that the frequency of the video data transmitted through the data transmission line (36) is increased. Is at least 1 /
The power required for transmitting the video data is reduced in conjunction with the reduction to 2 or less. As a result, EMI in video data is reduced.

Further, the superimposition demodulator (46) is composed of a large number of D-ICs.
(44), the data transmission line (36) and the key transmission line (38) have a large number of D-channels.
When commonly connected to an IC or the like (44), EMI generated in video data transmitted from the video card (32) to many D-ICs or the like (44) is minimized. Needless to say, the wiring structure between the controller (48) and the D-IC is simplified.

FIG. 3 shows in detail the superimposed modulation cell included in the superimposed modulator (34) in FIG. As in FIG.
In the superimposed modulation cell, the first flip-flop (5) responds to the data clock (DCLK) from the clock line (33).
0) and second and third flip-flops (52, 54) that are commonly supplied with a video bit stream (VBS) from a bit line (33). The first to third flip-flops (50, 52, 54) are initialized by a reset signal (RS) applied to their own clear terminal or the like (CLR) at the time of initial startup of the computer system. A malfunction that may occur at an early stage is prevented. The first flip-flop (50) changes the logic state on its output terminal (Q) to High every falling edge of the data clock (DCLK) as shown in FIG.
The data clock (DCLK) applied to its own clock terminal (CLK) is divided by two by inverting the data clock (Low) or the reverse. The signal divided by 2 by the first flip-flop (50) is used as a key clock (KCLK), so that the key transmission line (3) is used.
8), it is supplied to the clock terminal and the like (CLK) of the second and third flip-flops (52, 54).

The second and third flip-flops (52, 5
4) In response to the key clock (KCLK), the bit data of the video bit stream (VBS) from the bit line (31A) is superimposed on the preceding bit data, the succeeding bit data and the half cycle of the key clock (KCLK). Let it. To this end, the second flip-flop (52) outputs a video bit stream (VBS) from the bit line (31A) at each rising edge of the key clock (KCLK) to its own output terminal (Q).
On the other hand, the third flip-flop (54) transmits the bit line (3) every falling edge of the key clock (KCLK).
The video bit stream (VBS) from 1A) is transmitted to its own output terminal (Q). As a result, the odd-numbered video bit data (Dn) is output from the output terminal (Q) of the second flip-flop (52), and the even-numbered video bit data is output from the output terminal (Q) of the third flip-flop (54). (Dn + 1) is continuously output. The odd-numbered video bit data (Dn) and the even-numbered video bit data (Dn + 1) have the same frequency as the key clock (KCLK), but have a 180 ° phase difference with each other.

The superimposed modulation cell is connected to the output terminal (Q) of the second flip-flop (52) and the bit transmission line (36).
A), a first resistor (R1) connected between them, an output terminal (Q) of a third flip-flop (54) and a bit transmission line (3).
6A) and a second resistor (R2) connected between them. First
The resistor (R1) is an output terminal of the second flip-flop (52).
The voltage signal from (Q) is reduced to 1/3, and the dropped voltage signal is transmitted to the bit transmission line (36A). The second resistor (R2) drops the voltage signal from the output terminal (Q) of the third flip-flop (54) to 2/3, and converts the dropped voltage signal to a bit transmission line (36).
A). Accordingly, a superimposed modulation signal (TFMS) having a combined voltage of the voltage signals dropped by the first and second resistors (R1, R2) appears on the bit transmission line (36A). This superimposed modulation signal (TF
MS) is the data clock (DCLK) every half cycle of the key clock (KCLK) according to the logic value of the 2-bit data stored in the second and third flip-flops (52, 54).
Has an amplitude that is changed every cycle. The superimposed modulation signal (TFMS) has a minimum average voltage and a video
Of the stream (VBS)
This allows you to use a video bitstream (VBS)
Power consumption can be reduced to a value close to 1/4 .
As a result, the first and second resistors (R1, R2) perform a function of converting 2-bit parallel data into an amplitude signal, and therefore, the first and second resistors (R1, R2) become 2:
It is set to have a resistance value of 1.

FIG. 5 is a circuit diagram showing in detail the superimposition demodulation cell included in the superimposition demodulator (46) in FIG.
6 is an operation timing diagram for each part of the superimposition demodulation cell shown in FIG. In FIG. 5, superimposed demodulation cells are first to third level detectors (60, 62, 64) commonly connected to a bit transmission line (36A), and these level detectors (60, 62, 64). And an encoding unit (66) for encoding the output signal or the like. First to third
The level detectors (60, 62, 64) detect the voltage level (ie, amplitude) of the superimposed modulation signal (TFMS) from the bit transmission line (36A) as shown in FIG. First
When the superimposed modulation signal (TFMS) is equal to or higher than a first predetermined voltage level (for example, Vh / 3), the level detector (60) has a low logic first amplitude detection signal (ADI), a second level detector ( 62) is a low logic second signal when the superimposed modulation signal (TFMS) is equal to or higher than a second predetermined voltage level (for example, Vh / 2).
The amplitude detection signal (AD2), and the third level detector (64) outputs a low logic third amplitude detection signal when the superimposed modulation signal (TFMS) is equal to or higher than a third predetermined voltage level (for example, Vh). (AD3) respectively. These first to third level detection signals (AD1 to AD3) indicate the amplitude value (that is, the quantized value) of the superimposed modulation signal (TFMS). As a result, the first to third level detectors (60, 62, 64) perform the function of quantizing the superimposed modulation signal (TFMS). The encoding unit (66) encodes the amplitude values specified by the first to third amplitude detection signals (AD1 to AD3) from the first to third level detectors (60, 62, 64) into 2-bit data. Become like The lower bit data and the upper bit data encoded by the encoding unit (66) are used for odd-numbered bit data (Dn) and even-numbered bit data (Dn + 1). The even-numbered bit data (Dn + 1) has a second level detector (6
While the second level detection signal (AD2) generated in 2) is used, the odd-numbered bit data (Dn) is the first to third bits.
Since the level detection signals (AD1 to AD3) are in a logical combination, they are generated. To this end, the encoding unit (66) includes first and second AND gates (AND1, AND2) and one NOT logic buffer (NB1).

A key transmission line (3
4th to 7th flip-flops (68, 70, 72, 7) commonly responding to the key clock (KCLK) from 8).
4) is included. The fourth and fifth flip-flops (68, 70) synchronize the encoded odd-numbered and even-numbered bit data (Dn, Dn + 1) with the key clock (KCLK) by the encoding unit (66). . More specifically, the fourth flip-flop (68) is connected to the second AND gate (AND) every rising edge of the key clock (KCLK).
The odd-numbered bit data (Dn) from 2) is output to its own output terminal.
The odd-numbered bit data (SDn) transmitted and synchronized to the slave (Q) is input to a sixth flip-flop (72).
(D) . Similarly, the fifth flip-flop (70) also outputs the second level detection signal from the second level detector (62) every rising edge of the key clock (KCLK).
By transmitting (AD2) to its own output terminal (Q) , the synchronized even-numbered bit data (SDn + 1) is supplied to the input terminal (D) of the seventh flip-flop (74). Sixth
And the seventh flip-flops (72, 74) control the 2-bit data (SDn) so that the synchronized odd-numbered bit data (SDn) and the synchronized even-numbered bit data (SDn + 1) have a phase difference of about 180 °. , SDn + 1). To this end, the sixth flip-flop (72) receives the synchronized odd-numbered bit data (SDn) from the fourth flip-flop (68) every falling edge of the key clock (KCLK) and outputs it to its own output terminal (Q). Transmitted to
Then, the seventh flip-flop (74) is driven by the key clock (KCL).
The synchronized even-numbered bit data (SDn + 1) from the fifth flip-flop (70 ) is transmitted to its own output terminal (Q) every rising edge of K).

The superimposed demodulation cell is a key transmission line (3
8) The third and fourth AND gates (AND3, AND4) for commonly inputting the key clock (KCLK) from (8) and an OR gate (OR1) connected to these AND gates (AND3, AND4). I do. Third and fourth AND gates (AND
3, AND4) are the sixth and seventh flip-flops (72,
74), the cycle of the odd-numbered bit data and the even-numbered bit data is shortened to a half cycle of the key clock (KCLK).
K) twice as high. More specifically, the third AND gate (AND3) demodulates the odd-numbered video bit data (DDn) by performing an AND operation on the odd-numbered bit data from the sixth flip-flop (72) and the inverted key clock. And the fourth AND gate (AND
4) demodulates the even-numbered video bit data (DDn + 1) by ANDing the even-numbered bit data from the seventh flip-flop (74) with the key clock (KCLK). The odd-numbered video bit data (DDn) demodulated by the third AND gate (AND3) and the fourth AND gate (AND)
4) Even-numbered video bit data (DDn +
1) will be interchanged. Finally, the OR gate (O
R1) is the odd-numbered video bit data (DDn) demodulated from the third AND gate (AND3) and the fourth AND gate (AND4).
Even-numbered video bit data (DDn +
By performing an OR operation on 1), these video bit data (DD
n, DDn + 1) are demodulated in a video bit stream (VBS) in which the VBSs are alternately arranged. The video bit stream (VBS) thus demodulated is supplied to the second bus line (4
D) via the second bit line (41A) constituting 1)
-Commonly supplied to IC (44).

FIG. 7 shows the level detector (6) shown in FIG.
0, 62, 64), an NMOS transistor (MP1) connected between the base voltage source and the node (75), and connected between the node (75) and the supply voltage source (VCC). And a third resistor (R3). When the superimposed modulation signal (TFMS) applied to its own gate terminal from the bit transmission line (36A) is larger than the threshold voltage (Vth), the NMOS transistor (MP1) applies the voltage on the node (75) to the ground voltage source (GND). ), A low logic amplitude detection signal (AD) is generated. Conversely, if the superimposed modulation signal (TFMS) applied from the bit transmission line (36A) to its own gate terminal is smaller than the critical voltage (Vth), the NMOS transistor (MP1) releases the node from the ground voltage source (GND). By doing so, a high logic amplitude detection signal (AD) is generated on the node (75). NMO
The threshold voltage (Vth) of the S-transistor (MP1) is determined by a voltage level to be detected by the level detectors (60, 62, 64). To elaborate on this,
The critical voltage (Vth) of the NMOS transistor (MP1) is the supply voltage
In the case of the first level detector (60) which detects a voltage corresponding to 1/3 of (VCC), the supply voltage (V
In the case of the second level detector (62) for detecting a voltage corresponding to 2/3 of (CC), a voltage corresponding to VCC / 3 to VCC × 2/3 and a voltage corresponding to the supply voltage (VCC) are detected. In the case of the third level detector (64), the voltage is set to VCC × 2/3 to VCC. Accordingly, the amplitude detection signal (AD) generated at the node (75) has a high logic when the superimposed modulation signal (TFMS) is lower than the voltage to be detected, while the superimposed modulation signal (TFMS) is higher than the voltage to be detected. In such a case, it has low logic.

From the above description, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but must be determined by the appended claims.

Other objects and features of the present invention other than the above-mentioned objects will become apparent through detailed description of embodiments with reference to the accompanying drawings.

As described above, in the superimposition modulator of the present invention, two-bit data adjacent on the time axis is superimposed in the form of an amplitude signal, so that the frequency of the transmission data is lowered and the data transmission is performed. Power consumption is close to 1/4
To a small value . This reduces EMI in the superimposed modulated signal generated by the superimposed modulator according to the present invention.

Also, in the repeater according to the present invention using a superimposition modulator and a superimposition demodulator, data of at least 2 bits on the time axis is transmitted in a state of being superimposed in the form of an amplitude signal, so that the transmission frequency band is increased. And the power consumption is reduced. This makes the data transmitted by the repeater according to the invention almost insensitive to EMI.

An LC according to the present invention utilizing the repeater described above
Similarly, in D, the data transmission frequency band is lowered, and the power consumed for data transmission is reduced. As a result, the LCD according to the present invention can minimize EMI effects. At the same time, in the LCD according to the present invention, the
-Data transmission line (36) in addition to being built into IC
If the key transmission line is connected to the D-IC in common, the video data transmitted from the video card to the D-IC
In addition to minimizing the influence, the wiring structure can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a normal computer system using a liquid crystal display device.

FIG. 2 is a diagram schematically illustrating a liquid crystal display device to which a modulator and a superimposition demodulator according to an embodiment of the present invention are applied.

FIG. 3 is a detailed block diagram of a superimposition modulator illustrated in FIG. 2;

FIG. 4 is an output waveform diagram for each part of the superposition modulator shown in FIG. 3;

FIG. 5 is a detailed block diagram of the superimposition demodulator shown in FIG. 2;

FIG. 6 is an output waveform diagram for each part of the superposition demodulator shown in FIG. 5;

FIG. 7 is a detailed block diagram of the level detector shown in FIG. 5;

[Explanation of symbols]

 10, 30: Computer main body 12, 32: Video card 20, 40: LCD 22, 42: Liquid crystal panel 24, 44: D-IC 26, 48: Controller 34: Superimposed modulator 36: Transmission line 38: Key transmission line 46: superimposition demodulator 50: first flip-flop 52: second flip-flop 54: third flip-flop 66: encoding unit 68: fourth flip-flop 70: fifth flip-flop 72: sixth flip-flop 74: seventh flip flop

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-258686 (JP, A) JP-A-61-281734 (JP, A) JP-A-60-239141 (JP, A) JP-A-1- 243623 (JP, A) JP-A-3-258025 (JP, A) Registered utility model 3005113 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 25/49 G09G 3/20 612 G09G 3/20 633 G09G 3/36

Claims (7)

(57) [Claims] (1) Synchronizes with incoming bit data stream
Divide the data clock, which is divided into the key clock signal
A frequency divider that outputs 2 adjacent on the time axis from the bit data stream
One bit data at the rise of the key clock signal
And 1st latching in synchronization with the falling edge, respectively.
A second latch device; Each of the first and second latches having a different resistance value
First and second obtaining a superimposed modulation signal by superimposing an output voltage;
Resistance and Superposition modulation device provided with . (2) The divider divides the data clock by two
Frequency divider, The first and second resistors are connected to the first and second latches.
Output voltage values of about 1/3 and 2/3 respectively
Reduce to 2. A superposition modulation apparatus according to claim 1, wherein: . (3) Display bit stream of video data on LCD
Data relay device for transmitting to the display device, ,Divide the data clock synchronized with the bit stream
And a frequency divider that outputs this as a key clock signal, 2 adjacent on the time axis from the bit data stream
One bit data at the rise of the key clock signal
And 1st latching in synchronization with the falling edge, respectively.
A second latch having a different resistance value than the first latch;
Each output voltage of the second latch is superimposed to generate a superimposed modulation signal.
A superimposed modulator including first and second resistors to obtain; An input terminal receives the superimposed modulation signal through a transmission path,
A number of digital data corresponding to the voltage level
A level detector for converting the Receiving the key clock signal at the input terminal through the transmission line;
In synchronism with this, the plurality of digital data are combined.
An encoder for encoding the video data together; The key
The video data is displayed on the time axis in synchronization with the clock signal.
Arranging and outputting the arranged video data to the liquid crystal display device
A demodulator that A data relay device comprising: (4) The divider divides the data clock by two
Frequency divider, The first and second resistors are connected to the first and second latches.
Output voltage values of about 1/3 and 2/3 respectively
Reduce to 4. The data relay device according to claim 3, wherein: (5) The level detector is Vth / 3, 2Vth / 3
And Vth having a reference level potential of Vth, respectively.
3 level detectors, each of the level detectors
The level of the control signal is compared with each reference level potential.
First to third digital data corresponding to the comparison result
Output The encoder discusses the first to third digital data.
Parallel processing of the first and second video data obtained by
Output to The demodulator receives the first and second video data at an input terminal.
In synchronization with the key clock signal.
Arranging the second video data on a time axis, and
The data is output to a driver circuit for driving the liquid crystal display device.
Empower, 5. The data relay device according to claim 4, wherein: 6. A liquid crystal display device, Data synchronized with the bit data stream of video data
Clock, and output this as the key clock signal.
Frequency divider and time from the bit data stream
Two key data adjacent on the axis are converted to the key clock
Synchronize with the rise and fall of the signal, respectively.
Have different resistance values from the first and second latch devices to be latched.
And superimposing each output voltage of the first and second latches.
And a first resistor and a second resistor for obtaining a superimposed modulation signal.
Input the superimposed modulation signal from a tatami modulation device through a transmission path.
At the end to detect the voltage level of this signal, and
To multiple digital data corresponding to different voltage levels
A level detector for The key clock signal supplied through the transmission path
Synchronize and combine multiple digital data in parallel
An encoder for encoding the video data in a form; The video in the parallel form in synchronization with the key clock signal
Arrange data on the time axis and output the arranged video data
A demodulator that A liquid crystal panel for displaying video data, The video data from the demodulator is received at the input end and the liquid
A driver circuit for driving the crystal panel; A liquid crystal display device comprising: 7. The level detector is Vth / 3, 2Vth / 3
And Vth having a reference level potential of Vth, respectively.
3 level detectors, each of the level detectors
The comparison result is compared with each reference level potential
Output the corresponding first to third digital data respectively
And The encoder discusses the first to third digital data.
Parallel processing of the first and second video data obtained by
Output to The demodulator receives the first and second video data at an input terminal.
In synchronization with the key clock signal.
Arranging the second video data on a time axis, and
Outputting data to the driver circuit; The liquid crystal display device according to claim 6.