JP3290716B2 - Multi-tone processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-gradation processing method and a multi-gradation processing recording apparatus, and more particularly, to a multi-gradation processing apparatus and a multi-gradation processing recording applied to a digital copying machine and a facsimile machine. Related to the device.

[0002]

2. Description of the Related Art Hitherto, a dither system has been widely used as a means for displaying a halftone image in a recording section of a copying machine, a facsimile machine or the like. FIG. 3 shows an example of a block configuration of a binary dither processing circuit. The comparator 1 compares input multi-level data with threshold data according to a dither matrix, and determines a corresponding pixel as a white pair according to the magnitude. The information is output as black binary information. As a result, the halftone can be expressed in binary.

[0003] On the other hand, in recent years, demands for higher image quality have increased,
Research and development of recording systems capable of modulating and recording one pixel at multiple gradations are also being actively pursued. However, the number of gradations per pixel obtained by such a multi-value recording system can be compared to the number of input gradations to be read. The number may vary due to various restrictions (for example, the number of gradations cannot be obtained compared to an almost linear input system due to the rise of the gamma value of the recording system, the problem of toner particle size and toner adhesion amount, or jitter). Is smaller than the input system at present. FIG. 4 shows an example of the multi-value dither processing circuit. However, since the number of gradations of the output recording system is smaller than the number of gradations of the input reading system as described above, in the multi-value dither processing,
As shown in FIG. 4, a latch 3 and a large-capacity ROM table 4 as a multi-value pattern table are required. Further, as a recording system of such multi-tone modulation recording, for example, there is a recording system described in JP-A-62-43264 in which an input multi-value is obtained as a pseudo gradation by a multi-value pattern table. Japanese Unexamined Patent Publication No.
The thing described in 1-105170 is known.

[0004]

However, in such a conventional multi-tone processing method, a large-capacity ROM is required.
There is a problem that a table is required, a great deal of effort is required to create this pattern table, or a circuit configuration becomes complicated, and the cost increases to obtain high image quality. .

Therefore, the present invention provides a low-cost multi-tone processing apparatus and a multi-level processing apparatus capable of obtaining a high-quality image by constructing a simple multi-value dither processing circuit by extending the binary dither processing circuit. An object of the present invention is to provide a tone processing recording device.

[0006]

According to the first aspect of the present invention,
In order to solve the above problem, the input pixel bit L per pixel
Output multi-valued input pixel data per pixel
And outputs the input pixel bits L and
Relationship finely the output pixel number of bits M is a multi-gradation processing device which is a L ≧ M, any of the within a range satisfying L ≧ M
Output bit number input means for inputting the output pixel bit number M
Means for inputting the input pixel bit L to the output bit number input means.
The number M of the output pixel bits input by
Bit allocation to the lower number of bits (LM)
Dividing means and before the input of the output bit number input means
The matrix size is determined based on the output pixel bit number M.
A matrix size setting means for setting, said comparing means values and matrix size by (LM) bits of the lower of the pixel data is compared with the value of the dither matrix such that 2 ^LM tone, said comparison means based on the comparison result, characterized in that it has a selection output means for selecting and outputting any of those +1 upper M-bit data of the upper M-bit data itself and the input pixel bit data of the input pixel data And

According to a second aspect of the present invention, in order to solve the above-mentioned problem, in addition to the configuration of the first aspect, the output pixel bit number
M is the magnification and linear density of the recorded image within the range satisfying L ≧ M.
The output pixel view set as described above.
Output bit number for inputting the number of bits M to the output bit number input means.
It is characterized by having a number-of-bits setting means .

[0008]

According to the first aspect of the present invention, the value of the lower (LM) bits of each pixel data and the matrix size are 2 bits.
The value of the dither matrix that becomes the ^LM gradation is compared, and based on the comparison result, one of the upper M-bit data of the input pixel data itself and one obtained by adding +1 to the upper M-bit data of the input pixel data is selected. Output. As a result, a simple multi-level dither processing circuit can be realized by extending the binary dither processing circuit.

[0009] In the present invention of claim 1, wherein, before SL output pixel number of bits M is, is variably set in a range satisfying M ≦ L, it is possible to increase the versatility of the processing circuit. In the invention of claim 2, wherein, in addition to the operation of claim 1, before SL output pixel number of bits M is set according to the magnification ratio or linear density of recorded images in a range satisfying M ≦ L. Therefore, a simple multi-level dither processing circuit can be realized by extending the binary dither processing circuit, and the resolution can be favorably maintained in a digital copying machine or a copying machine in accordance with the magnification or linear density.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure 1 is a diagram showing an embodiment of a multi-gradation processing unit. In FIG. 1, 11 is an L-bit latch, 12 is an adder, 13 is a selector, 14 is a comparator, 15 is a sub-scanning counter, and 16 is a main-scanning counter. Also,
S (L) in FIG. 1 is input pixel data of L bits per pixel, P (M) is output pixel data of M bits per pixel, and the number of gradation patterns of the dither table value in FIG. ^LM . Note that L and M are natural numbers, but M
May be zero.

Here, in the present embodiment, the input pixel data read in multi-valued L bits (2 ^L values) per pixel is 1 bit.
M bits per pixel are output as multi-values (2 ^M values), and the relationship between M and L is M ≦ L. And
When the input pixel data is output with the number of tones lowered from the 2 ^L value to the 2 ^M value, the lower (L−
The value of the M) bits and the value of the dither matrix such that the matrix size becomes 2 ^LM gradation are compared by the comparator 14, and the upper M-bit data itself of the input pixel data and the upper M-bit data of the input pixel data are compared. Either of the + 1's is selected by the selector 13 and output. Therefore, the comparator 14 constitutes the comparison means of the present application, and the selector 13 constitutes the selection output means of the present application.

More specifically, image information input multi-valued data S (L)
Is temporarily latched by the L-bit latch 11, and M bits equivalent to the recording capability of the plotter are extracted from the upper part of the input L bits and input to the selector 13. On the other hand, the upper M-bit data is incremented by one by the adder 12 and enters the other of the selectors 13. The lower LM bits of the output of the L-bit latch 11 are input (LM)
The same processing as the binary dither of the bit is performed, and the value A after the processing is obtained.
Is compared with a ditherable value B corresponding to 2 (LM) gradations by the comparator 14 . A and B are compared
As a result, when A is smaller than B (as shown in FIG. 1),
Based on the above two cases, which are larger than B,
The selector 13 of the set is switched. A is less than B
In this case, +1 is added to the upper M-bit data of the input pixel data.
Are selected by the selector 13, and A is larger than B
, The upper M-bit data of the input pixel data
Is selected by the selector 13. Note that FIG.
The selector 25 now selects as described above.
ing. As a result, the lower-order (LM) data that has been truncated in the process of converting the input S (L) to the output P (M) has been distributed to area gradation by dither processing.

As described above, in this embodiment, a large-capacity ROM is required as in the conventional multi-valued pattern table ROM method shown in FIG. A multi-level dither processing circuit can be easily realized by extending the binary dither processing circuit without using a multi-level dither processing circuit. With this resolution, a high-quality image equivalent to the number of input gradations can be obtained. Therefore, it is possible to simplify the device configuration and reduce costs while providing a high-quality image.

[0014] Figure 2 is a block diagram showing a multi-gradation processing section of one embodiment of a multi-gradation processing equipment (digital copiers and copier). In FIG. 2, 21 is an L bit latch, 2
2 is a bit distributor, 23 is an adder, 24 is a selector,
25 is a comparator, 26 is an M-bit register, 27 is a matrix size setting circuit, and 28 is a main / sub-scanning counter.

In this embodiment, similarly to the above-described embodiment, input pixel data read in L bits per pixel (2 ^L values) is output in M bits per pixel (2 ^M values). And
An apparatus in which the relationship between M and L is M ≦ L. Further, in this embodiment, when the input pixel data is output with the number of gradations reduced from the 2 ^L value to the 2 ^M value, the value of the omitted lower (LM) bits of each pixel data and the matrix size are 2
^The comparator 25 compares the value of the dither matrix to the ^LM gradation. This comparator 25
Based on the comparison result, either the upper M-bit data itself of the input pixel data itself or the value obtained by adding +1 to the upper M-bit data of the input pixel data is selected and output by the selector 24. On the other hand, when the output pixel bit number M is
Magnification and linear density of the recorded image within the range satisfying M ≦ L
Depending on either, CPU 40 shown in FIG. 2 (Centoral
Processing Unit)
You. CPU 40 (Centoral Processing Uni) shown in FIG.
output bit number setting data from t) is are entered into the M-bit register 26. According to the set number of bits, the distributor 22 changes the L bits into the upper M bits and the lower L bits.
-Assign to M bits. On the other hand, the matrix size of the dither table is changed by the matrix size setting circuit 27 in accordance with the set number of bits. Therefore, the comparator 25 constitutes the comparing means, the selector 24 constitutes the selection output means, and the bit distributor 22 distributes the bits.
The M bit register 26 stores the number of output bits.
To form an input unit, a matrix size setting circuits 27 constitute a matrix size setting means, CPU 40 (Centor
al Processing Unit) constitutes an output bit number setting unit.

Here, the number of bits of M corresponding to the read linear density and the set magnification and the effect thereof are as follows, for example. Reading linear density 100 dpi ← → 400 dpi ← → 1600 dpi Set scaling ratio 25% ← → 100% ← → 400 % M 8 bits ← → 4 bits ← → 1 bit Effect Multi-value direct output ← → 16-value dither ← → 2-value dither As described above, in the present embodiment, the effect of the above-described embodiment can be obtained, and the amount of conversion from L to M bits is M ≦
L can be set arbitrarily in a range of L, so that it can be set arbitrarily from binary dither processing output to complete multi-value level with the same number of bits as one input with one hardware, without dropping the number of macro gradations to any output printer Can be output. Also, conventionally, it was necessary to have two types of circuits, a binary dither processing circuit and a multi-value dither processing circuit. However, according to the present invention, there is an advantage that the circuits can be integrated into one type of circuit.

Further, the area modulation ratio from binary dither processing to multi-level direct output can be freely set with the same hardware, so that it can be applied to various printers and can be adapted to originals. By switching this, an optimum image can be obtained. Further, the versatility of the processing circuit can be increased, and cost reduction and integration can be achieved. Furthermore, since the number of gradations per pixel is changed according to the resolution (magnification and linear density), the number of macro gradations (= pseudo intermediate gradation + multi-value gradation number) is always maintained. However, the resolution can be kept good in accordance with the magnification and the linear density. That is, by setting the value of M as described above, when the reading linear density is low, it is possible to prevent the apparent resolution from further lowering by increasing the multi-value output level, and to reduce the reading linear density. If it is large, the area modulation ratio can be increased to ensure macro smoothness, and high quality image quality can be maintained as a whole.

[0018]

According to the first aspect of the present invention, a simple multi-level dither processing circuit can be realized by extending the binary dither processing circuit, so that the apparatus configuration can be simplified while providing high quality images. Further, cost can be reduced. Claim
According to the invention 1, wherein the number of output pixel bit M is, M ≦ L
Since it can be set variably within a range that satisfies, the versatility of the processing circuit can be increased, and cost reduction and integration can be achieved.

According to the invention of claim 2 , according to claim 1,
In addition to the effect , the output pixel bit number M can be changed according to the scaling ratio and the linear density of the recorded image. Therefore, in a digital copying machine, a copying machine, etc., while always maintaining a macro-like gradation number, The resolution can be kept good according to the magnification and the linear density.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-tone processing device according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a multi-tone processing device according to the present invention.

FIG. 3 is a block diagram showing a conventional binary dither processing circuit.

FIG. 4 is a block diagram showing a conventional multilevel dither processing circuit.

[Explanation of symbols]

13 selector (selection output means) 14 comparator (comparison means) 22 bit distributor ( bit distribution means ) 24 selector (selection output means) 25 comparator (comparison means) 26 M-bit register ( output bit number input means ) 27 matrix size setting Circuit ( matrix size setting)
Constant means) 40 CPU (output bit number setting means)

Claims (2)

(57) [Claims] 1. An input pixel bit L is read per pixel.
Output pixel bits per pixel
And outputs the input pixel bit L and the output image.
A multi-gradation processing device in which the relationship of the number of prime bits M is L ≧ M , wherein the output pixel bit number M is arbitrary within a range satisfying L ≧ M.
An output bit number of input means but that is input, the input pixel bits L to the output bit number of input means
Of the output pixel bit number M,
Bit allocation to lower bits (LM)
Means, and the output pixel bit inputted by the output bit number input means.
A matrix that sets the matrix size based on the number of
And Rikusu size setting means, and comparing means for the values and the matrix size by (LM) bits of the lower of the pixel data is compared with the value of the dither matrix such that 2 ^LM tone, comparison of the comparison means based on the results, and having a selection output means for selecting and outputting either the upper M-bit data per se and the input to the upper M-bit data of the pixel bit data plus the although the input pixel data Multi-tone processing device. 2. The output pixel bit number M satisfies L ≧ M.
Within the range according to either the magnification or linear density of the recorded image
Output the set output pixel bit number M
Output bit number setting means for input to bit number input means
2. The multi-gradation processing device according to claim 1, wherein
Place.