JP3262258B2 - Data transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit for distributing and selecting data signals in a digital circuit.

[0002]

2. Description of the Related Art Data transmission circuits such as data distribution circuits (demultiplexers) and data selection circuits (multiplexers) used in digital circuits are usually CMOS [Compl.
ementary Metal Oxide Semiconductor] logic circuit. This CMOS logic circuit uses complementary P-channel and N-channel MOS transistors, and has a TTL [Transistor Transistor Logi
This has the advantage that power consumption is extremely reduced as compared with c).

FIG. 11 shows a circuit example of a data distribution circuit using the above-described CMOS logic circuit. This data distribution circuit
It comprises four 3-input AND gates 11 for inputting an input signal IN and 2-bit address signals A0 and A1. However, the address signals A0 and A1 input to each of the three-input AND gates 11 are appropriately connected to the inverter circuits 12 and 12 respectively.
Is inverted by Therefore, these four 3-input ANs
Since only one of the D gates 11 passes the input signal IN according to the address signals A0 and A1, the input signal IN can be distributed to four output signals OUT1 to OUT4.

As shown in FIG. 12, each three-input AND gate 11 has three P-channel MOS transistors Q21.
To the output of a logic circuit in which a parallel circuit of Q23 to Q23 and a series circuit of three N-channel MOS transistors Q24 to Q26 are connected in series between the power supply VDD and the ground GND.
It is configured by connecting an inverter circuit composed of channel MOS transistors Q27 and Q28.

Therefore, if the input is in a steady state, all three P-channel MOS transistors Q21 to Q23 are always cut off or three N-channel MOS transistors Q21 to Q23 are turned off.
24 to Q26 is cut off and the output is M
Since the input is made to the high impedance gates of the OS transistors Q27 and Q28, the power consumption is extremely reduced.

However, in the case of the data distribution circuit described above, the P-channel and N-channel MOS transistors Q21 to Q26 may be simultaneously turned on during the transition of the signal change when the address signals A0 and A1 are switched. , A through current flows between the power supply VDD and the ground GND.

Therefore, a circuit system using a pass transistor which can eliminate such a through current between the power supply and the ground and reduce the number of transistors has been conventionally proposed. FIG. 1 shows a circuit example of a data selection circuit using pass transistors.
3 is shown. This data selection circuit responds to the 4-bit address signals A0 to A3 by inputting 16-bit input signals IN0 to IN0.
To IN15 and outputs it as an output signal OUT, and is configured by connecting 15 switch circuits SS in a binary tree structure (binary tree).

As shown in FIG. 14, each switch circuit SS has two select terminals b and c connected to one common terminal a via pass transistors Q31 and Q32, respectively. Each of the pass transistors Q31 and Q32 is an N-channel MOS transistor, and is arranged so as to connect between the selection terminals b and c and the common terminal a via the source and the drain.

A control input terminal s is connected to the gate of one of the pass transistors Q32, and a control input terminal s bar obtained by inverting the control input terminal s is connected to the gate of the other pass transistor Q31. I have. Therefore, in each switch circuit SS, according to the signal level of the control input terminal s, either the pass transistor Q31 or the pass transistor Q32 conducts, so that one of the signals input to the selection terminals b and c is selected. And output from the common terminal a.

As shown in FIG. 13, one switch circuit SS30 is arranged at the uppermost stage of the binary tree structure, two switch circuits SS20 and SS21 are arranged at the second stage, and the third stage is arranged at the third stage. Has four switch circuits SS10 to SS
13 are arranged, and eight switch circuits SS00-
SS07 is arranged. Then, the lower switch circuit S is sequentially connected to the selection terminals b and c of the upper switch circuit SS, respectively.
By connecting the common terminal a of S, 15 switch circuits SS are connected in a binary tree structure. Here, each switch circuit SS is arranged at each node in the binary tree structure. And
The stage at which each switch circuit SS is arranged represents the depth of a node in this binary tree, and the topmost switch circuit SS30 is the root.

Each of the 16-bit input signals IN0 to IN15
Is input to the selection terminals b and c of the eight lowermost switch circuits SS00 to SS07, and the output signal OUT is output from the common terminal a of the uppermost one switch circuit SS30. Also, each bit signal A0 of the 4-bit address signal
A3 to A3 and the inverted bit signals A0 to A3 are respectively connected to a switch circuit SS having a binary tree structure.
Are input to the control input terminals s and s bar.

That is, the most significant bit signals A3, A3 are input to the control input terminals s, s of the uppermost switch circuit SS30, and the most significant bit signals A2, A2 are supplied to the second-stage switch circuits SS20 to SS21. The bit signals A1, A1 are input to the control input terminals s, s bar of the third-stage switch circuits SS10 to SS13.
The bit signals A0 and A0 are supplied to the lowermost switch circuit SS00.
Are input to the control input terminals s and s bar of .about.SS07.

Therefore, each of the 16-bit input signals IN0 to IN0.
When IN15 passes through the switch circuits SS of each stage of the binary tree structure, any one of the adjacent ones is sequentially selected according to the bit signals A0 to A3 of these address signals, and finally, the uppermost switch circuit SS30 Is output as the output signal OUT.

For example, if the address signals A0 to A3 are "Ah"
(“H” indicates hexadecimal notation), that is, “10” in binary notation
If it is 10 ", the bit signals A0 and A2 go to the H level and the bit signals A1 and A3 go to the H level. As a result, only the pass transistor Q32 of the uppermost switching circuit SS30 conducts, Second stage switch circuit S
In S20 to SS21, only the pass transistor Q31 conducts,
In the switch circuits SS10 to SS13 of the stage, only the pass transistor Q32 conducts, and the switch circuits SS00 to SS
In 07, only the pass transistor Q31 conducts. Therefore, in this case, the input signal IN10 is applied to the switch circuits SS05 and S05.
The signal is output as an output signal OUT through the paths of S12, SS21 and SS30.

When the address signals A0 to A3 are "5
h ”(“ 0101 ”in binary notation),
Since the bit signals A0 and A2 go to the H level and the bit signals A1 and A3 go to the H level, only the pass transistor Q31 of the uppermost switch circuit SS30 conducts.
In the second-stage switch circuits SS20 to SS21, only the pass transistor Q32 conducts, and the third-stage switch circuits SS10 to SS21
In S13, only the pass transistor Q31 conducts, and in the lowermost switch circuits SS00 to SS07, only the pass transistor Q32 conducts. Therefore, in this case, the input signal IN5 is output as the output signal OUT through the path of the switch circuits SS02, SS11, SS20, and SS30.

In the data selection circuit, since the pass transistor Q of the switch circuit SS can transmit a data signal in both directions, the data selection circuit can be used as a data distribution circuit with its input and output reversed.

[0017]

However, in the data selection circuit, when the address signals A0 to A3 change from "Ah" to "5h", all the bit signals A0 to A3 are inverted. The conduction and interruption of the pass transistors Q31 and Q32 in the switch circuit SS are switched. Then, for example, in the case of the input signal IN13, while the address signals A0 to A3 are "Ah", they are immediately cut off by the pass transistor Q32 of the switch circuit SS06, but the address signals A0 to A3 change to "5h". And the switch circuit SS
06, SS13 and SS21 are connected, and the switch circuit SS30
To the pass transistor Q32.

Therefore, on the supply side of the input signal IN13, when the path is extended due to the change of the address signals A0 to A3, charging and discharging of stray capacitance and parasitic capacitance on the extended path are performed. It is necessary to supply a current to the device.
Then, no matter how the address signals A0 to A3 change, such useless charge / discharge current is generated to some extent.

For this reason, in the conventional data selection circuit using pass transistors, the through current between the power supply and the ground which occurs when the CMOS logic circuit is used can be eliminated, but when the address signals A0 to A3 change, the selection current does not change. Since the switching is performed up to the pass transistor Q of the switch circuit SS on a path that is not performed, an unnecessary signal change occurs on these paths and a useless charge / discharge current flows, so that power consumption cannot be reduced sufficiently. was there.

The bit signals A0 to A3 of the address signal
When a timing skew occurs between the bit signal A0 bar and the inverted bit signal A3 bar, the pass transistor Q31 and the pass transistor Q32 of each switch circuit SS are simultaneously turned on during the transition period when the address signal changes. Conduction may occur. For example, when a timing skew occurs between the lowermost bit signal A0 and the bit signal A0 bar, the pass transistors Q31 and Q32 of the lowermost switch circuits SS00 to SS07 are simultaneously turned on, and the input signals IN0 and IN0.
When adjacent input signals IN such as between IN1 and input signals IN2 and IN3 are short-circuited, a through current may flow when these signal levels are different.

Further, when the address signals A0 to A3 change, as described above, the switching is performed up to the pass transistor Q of the switch circuit SS on the path that is not selected, so that, for example, when the least significant bit signal A0 changes. , The input signal I in all the eight switch circuits SS in the lowermost stage.
There is a possibility that a through current flows between N.

For this reason, in the conventional data selection circuit using pass transistors, when the address signals A0 to A3 change, the through current flows between the input signals IN even through the pass transistor Q of the switch circuit SS on the path not selected. Therefore, there is a problem that power consumption cannot be sufficiently reduced.

The present invention has been made in view of the above circumstances, and has as its object to provide a data transmission circuit that eliminates unnecessary charge / discharge currents and through currents by preventing switching of switch circuits on paths that are not selected.

[0024]

According to the data transmission circuit of the present invention, two selection terminals are connected to one common terminal via a source and a drain of a MOS transistor, respectively, and a control terminal is connected to the gates of these MOS transistors. By inputting the input signal as it is or by inverting the input signal, switch circuits for conducting only one of the selection terminals to the common terminal according to the input signal are sequentially connected to the two selection terminals of the upper-stage switch circuit, respectively. In a data transmission circuit provided with a data signal switching circuit connected to a binary tree structure by connecting common terminals of a lower switching circuit, each bit signal of an address signal is converted into each stage of the binary tree structure of the data signal switching circuit. And the control input of the uppermost switch circuit in the data signal switching circuit is A bit signal corresponding to the upper stage is supplied, and for each subsequent stage, of the plurality of switch circuits of the stage, a selection of a side that is conductive with the common terminal in the switch circuit of the upper stage to which the bit signal is supplied is selected. An address signal distribution circuit for supplying a bit signal corresponding to the stage only to a control input of a switch circuit connected to a terminal is provided, thereby achieving the above object.

Preferably, for each bit signal except for the one corresponding to the highest stage in the address signal, the address signal distribution circuit switches the switch circuit to a binary number of stages one less than the corresponding stage of the bit signal. In addition to being connected to the tree structure, a holding circuit that keeps outputting the immediately preceding bit signal even when the bit signal is no longer output from the selected terminal is connected to each selection terminal of the lowermost switch circuit of the binary tree structure. An address signal switching circuit is provided, and each bit signal except for the one corresponding to the uppermost stage is input to a common terminal of the uppermost switch circuit in each address signal switching circuit, and the bit signal corresponding to the uppermost stage is input to the common terminal. Input to the control input of the uppermost switch circuit in each address signal switch circuit and the data signal switch circuit And controlling a bit signal output from each holding circuit in each of the address signal switching circuits by a switching circuit of a stage corresponding to the bit signal in each of the address signal switching circuits having more stages and the data signal switching circuit. It is to input to each input.

Preferably, the data signal switching circuit inputs a data signal to a common terminal of the uppermost switch circuit of the binary tree structure, and receives the data signal from one of the selection terminals of the lowermost switch circuit. Is a data distribution circuit that outputs.

Preferably, the data signal switching circuit inputs a data signal to each selection terminal of each of the lowermost switch circuits in the binary tree structure, and inputs a data signal from the common terminal of the uppermost switch circuit to the data signal. A data selection circuit that outputs one of the data signals.

Preferably, the data signal switching circuit inputs a data signal to a common terminal of an uppermost switch circuit of a binary tree structure, and receives the data signal from one of select terminals of a lowermost switch circuit. And outputs a predetermined logic level from the selection terminal of another lowermost switch circuit.

The operation will be described below.

According to the above configuration, each bit signal of the address signal is supplied not to all the switch circuits of the data signal switching circuit but to only the switch circuits on the path selected by the address signal. Therefore, the switch circuits on all the paths not selected by the address signal do not switch the selection terminals, so that there is no unnecessary signal change on these paths and unnecessary charge / discharge current can be eliminated. In addition, since only the minimum necessary switch circuit switches the selection terminal, the possibility that a through current flows between the data signals when the address signal changes can be reduced.

The address signal referred to here is not limited to a signal indicating an address of a memory or an I / O port, but indicates a general coded signal.

Further, according to the above configuration, the address signal distribution circuit can be constituted by providing an address signal switching circuit in which a switch circuit is connected in a binary tree structure for each bit signal of the address signal, similarly to the data signal switching circuit. it can. Each address signal switching circuit distributes such that the bit signal is supplied only to a switching circuit on a selected path in a corresponding stage of the data signal switching circuit. Further, since the previous bit signal is supplied from the holding circuit to each of the switch circuits on the paths not selected in the data signal switching circuit, switching of the selection terminal does not occur in these switch circuits.

Further, with the above configuration, the data transmission circuit can be used as a data distribution circuit.

Further, with the above configuration, the data transmission circuit can be used as a data selection circuit.

Further, with the above configuration, the data transmission circuit can be used as a decoder circuit. in this case,
Each switch circuit of the data signal switching circuit is configured to output a predetermined logic level from a selection terminal that does not conduct with the common terminal.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 8 show Embodiment 1 of the data transmission circuit of the present invention. Components having the same functions as those of the conventional example shown in FIG. 13 are denoted by the same reference numerals.

In the first embodiment, a case where the data transmission circuit is applied to a data distribution / selection circuit will be described. This data distribution / selection circuit includes a data signal switching circuit 1 and an address signal distribution circuit 2, as shown in FIG.

The data signal switching circuit 1 has substantially the same configuration as that of the data selection circuit shown in FIG. 13, except that 15 switch circuits SS are connected in a binary tree structure. According to the bit signal supplied from the address signal distribution circuit 2, the signal input to the input / output terminal IOX is used as a data distribution circuit for outputting from any of the input / output terminals IO0 to IO15, or the input / output terminal IO0 ~
It can be used as a data selection circuit that selects any one of the 16-bit signals input to IO15 and outputs it from input / output terminal IOX.

As shown in FIG. 2, each switch circuit SS has one common terminal a, two selection terminals b and c, and one control input terminal s. One of the selection terminals b is connected to a common terminal a via a parallel circuit of pass transistors Q1 and Q2 comprising P-channel and N-channel MOS transistors.
It is connected to the. The other selection terminal c is connected to a common terminal a via a parallel circuit of pass transistors Q3 and Q4, which are P-channel and N-channel MOS transistors.
It is connected to the. The control input terminal s is connected to the gates of the pass transistors Q1 and Q4 and to the gates of the pass transistors Q2 and Q3 via the inverter circuit 3.

Therefore, the switch circuit SS switches the pass transistors Q1, Q2 in accordance with the signal level of the control input terminal s.
Either both Q2 or both pass transistors Q3 and Q4 conduct. Therefore, the signal input to the common terminal a is distributed to one of the selection terminals b and c and output, or one of the signals input to the selection terminals b and c is selected to output the signal from the common terminal a. Can be output.

As shown in FIG. 3, the switch circuit SS can also be constituted by pass transistors Q5 and Q6 composed of N-channel MOS transistors. In this case, the selection terminals b and c are connected to the common terminal a via these pass transistors Q5 and Q6, respectively. In addition, the control input terminal s is connected to the gate of the pass transistor Q6 via the inverter circuit 3 while being connected to the gate of the pass transistor Q6.

This switch circuit SS has a control input terminal s bar instead of the inverter circuit 3 as in the case of the conventional example shown in FIG.
The bar may be connected to the gate of the pass transistor Q5. It should be noted that the pass transistors Q5 and Q6 can also be constituted by P-channel MOS transistors.

In the data signal switching circuit 1, as shown in FIG. 1, one switch circuit SS30 is arranged at the top of the binary tree structure, and two switch circuits SS20 and SS21 are arranged at the second stage. Then, four switch circuits SS10 to SS13 are arranged in the third stage, and eight switch circuits SS00 to SS07 are arranged in the lowest stage. Then, the lower switch circuit S is sequentially connected to the selection terminal of the upper switch circuit SS.
By connecting the common terminals of S, 15 switch circuits SS are connected in a binary tree structure.

An input / output terminal IOX is connected to a common terminal of the uppermost switch circuit SS30, and input / output terminals IO0 to IO15 are connected to respective select terminals of the lower eight switch circuits SS00 to SS07. Have been.

When the data signal switching circuit 1 is used as a data distribution circuit, a data signal is input to the input / output terminal IOX, and the data signal is output from any of the input / output terminals IO0 to IO15. When used as a data selection circuit, a data signal is input to each of the input / output terminals IO0 to IO15, and one of the data signals is output from the input / output terminal IOX.

The address signal distribution circuit 2 includes an address signal switching circuit 2a in which seven switch circuits S are connected in a binary tree structure, an address signal switching circuit 2b in which three switch circuits S are connected in a binary tree structure, 1
Address signal switching circuit 2c including a plurality of switch circuits S
It is composed of

The switch circuit S has the same configuration as the switch circuit SS of the data signal switching circuit 1 shown in FIGS. The address signal switching circuit 2a includes one switch circuit S20 at the top, two switch circuits S10 and S11 at the second stage, and four switch circuits S00 to S03 at the bottom. Then, the least significant bit signal A0 of the address signal is input to the common terminal of the uppermost switching circuit S20. Further, the lowermost four switch circuits S00 to S03
Are connected to respective control input terminals s of the lowermost switch circuits SS00 to SS07 of the data signal switching circuit 1 via holding circuits H00 to H07, respectively.

The address signal switching circuit 2b is connected to the uppermost 1
Switch circuits S21 and the two lowest switch circuits S
12, S13. And the uppermost switch circuit S
The bit signal A1 of the address signal is input to the common terminal 21. In addition, the two lowermost switch circuits S12 and S12
13 are connected to the control input terminals s of the lowermost switch circuits S00 to S03 of the address signal switching circuit 2a via hold circuits H14 to H17, respectively. It is also connected to each control input terminal s of the third-stage switch circuits SS10 to SS13.

The address signal switching circuit 2c includes one switch circuit S22, and a bit signal A2 of an address signal is input to a common terminal of the switch circuit S22.
The selection terminals of the switch circuit S22 are connected to the control input terminals s of the second-stage switch circuits S10 and S11 of the address signal switching circuit 2a via the hold circuits H24 and H25, respectively. Signal switching circuit 2b
Control input terminals s of the lowermost switch circuits S12 and S13 of FIG.
To the data signal switching circuit 1
Each control input terminal s of the switch circuits SS20 and SS21 of the stage
Is also connected. The address signal switching circuit 2c can be considered to be one in which one switch circuit S22 is connected in a binary tree structure, and this switch circuit S22 is the one at the top and the bottom.

As shown in FIG. 4, the hold circuit H is a flip-flop circuit in which two inverter circuits 4 and 4 are connected in a cyclic manner, and an input signal is held by these inverter circuits 4 and 4. Accordingly, even when the input side is in a high impedance state, the immediately preceding input signal can be continuously output. Note that the hold circuit H may be a circuit in which four or more even-numbered inverter circuits are connected in a cyclic manner, or a flip-flop circuit having another normal configuration may be used.

In the address signal distribution circuit 2, the most significant bit signal A3 of the address signal is transferred to the hold circuit H30.
, The respective control input terminals s of the uppermost switch circuits S20 to S22 of the address signal switching circuits 2a, 2b, 2c and the uppermost switch circuit SS30 of the data signal switching circuit 1
Is entered. Note that this bit signal A
3, if it does not become high impedance state,
The signal may be directly input to each control input terminal s without going through the hold circuit H30.

In the data distribution / selection circuit having the above configuration, the address signals A0 to A3 are set to "Ah"("1" in binary notation).
010 ") to" 5h "(" 0101 "in binary notation).

First, when the address signals A0 to A3 become "Ah", the node N30 which is the output of the holding circuit H30 becomes H level by the most significant bit signal A3. Then, as shown in FIG. 5, in the address signal distribution circuit 2, the switch circuits S20 to S22 are connected to the nodes N21, N23, N25.
Switches to the selection terminal on the side. Also, since the node N25 goes low due to the bit signal A2, the switch circuits S11 and S13 are switched to the selection terminals on the nodes N12 and N16 side, and the node N16 goes high due to the bit signal A1. S02 is switched to the selection terminal on the node N05 side, and the node N05 becomes L level by the bit signal A0.

Therefore, the bit signal A3 causes the node N3
When 0 becomes H level, the data signal switching circuit 1
Is switched to the selection terminal on the node SN31 side, and the bit signal A2 switches the node N25 to the node N25.
Becomes L level, the second-stage switch circuit S
S21 is switched to the selection terminal on the node SN22 side, and the node N16 is set to the H level by the bit signal A1, whereby the third-stage switch circuit SS12 is switched to the selection terminal on the node SN15 side, and the bit signal A0 causes the node N0 to switch to the node N0.
When 5 goes low, the lowermost switch circuit SS05 is switched to the selection terminal on the input / output terminal IO10 side.
In the data signal switching circuit 1, the nodes SN31, S
The input / output terminal IOX and the input / output terminal IO10 are connected via a path passing through N22 and SN15.

That is, in the address signal distribution circuit 2, FIG.
As shown in FIG. 7, at time t1, the address signals A0 to A3 are set to "A".
h ", the node N30 sequentially goes high, the node N25 goes low, the node N16 goes high, and the node N05 goes low. In the data signal switching circuit 1, as shown in FIG. As shown, the nodes SN15, SN22, and SN31 are sequentially connected to the input / output terminal IO10, and finally, the input / output terminal IOX is connected to the input / output terminal IO10. , Hold circuit H holds the previous signal level, so that other nodes N of data signal switching circuit 1
Also, the previous state is maintained.

Next, when the address signals A0 to A3 change to "5h", the most significant bit signal A3 causes the node N3 to change.
0 changes to L level. Then, as shown in FIG. 8, in the address signal distribution circuit 2, the switch circuits S20 to S22 are switched to the selection terminals on the nodes N20, N22 and N24. Further, since the node N24 becomes H level by the bit signal A2, the switch circuits S10 and S12 are connected to the nodes N11 and N11.
Since the node N15 is switched to the L level by the bit signal A1, the switching circuit S01 is switched to the selection terminal on the node N02, and the node N02 is switched to the H level by the bit signal A0.

Therefore, the bit signal A3 causes the node N3
When 0 becomes L level, the data signal switching circuit 1
Is switched to the selection terminal on the node SN30 side, and the bit signal A2 switches the node N24 to the node N24.
Becomes H level, the second-stage switch circuit S
S20 is switched to the selection terminal on the node SN21 side, and the node N15 is set to the L level by the bit signal A1, whereby the third-stage switch circuit SS11 is switched to the selection terminal on the node SN12 side, and the node signal N0 is switched to the node N0 by the bit signal A0.
When 2 goes to the H level, the lowermost switch circuit SS02 switches to the selection terminal on the input / output terminal IO5 side.
Then, in the data signal switching circuit 1, the nodes SN30, S
The input / output terminal IOX and the input / output terminal IO5 are connected via a path passing through N21 and SN12.

That is, in the address signal distribution circuit 2, FIG.
As shown in the figure, at time t2, the address signals A0 to A3 are set to "5".
h ", the node N30 sequentially transitions to the L level, the node N24 goes to the H level, the node N15 goes to the L level, and the node N02 goes to the H level. As shown in FIG. 7, the nodes SN12, SN21 and SN30 are sequentially connected to the input / output terminal IO5, and finally the input / output terminal IOX is connected to the input / output terminal IO5.
Connected to

Also in this case, as shown in FIG.
Hold circuits H05, H16, H of address signal distribution circuit 2
25 keeps the signal level immediately before the nodes N05, N16 and N25.
The route to 5, SN22, SN31 is also maintained as it is, and cut off by the switch circuit SS30.

That is, as shown in FIG. 6, even after the address signals A0 to A3 change to "5h" at time t2, the signal levels of the nodes N25, N16 and N05 of the address signal distribution circuit 2 are maintained. Accordingly, even in the data signal switching circuit 1,
As shown in FIG. 7, the state where the nodes SN15, SN22, and SN31 are connected to the input / output terminal IO10 is maintained.

Therefore, the data signal input to the input / output terminal IO10 retains the path of the nodes SN15, SN22, and SN31 even after the address signals A0 to A3 change to "5h". There is no need to supply a current for charging / discharging the stray capacitance and the like. In addition, in the other routes than the route selected this time, the address signals A0 to A3
Is maintained before "Ah", so that the charge / discharge current supplied from the input / output terminals IO0 to IO15 can be minimized.

Note that FIGS. 5 and 8 do not show this switching state for the switch circuits SS and S for which it is unknown which of the selection terminals has been switched to in the initial state.

As a result, as described above, the address signal A0
When A3 changes from "Ah" to "5h", FIG.
As is clear from FIG. 1, the signal level surely changes only at the node N30 of the address signal distribution circuit 2, and depending on the initial state, the signal levels at the nodes N24, N15, and N02 change. Nodes N22, N20, N
Eleven signal levels can also change.

As is clear from FIG. 7, the signal levels of the nodes SN12, SN21 and SN30 of the data signal switching circuit 1 also change depending on the initial state. That is, in the data distribution / selection circuit according to the first embodiment, the signal level at one node changes without fail, and the signal level at nine nodes may change. The signal level of one node changes.

Also, the possibility of this signal level change is 5
Assuming 0%, the signal levels of 5.5 nodes (= 1 + 9 × 0.5) on average change. On the other hand, FIG.
In the case of the conventional example shown in FIG.
All of the pass transistors Q31 and Q32 are switched, so that the signal levels of the 14 nodes between these switch circuits SS all change.

Therefore, in the data distribution / selection circuit of the first embodiment, the worst node is about 71% (= 10/14) and the best node is about 7% (= 10%) as compared with the conventional example.
1/14), and on average can be reduced to about 39% (= 5.5 / 14), thereby reducing the supply of useless charge / discharge current. In addition, the data signal switching circuit 1 which switches according to the change of the address signal
The number of switch circuits SS is also greatly reduced, and the possibility that a through current flows between the data signals of the input / output terminals IO0 to IO15 is extremely reduced as compared with the conventional example.

(Embodiment 2) FIGS. 9 and 10 show Embodiment 2 of the data transmission circuit of the present invention. Note that components having the same functions as those of the first embodiment illustrated in FIGS. 1 to 3 are denoted by the same reference numerals, and a specific description thereof will be omitted.

In the second embodiment, a case where the present invention is applied to a decoder circuit will be described. This decoder circuit includes a data decode circuit 5 and an address signal distribution circuit 2, as shown in FIG. The address signal distribution circuit 2 has the same configuration as that of the first embodiment. The data decode circuit 5 is obtained by replacing the switch circuit SS in the data signal switching circuit 1 of the first embodiment with a switch circuit DS.

As shown in FIG. 10, the switch circuit DS has one common terminal a, two selection terminals b and c, and one control input terminal s, and is configured by pass transistors Q1 to Q4 and an inverter circuit 3. The configuration is the same as that of the switch circuit SS of the first embodiment shown in FIG. However, one select terminal b is grounded via the pass transistor Q7,
The other select terminal c is grounded via a pass transistor Q9.

The control input terminal s is connected to the gate of the pass transistor Q7.
Control input terminal s via inverter circuit 3
Is connected. Therefore, this switch circuit DS
When any one of the selection terminals b and c is made conductive to the common terminal a by the control input terminal s, the selection terminals b and c on the non-conductive side are not opened but these selection terminals b and c are opened.
C is grounded to output an L level.

In the data decode circuit 5, an input terminal Enable is connected to a common terminal of the uppermost switch circuit DS30, and an enable signal is input. The selection terminals of the lowermost switch circuits DS00 to DS07 are connected to output terminals OUT0 to OUT15. Then, similarly to the case where the data distribution / selection circuit of the first embodiment is used as the data distribution circuit, the H level of the enable signal Enable input to the input terminal Enable is selected according to the address signals A0 to A3. ~ OUT15
Can be output from any of The L level is output from the unselected output terminals OUT0 to OUT15.

In such a decoder circuit as well, the number of nodes at which the signal level changes due to the change of the address signals A0 to A3 is reduced, so that the supply of useless charge / discharge current can be reduced. Further, since the number of switch circuits DS of the data decode circuit 5 which is switched by the change of the address signal is greatly reduced, the output terminals OUT0 to OUT0 are output.
The possibility that a through current flows between the UTs 15 is extremely reduced as compared with the related art.

[0074]

According to the data transmission circuit of the present invention described above, since the switch circuit on the path not selected in the data signal switching circuit does not switch the selection terminal, unnecessary signal changes on these paths are prevented. As a result, power consumption can be reduced by eliminating waste of supplying a charging / discharging current to a stray capacitance or the like.

Further, since only the minimum necessary switch circuit switches the selection terminal, the possibility that a through current flows between the data signals when the address signal changes can be reduced to further reduce the power consumption. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of a data transmission circuit according to the present invention and illustrating a configuration of a data distribution / selection circuit.

FIG. 2 is a circuit block diagram illustrating a first embodiment of the data transmission circuit of the present invention and illustrating a configuration of a switch circuit.

FIG. 3 is a circuit block diagram illustrating a first embodiment of the data transmission circuit of the present invention and illustrating another configuration of the switch circuit.

FIG. 4 shows the first embodiment of the data transmission circuit of the present invention, and is a block diagram showing a configuration of a hold circuit.

FIG. 5 is a block diagram showing Embodiment 1 of the data transmission circuit of the present invention and showing an operation of the data distribution / selection circuit when an address signal is Ah.

FIG. 6 is a timing chart showing the operation of the address signal distribution circuit according to the first embodiment of the data transmission circuit of the present invention.

FIG. 7 shows the first embodiment of the data transmission circuit of the present invention, and is a timing chart showing the operation of the data signal switching circuit.

FIG. 8 shows the first embodiment of the data transmission circuit of the present invention, and is a block diagram showing the operation of the data distribution / selection circuit when the address signal changes to 5h.

FIG. 9 is a block diagram showing Embodiment 2 of the data transmission circuit of the present invention and showing a configuration of a data distribution / selection circuit.

FIG. 10 is a circuit block diagram illustrating a second embodiment of the data transmission circuit of the present invention and illustrating a configuration of a switch circuit.

FIG. 11 is a block diagram showing a conventional example and showing a configuration of a data distribution circuit using a CMOS logic circuit.

FIG. 12 is a circuit diagram showing a conventional example and showing a configuration of a three-input AND gate using a CMOS logic circuit.

FIG. 13 is a circuit diagram showing a conventional example and showing a configuration of a data selection circuit using pass transistors.

FIG. 14 is a circuit diagram showing a conventional example and showing a configuration of a switch circuit.

[Explanation of symbols]

 Reference Signs List 1 data signal switching circuit 2 address signal distribution circuit 2a address signal switching circuit 2b address signal switching circuit 2c address signal switching circuit 5 data decoding circuit SS switch circuit S switch circuit H hold circuit DS switch circuit a common terminal b selection terminal c selection terminal s control input terminal

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yuki Kajikawa 22-22 Nagaikecho, Abeno-ku, Osaka, Osaka Inside Sharp Corporation (72) Inventor Kazuya Fujimoto 22-22 Nagaikecho, Abeno-ku, Osaka, Osaka Co., Ltd. (72) Inventor Hiroshi Tanaka 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka Prefecture Inside Sharp Co., Ltd. (72) Inventor Kazuo Taki 4-6 Mireicho, Tarumi-ku, Kobe (56) JP-A-259847 (JP, A) JP-A-8-213894 (JP, A) JP-A-9-186242 (JP, A) JP-A-4-86120 (JP, A) JP-A-5-191239 (JP, A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (5)

(57) [Claims] 1. Two selection terminals are connected to one common terminal via a source and a drain of a MOS transistor, respectively, and an input signal of a control input is input to the gates of these MOS transistors as they are or inverted. Thereby, the switch circuit for conducting only one of the selection terminals to the common terminal in accordance with the input signal is sequentially connected to the two selection terminals of the upper switch circuit by connecting the common terminal of the lower switch circuit to each of the two selection terminals. In a data transmission circuit having a data signal switching circuit connected to a binary tree structure, each bit signal of an address signal is made to correspond to each stage of the binary tree structure of the data signal switching circuit, and the uppermost stage in the data signal switching circuit To the control input of the switch circuit of
A bit signal corresponding to the uppermost stage is supplied, and for each subsequent stage, a side of the plurality of switch circuits of the stage that is electrically connected to a common terminal in the switch circuit of the upper stage to which the bit signal is supplied. A data transmission circuit including an address signal distribution circuit that supplies a bit signal corresponding to the stage only to a control input of a switch circuit connected to the selection terminal of (1). 2. An address signal distribution circuit comprising: for each bit signal except for the one corresponding to the highest stage in the address signal, the switch circuit including a binary tree having one less stage than the corresponding stage of the bit signal; An address that is connected to a holding circuit that is connected to the selection circuit of the lowermost switch circuit of the binary tree structure and that continues to output the immediately preceding bit signal even when no bit signal is output from the selection terminal. Signal switching circuits, each bit signal except for the one corresponding to the uppermost stage is input to a common terminal of the uppermost switching circuit in each address signal switching circuit, and the bit signal corresponding to the uppermost stage is input to each of the Input to the control input of the uppermost switch circuit in the address signal switching circuit and the data signal switching circuit, and The bit signal output from each holding circuit in each address signal switching circuit is applied to the control input of the switching circuit of the stage corresponding to the bit signal in each of the other address signal switching circuits and the data signal switching circuit having a greater number of stages. 2. The data transmission circuit according to claim 1, wherein the data is input. 3. The data signal switching circuit inputs a data signal to a common terminal of an uppermost switch circuit of a binary tree structure and outputs the data signal from one of select terminals of a lowermost switch circuit. 3. The data transmission circuit according to claim 1, which is a data distribution circuit. 4. The data signal switching circuit inputs a data signal to each selection terminal of each of the lowermost switch circuits in the binary tree structure, and any one of these from a common terminal of the uppermost switch circuit. 3. The data transmission circuit according to claim 1, wherein the data transmission circuit is a data selection circuit that outputs a data signal. 5. The data signal switching circuit inputs a data signal to a common terminal of an uppermost switch circuit of a binary tree structure and outputs the data signal from one of select terminals of a lowermost switch circuit. 3. The data transmission circuit according to claim 1, further comprising a decoder circuit that outputs a predetermined logic level from a selection terminal of another lowermost switch circuit.