JP3252299B2 - Thin film transistor matrix and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) matrix formed on a liquid crystal panel or the like by an active matrix driving method and a method of manufacturing the same.

In recent years, TFT matrix type liquid crystal panels used for laptop personal computers and wall-mounted televisions have been developed. In the inspection process of a TFT matrix type liquid crystal panel, it is necessary to know the address of each pixel.

[0003]

2. Description of the Related Art The structure of a TFT matrix substrate will be schematically described with reference to the following drawings. FIG. 7 is a plan view of a TFT matrix.

In a TFT matrix type liquid crystal panel, a drive voltage is applied to a large number of gate bus lines 41 and drain bus lines 42 arranged in a matrix so as to intersect in the X and Y directions and to connect the two bus line intersections. By selectively driving the TFT 43 thus set, a corresponding desired pixel is displayed in dots. The structure of such a TFT matrix is, for example, that titanium (Ti) is placed on a transparent insulating glass substrate.
-A large number of gate bus lines and drain bus lines made of aluminum (Al) are arranged so as to intersect in the X and Y directions with an interlayer insulating film made of silicon nitride (SiN) or the like intersected. Is connected to the TFT. Amorphous silicon (a-Si) is used for the TFT operation semiconductor layer.
When a layer is used, plasma vapor deposition is performed on the gate insulating film.
A silicon nitride film (SiN) or a silicon nitride oxynitride (SiNO) film by a (P-CVD) method is used.

In the figure, 8D is the drain electrode of the TFT, 8S
Indicates the source electrode of the TFT, and 8C indicates the upper electrode of the storage capacitor (auxiliary capacitor bus line). Here, the address of the pixel is necessary when specifying a specific location such as a defective location.

Conventionally, the following method has been used as a method of representing an address. (1) Conventional example (1): Method of putting coordinate numbers in the outer frame of the display unit FIG. 8 is an explanatory diagram of a method of representing the address of a pixel according to the conventional example (1).

[0007] As shown in the figure, numbers are put on the gate bus side and the drain bus side outside the display portion of the liquid crystal panel (where there is no pixel pattern) every 10 or 100 lines from the end of the substrate. Specify a specific pixel.

(2) Conventional example (2): A method in which a pattern of numbers is put in a pixel and an address is looked up from the numbers Next, referring to FIG.
Will be described.

FIGS. 9A to 9F are cross-sectional views illustrating the steps of manufacturing a conventional TFT element. In FIG. 9A, a transparent insulating substrate is sputtered on a glass substrate 1.
An Al film and a Cr film are successively formed, the resist film is patterned by photolithography, and then etched using the resist film as a mask to form a gate electrode 2, a storage capacitor lower electrode 3, and an address pattern AD.

Next, the resist film is peeled off, and the gate insulating film as the first insulating film and the SiN film as the storage capacitor dielectric film, and the a-Si film as the working semiconductor layer by the P-CVD method.
5. Continuously grow a SiN film 6 as a channel protective film. Here, instead of the CVD SiN film 4, an alumina film formed by an atomic layer epitaxy (ALD) method may be used as the first insulating film.

In FIG. 9B, patterning is performed so that the channel protective film 6 immediately above the gate electrode 2 is left. FIG.
In (C), an n ⁺ -type a-Si
The layer 7 and the metal film 8 for source / drain electrodes are continuously formed.

In FIG. 9D, a contact layer 7 and a metal film 8 for source / drain electrodes are patterned to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C.

In FIG. 9E, a SiN film is formed as a second insulating film 14 by a P-CVD method, and contact holes are formed on the source electrode 8S and the storage capacitor upper electrode 8C. FIG.
In (F), an ITO film is formed as a transparent electrode film on the substrate, and the storage capacitor upper electrode 8C and the source electrode 8S are contacted and patterned to form the pixel electrode 11, thereby forming a TFT matrix.

[0014]

[Problems to be solved by the invention] As in the conventional example (1),
When a number is placed outside the gate bus and drain bus lines to see a specific pixel, it is very difficult to read the coordinates using a normal microscope.

In particular, cutting the substrate (to a certain size)
In this case, since there is no reference such as a numeral in the pixel, the specific pixel cannot be checked. If a number is entered in the pixel when forming the gate electrode and the storage capacitor electrode in the conventional example (2), this number is formed of a metal film, so the transmittance (aperture ratio) of the pixel decreases. There is a problem. Further, when an automatic inspection device for examining a defective portion by transmitted light is used, this number is detected as a defect.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pixel address (address) display for each pixel in a TFT matrix without lowering the transmittance so that a specific pixel such as a defect can be designated.

[0017]

Means for solving the problems are as follows: 1) A gate bus line 41 and a drain bus line 42 are arranged in a matrix with an insulating film interposed therebetween, and a thin film transistor 43 is provided at the intersection of both bus lines. The thin film transistor is disposed on a transparent insulating substrate 1 on a gate electrode 2, a lower electrode of a storage capacitor 3, a first insulating film serving as a gate insulating film.
4, a working semiconductor layer 5 is laminated in this order, a source electrode 8S and a drain electrode 8D are arranged on the working semiconductor layer via a channel protective film 6, and a dielectric film is formed on the storage capacitor lower electrode. Upper electrode of storage capacitor via first insulating film
8C is formed, a contact hole connected to the storage capacitor upper electrode and the source electrode is provided in the second insulating film deposited thereon, and a pixel electrode including the contact hole is formed. A drain electrode connected to the drain bus line, and a gate electrode connected to the gate bus line; a thin film transistor matrix provided with an address display pattern of pixel coordinates on a light-shielding film of a display unit; The address display pattern is formed on a storage capacitor, a gate bus line, or a drain bus line, the thin film transistor matrix according to the above 1), or 3) a gate electrode 2 and a storage layer on a transparent insulating substrate 1. A lower capacitor electrode 3 is formed, and a first insulating film 4, an operating semiconductor layer 5, a channel A first step of sequentially forming a protective film 6, a second step of patterning the channel protective film so as to leave the channel protective film immediately above the gate electrode, and a high-concentration semiconductor on the substrate. A third step of sequentially forming a contact layer 7 and a source / drain electrode metal film 8 made of, and then patterning the working semiconductor layer, the contact layer, and the source / drain electrode metal film to form a drain electrode 8D A fourth step of forming a source electrode 8S and a storage capacitor upper electrode 8C.
A fifth step of depositing a second insulating film 9; and then forming a contact hole in the second insulating film on the source electrode and the storage capacitor upper electrode, and forming a contact hole on the storage capacitor upper electrode. A sixth step of forming a contact hole in an address display pattern of pixel coordinates, and then forming a transparent electrode film on the substrate, and contacting the storage capacitor upper electrode and the source electrode with the transparent electrode film. And a seventh step of patterning the transparent electrode film to form a pixel electrode 11. 4) the fourth step instead of forming the address display pattern in the sixth step. Forming the address display pattern by patterning the active semiconductor layer, the contact layer, and the source / drain electrode metal film on a gate bus line. 5) The method of manufacturing a thin film transistor matrix according to 3), or 5) instead of forming the address display pattern in the sixth step, patterning the transparent electrode film on a gate bus line or a drain bus line in the seventh step. This is achieved by the method of manufacturing a thin film transistor matrix described in 3) above, wherein the address display pattern is formed.

[0018]

According to the present invention, it is possible to designate a specific pixel without lowering the transmittance by providing an address (address) display of a TFT matrix in a light shielding film in a display section of a liquid crystal panel.

For example, if a pattern such as a numeral is formed on a storage capacitor electrode as a light-shielding film in a display portion, it is possible to eliminate a decrease in transmittance due to a metal address using a metal film, which has conventionally been a problem. In addition, it is not detected as a defect in the automatic inspection using transmitted light.

[0020]

Next, a conventional structure will be described together with a manufacturing process. Embodiment (1): FIGS. 1A to 1F are cross-sectional views of an embodiment (1) of the present invention.

In FIG. 1 (A), a 1000 .mu.m thick Al is sputtered on a glass substrate 1 as a transparent insulating substrate.
A film and a Cr film having a thickness of 1000 mm are successively formed, the resist film is patterned by photolithography, and then etched using the resist film as a mask to form a gate electrode 2 and a storage capacitor lower electrode 3.

Next, the resist film is peeled off, and a 4000-nm-thick silicon nitride (SiN) film is formed by a P-CVD method as a gate insulating film as a first insulating film and a storage capacitor dielectric film.
4, a 150-mm thick a-Si film as a working semiconductor layer, and a 1200-nm thick SiN film 6 as a channel protective film are continuously grown.
Here, instead of the SiN film 4, an alumina film formed by an ALD method may be used as the first insulating film.

In FIG. 1B, patterning is performed so that the channel protective film 6 immediately above the gate electrode 2 is left. FIG.
In (C), the contact layer is 600 mm thick on the substrate.
The n ⁺ -type a-Si layer 7 and a metal film 8 for a source / drain electrode made of a chromium (Cr) film having a thickness of 1500 ° are continuously formed.

In FIG. 1D, the contact layer 7 and the metal film 8 for source / drain electrodes are patterned to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C.

In FIG. 1E, a 4000 nm thick SiN film is deposited as the second insulating film 9 by the P-CVD method. Next, a resist film 10 having an opening above the source electrode and the storage capacitor is formed on the substrate by photolithography.

At this time, an opening is formed on the storage capacitor as an address display pattern AD in the shape of a numeral (or a symbol, a character, or the like) (see FIG. 2). 1F, using the resist film 10 as a mask, the second insulating film 9 is etched to form a contact hole, and the resist film 10 is removed. At this time, the resin on the connection terminals is also removed by etching.

At this time, a contact hole having a shape such as a number indicating an address is formed on the storage capacitor. Next, an ITO film having a thickness of 700 mm is formed as a pixel electrode film, and the storage capacitor upper electrode 8C and the source electrode 8S are contacted and patterned to form the pixel electrode 11, thereby forming a TFT matrix.

FIG. 2 is a plan view of the embodiment (1). Embodiment (2): FIGS. 3A and 3B are cross-sectional views of an embodiment (2) of the present invention.

These figures are views showing a cross-sectional structure of a gate bus line. FIG. 3A shows a manufacturing process in the embodiment (1). At the same time when the source and drain electrodes are formed, a pattern such as a numeral (metal film / n ⁺ type a-Si layer / a (Comprising -Si layer).

FIG. 3B shows a manufacturing process in the embodiment (1). At the same time when the pixel electrode 11 is formed, a pattern such as a numeral (made of an ITO film) is formed on the gate bus line as the address display pattern AD. This is an example.

FIG. 4 is a plan view of the embodiment (2). Embodiment (3): FIG. 5 is a sectional view of an embodiment (3) of the present invention.

This figure shows a sectional structure of the drain bus line. In the manufacturing process in the embodiment (1), the pixel electrode 11
This is an example in which a pattern such as a numeral (comprising an ITO film) is formed as an address display pattern AD on the drain bus line at the same time when the pattern is formed.

FIG. 6 is a plan view of the embodiment (3).

[0034]

According to the present invention, the address display of the TFT matrix can be provided for each pixel without lowering the transmittance, and it is possible to specify a specific pixel such as a defect.

The effects of the embodiment are listed as follows. (1) When an address pattern such as a metal film is provided outside a light-shielding film such as a storage capacitor as in the related art, the transmittance is reduced, but is not reduced in the embodiment. (2) In the case of using an automatic inspection device, a pattern defect is detected in the conventional example, but such an erroneous detection is not performed in the embodiment. (3) In the embodiment, a specific pixel can be seen even if the substrate is cut to any size. (4) By combining the embodiment with the conventional address display provided outside the display unit, the specific pixel can be more easily seen.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment (1) of the present invention.

FIG. 2 is a plan view of an embodiment (1) of the present invention.

FIG. 3 is a sectional view of an embodiment (2) of the present invention.

FIG. 4 is a plan view of an embodiment (2) of the present invention.

FIG. 5 is a sectional view of an embodiment (3) of the present invention.

FIG. 6 is a plan view of an embodiment (3) of the present invention.

FIG. 7 is a plan view of a TFT matrix.

FIG. 8 is an explanatory diagram of a method of representing a pixel address according to the conventional example (1).

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a conventional TFT element.

[Explanation of symbols]

1 Glass substrate with transparent insulating substrate 2 Gate electrode 3 Lower electrode of storage capacitor 4 First layer insulating film (gate insulating film and dielectric film of storage capacitor) SiN film 5 Working semiconductor layer a-Si film 6 Channel protective film 7 n ⁺ type a-Si layer as contact layer 8 metal film for source drain electrode and storage capacitor upper electrode 8D drain electrode 8S source electrode 8C storage capacitor upper electrode 9 SiN film as second insulating film 10 resist film 11 ITO film with pixel electrode 41 Gate bus line 42 Drain bus line 43 TFT

Claims (5)

(57) [Claims] 1. A gate bus line (41) and a drain bus line (42) are arranged in a matrix with an insulating film interposed therebetween.
A thin-film transistor (43) is arranged at the intersection of both bus lines, and the thin-film transistor is formed on a transparent insulating substrate (1) by a gate electrode (2), a storage capacitor lower electrode (3), and a first film serving as a gate insulating film. A layer insulating film (4) and a working semiconductor layer (5) are laminated in this order, and a channel protective film (6) is formed on the working semiconductor layer.
A source electrode (8S) and a drain electrode (8D) are arranged through the first electrode, and the first electrode serving as a dielectric film is formed on the lower electrode of the storage capacitor.
The storage capacitor upper electrode (8C) is formed via the layer insulating film,
A contact hole connected to the upper electrode of the storage capacitor and the source electrode is provided in the second insulating film deposited thereon, a pixel electrode is formed including the contact hole, and the drain electrode is formed of the drain electrode. A thin film transistor matrix in which a gate electrode is connected to the gate bus line in a bus line, and an address display pattern of pixel coordinates is provided on a light shielding film of a display unit. 2. The method according to claim 1, wherein the address display pattern is formed on a storage capacitor, a gate bus line, or a drain bus line.
The thin-film transistor matrix as described. 3. A gate electrode on a transparent insulating substrate (1).
(2) and a storage capacitor lower electrode (3) are formed, on which the first insulating film (4), the active semiconductor layer (5), and the channel protective film (6)
A second step of sequentially patterning the channel protective film so as to leave the channel protective film immediately above the gate electrode, and a contact made of a high-concentration semiconductor on the substrate. A third step of sequentially forming a layer (7) and a metal film for a source / drain electrode (8), and then patterning the working semiconductor layer, the contact layer and the metal film for a source / drain electrode to form a drain electrode ( 8D), the source electrode (8S), and the fourth electrode forming the storage capacitor upper electrode (8C).
And a fifth step of depositing a second-layer insulating film (9) on the substrate, and then contacting the second-layer insulating film on the source electrode and the storage capacitor upper electrode. A sixth step of forming a hole and forming a contact hole on the storage capacitor upper electrode in an address display pattern of pixel coordinates, and then forming a transparent electrode film on the substrate to form the storage capacitor upper electrode. And the source electrode are brought into contact with the transparent electrode film, and the transparent electrode film is patterned to form a pixel electrode.
And (7) forming a thin film transistor matrix. 4. The method according to claim 4, wherein, instead of forming the address display pattern in the sixth step, in the fourth step,
4. The method according to claim 3, wherein the address display pattern is formed by patterning the active semiconductor layer, the contact layer, and the source / drain electrode metal film on a gate bus line. 5. The method according to claim 6, wherein, instead of forming the address display pattern in the sixth step, in the seventh step,
4. The method according to claim 3, wherein the address display pattern is formed by patterning the transparent electrode film on a gate bus line or a drain bus line.