JP3240881B2 - Output buffer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer used in a MOS integrated circuit.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing a configuration of an output buffer in a conventional MOS integrated circuit. Input signal IN
Is the NAN controlled by the output enable signal OEN.
P of the output stage via D gate G1 and NOR gate G2
The data is transferred to the MOS transistor and the NMOS transistor. That is, when the output enable signal OEN is at the H level, one of the outputs of the NAND gate G1 and the NOR gate G2 becomes "H" and the other becomes "L" according to the "H" and "L" of the input signal IN. , The PMOS transistor or the NMOS transistor is turned on.

When a plurality of output buffers as described above are simultaneously turned on and off in a MOS integrated circuit, simultaneous switching noise becomes a problem. This will be described with reference to FIG. When the outputs of the three output buffers 51 to 53 shown in FIG.
Current flows into the MOS transistor. These currents are applied to the common ground line V _SS in the integrated circuit, as shown in FIG.
And flows out to the outside. At this time, the inductance component, such as package leads and the bonding wires, electromotive force is generated, which results in an increase in V _SS potential. FIG. 9 shows the voltage waveform. The rise of the V _SS potential indicated by the broken line raises the “L” level potential of the output voltage V _out , that is, a so-called ground bounce occurs.

[0004]

As described above, simultaneous switching noise is caused by the back electromotive force -Ldi / dt caused by a steep current change. It is desired to reduce the current and make the current change gradual. But,
There are limits to reducing stray inductance. Simply slowing down the change in current will impair high speed performance.

An object of the present invention is to provide an output buffer capable of suppressing simultaneous switching noise without impairing high-speed performance.

[0006]

According to the present invention, there is provided an output buffer having a driver MOS transistor having a drain connected to a signal output terminal and a gate connected to a signal input terminal. different that juxtaposed at least two elements transistors and is configured by arranging at a position closer to the signal input end of the small first element transistor driving capability for large second element transistor driving capability,
The first and second element transistors are formed in one active layer.
A gate electrode is formed continuously, and the source and drain are
Each of which is formed in a shared manner,
The gate electrode width of the elementary transistor is the second element transistor
Signal delay at the gate electrode
Drives the first and second element transistors in this order.
It is characterized by being made to be.

In the present invention, preferably, one activity
The drive of the first and second element transistors formed in the layer
In order to make the dynamic ability different, (a) first and second element
Changing the gate electrode width stepwise between transistors
Or (b) between the first and second element transistors
The gate electrode width is gradually changed.

[0008] In the present invention, preferably, dry
A MOS transistor has an interconnect in one active layer.
The first and second gates have a digital gate electrode structure.
It is configured by arranging multiple element transistors
Shall be.

[0009]

According to the output buffer of the present invention, one driver MOS transistor has a structure in which element transistors having different driving capacities are juxtaposed, and a first element transistor having a smaller driving capacity is replaced with a second element transistor having a larger driving capacity. It is arranged at a position near the signal input terminal with respect to the transistor. Therefore, when the driver MOS transistor is turned on, the first element transistor is turned on first, and the second element transistor is turned on after a predetermined time delay due to the gate electrode wiring resistance. Thus, the rise of the current change can be made gentle.

It is possible to vary the driving capability of the element transistors by varying the gate electrode width, and thus the channel length. If the channel length is large, g
A transistor having a small m and a small driving capability is obtained. Therefore, if the gate electrode width is reduced stepwise in order from the one closer to the signal input terminal, the element transistors will be arranged in ascending order of driving capability. If the gate electrode width is continuously reduced, there is no boundary as an element transistor, but this may be used.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a layout showing a configuration of an output buffer according to an embodiment of the present invention.

The output buffer includes a driver NMOS transistor 1 and a driver PMOS transistor 2 in an output stage in which a drain is connected to a signal output terminal and a gate is connected to a signal input terminal. The output stage MOS transistors 1 and 2 have an interdigital gate electrode structure. That is, the output stage NMOS transistor 1 has a structure in which six NMOS transistors are connected in parallel by arranging six comb-shaped gate electrodes in one active layer. The output stage PMOS transistor 2 also
The same is true.

The output stage NMOS transistor 1 has two element transistors Q _{N11 to} Q _N61 and Q _{N12 having} different gate electrode widths when viewed along each comb-shaped gate electrode.
~ Q _N62 . The first element transistors Q _{N11 to} Q _N
N61 is located closer to the signal input terminal to the second element transistor Q _N12 to Q _N62.

FIG. 2 shows an output stage NMOS according to the embodiment.
FIG. 2 is a cross-sectional view of the transistor 1 along AA ′. Output stage NMO
The S transistor 1 diffuses a p-type impurity into an n-type silicon substrate 10 to form a p-well 11 as an active layer, and then forms a gate electrode 13 of polycrystalline silicon or the like via a gate oxide film 12, Further, it is obtained by forming an n-type region serving as the source 14 and the drain 15 by ion implantation or the like. The source 14 is commonly V _SS and the drain 15
Are commonly connected to a signal output terminal OUT. The gate electrode width of the first element transistors Q _{N11 to} Q _N61 , that is, the channel length L1 is determined by the second element transistors Q _{N12 to} Q _N62.
Is larger than the gate electrode width L2 of
Of the element transistors Q _{N11 to} Q _N61 of the second
Of the element transistors Q _{N12 to} Q _N62 .

The output stage PMOS transistor 2 does not show a sectional structure, but is formed with a similar structure in one n-type active layer. The output stage PMOS transistor 2 also has the first
For elements transistor Q _P11 to Q _P61 and the output stage NMOS transistor 1 second element transistor Q _P12 to Q _P62 is described above and is similarly constructed of the driving capability of the first element transistor Q _P11 to Q _P61 is , The second element transistors Q _{P12 to} Q _P62 .

FIG. 3 is an equivalent circuit diagram of the output stage NMOS transistor 1 of the output buffer of the embodiment. The first element transistors Q _{N11 to} Q _N61 forming a pair and the second
A resistor R formed by a polysilicon gate electrode wiring is provided between the gates of the element transistors Q _{N12 to} Q _N62 .

Next, the operation of the output buffer configured as described above will be described. When the input signal IN becomes “H”, in the output-stage NMOS transistor 1, the first element transistor Q having a small driving capability in the first column shown in FIG.
_N11 to Q _N61 are turned on, followed by a large second element transistor of the driving capability of the second row with a delay of a predetermined time, the resistor R Q
_{N12 to QN62} are turned on. For this reason, the rise of the drawn current becomes gentle. When the input signal IN becomes “L”,
The same applies when the output stage PMOS transistor 2 is turned on, and the rising of the supply current becomes gentle.

As described above, according to this embodiment, the rise of the current of the output buffer becomes gentle, and the simultaneous switching noise is reduced. Since the output change is initiated by an element transistor having a small driving capability, the high-speed performance is not impaired as a whole.

FIG. 4 is a layout of an output-stage NMOS transistor showing the configuration of an output buffer according to another embodiment. In this embodiment, the output-stage NMOS transistor 1 is composed of three element transistors (Q _N11 , Q _N12 , Q _N13 ), (Q _N21 , Q _N22 , Q N3) having different gate electrode widths.
_N23 ),…. FIG. 5 is an equivalent circuit diagram thereof.

According to this embodiment, the same effect as in the previous embodiment can be obtained. Similarly, n having different gate electrode widths
The element transistors may be provided in parallel.

FIG. 6 is a layout showing a configuration of an output buffer according to still another embodiment. In this embodiment, the gate electrode widths of the transistors Q _{N1 to} Q _N6 along each comb-shaped gate electrode of the output stage NMOS transistor 1 are continuously reduced from the side closer to the signal input terminal IN of the gate electrode. I have. Therefore, each transistor does not have a boundary as an element transistor as in the previous embodiment, but the rise of current can be made gentle like the previous embodiment.

[0022]

As described above, according to the output buffer of the present invention, simultaneous switching noise can be reduced without impairing high-speed performance by combining element transistors having different driving capacities and making the current rise slow. It can be reduced effectively.

[Brief description of the drawings]

FIG. 1 is a layout showing a configuration of an output buffer according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of an output-stage NMOS transistor in the same embodiment.

FIG. 3 is an equivalent circuit diagram of an output stage NMOS transistor of the output buffer of the embodiment.

FIG. 4 is a layout of an output-stage NMOS transistor showing a configuration of an output buffer in another embodiment.

FIG. 5 is an equivalent circuit diagram of an output-stage NMOS transistor of the output buffer of the embodiment.

FIG. 6 is a layout showing a configuration of an output buffer according to still another embodiment.

FIG. 7 is a circuit diagram showing a configuration of a conventional output buffer.

FIG. 8 is a circuit diagram showing an application example of a conventional output buffer.

FIG. 9 is a diagram for explaining the occurrence of simultaneous switching noise.

[Explanation of symbols]

1: output stage NMOS transistor, 2: output stage PMOS
Transistors, 10: n-type silicon substrate, 11: p well, 12: gate oxide film, 13: gate electrode, 14: source, 15: drain, 51 to 53: output buffer. G
1 ... NAND gate, G2 ... NOR gate, IN ... input signal, L1, L2 ... gate electrode width, Q _N11 ~Q _N61, Q
_{P11 to} Q _P61 ... first element transistors, Q _{N12 to} Q _N
N62 , Q _{P12 to} Q _P62 ... second element transistors, R,
R1, R2 ... resistance.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-357712 (JP, A) JP-A-4-79371 (JP, A) JP-A-2-18823 (JP, A) JP-A-2- 203618 (JP, A) JP-A-3-204223 (JP, A) JP-A-4-180310 (JP, A) JP-A-4-165669 (JP, A) JP-A-5-206810 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70 H01L 27/04 H03K 19/00

Claims (4)

(57) [Claims] 1. A lead to a drain signal output terminal, the output buffer having a driver MOS transistor having a gate connected to the signal input terminal, said driver MOS transistor, that Do different driving capability
At least two factors transistors arranged side by side and is constructed by arranging at a position closer to the signal input end of the small first element transistor driving capability for large second element transistor driving capability, the first , The second element transistor is in one active layer
A gate electrode is formed continuously, and the source and drain are
Each of which is formed in a shared manner,
The gate electrode width of the elementary transistor is the second element transistor
Signal delay at the gate electrode
Drives the first and second element transistors in this order.
An output buffer characterized in that the output buffer is adapted to be used . 2. The output buffer according to claim 1, wherein a gate electrode width is changed stepwise between the first and second element transistors. 3. The output buffer according to claim 1, wherein a gate electrode width is gradually changed between said first and second element transistors. 4. The driver MOS transistor according to claim 1, wherein a plurality of said first and second element transistors are arranged in an active layer with an interdigital gate electrode structure. The output buffer according to claim 1.