JP3240231B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device formed on a semiconductor layer on an insulating surface.

[0002]

2. Description of the Related Art Conventionally, Bi has been used as a means for increasing the speed of an IC.
-CMOS is used, and it is used for a decoder section such as a DRAM. FIG. 37 shows a typical circuit diagram. However, in the case of forming a Bi-CMOS on bulk Si, device isolation, a CMOS process, and a vertical bipolar process are performed, so that the process becomes very complicated, the yield is reduced, and the cost is increased.

On the other hand, SOI (Silicon O)
Research on forming a Bi-CMOS on an n-insulator has been conducted. Fabrication on an SOI substrate enables dielectric isolation, and element isolation can be performed very easily as compared with bulk Si. In addition, I
Although depending on C, research using a lateral bipolar transistor has been conducted. Although the performance of the horizontal bipolar transistor is lower than that of the vertical bipolar transistor, most of the process can be shared with the CMOS process. Furthermore, because of the SOI structure, it is possible to eliminate the external base of the emitter-base results in degradation of the h _FE, characteristics are improved.

On the other hand, a MOS transistor formed on an SOI substrate suppresses a short channel effect and is suitable for miniaturization of elements, and Bi-CMOS on an SOI substrate is expected to be promising. However, as the miniaturization progresses, the element breakdown voltage,
Low voltage is inevitable in terms of power consumption and the like. For example, when the gate length is smaller than 0.8 μm, the power supply voltage needs to be 3.3 volts.

In a bipolar transistor, the emitter
As for the potential difference between the bases, V _BE does not become 0 volt, and at least about 0.6 to 0.7 volt is generated.

As a result, as shown in the input / output relationship shown in FIG. 38, the amplitude of the transferred signal is reduced by 1.2 to 1.4 volts from the power supply voltage of 3.3 volt, and the effective voltage for driving is 1.9 to 2.1 volt.

That is, at a low voltage, there is a serious problem that the driving force of the Bi-CMOS is extremely deteriorated. In the case where a low-voltage IC used in a portable product or a further reduction in power supply voltage is required due to miniaturization, at present, only a MOS circuit can be used.

The present inventors have provided a control electrode via a oxide film on a base region of a conventional SOI lateral bipolar transistor as a bipolar transistor which is turned on even at a low voltage, and further provided a control electrode, an emitter, a base, A lateral bipolar transistor (hereinafter, referred to as a lateral bipolar transistor with a control electrode) driven by connecting the base and the control electrode electrically so that the base region in contact with the oxide film is in a weak inversion state with the collector grounded. Already proposed.

In the manufacturing method, as shown in FIG. 39, the base region 806 is masked with the control electrode 808, and the emitter region 809 and the collector region 810 are formed by ion implantation. It is determined. In FIG. 39, reference numeral 801 denotes a base insulating film, and 802 denotes a semiconductor layer.

[0010]

However, since the practical base width is 300 nm or less, in order to realize a lateral bipolar transistor with a control electrode in the above manufacturing process, an exposure technique of 0.3 μm or less is required. For example, a control electrode made of, for example, polycrystalline silicon must be processed. Therefore, a fine processing process including the most advanced exposure technology is required, and improvement is desired in view of cost.

[0011]

According to a method of manufacturing a semiconductor device of the present invention, an emitter region, a base region, and a collector region of a lateral bipolar transistor are formed in a semiconductor layer formed on an insulating surface, and the semiconductor layer is formed via an insulating film. A method of manufacturing a semiconductor device comprising forming a control electrode for controlling the potential of the base region by using at least the following steps (A) to
(E) A method for manufacturing a semiconductor device, comprising:

(A) A first insulating film region and a second insulating film region thicker than the first insulating film region are formed on a first conductive type semiconductor layer provided on the insulating surface. (B) a step of introducing and activating a second conductivity type impurity under the first insulating film region by using the second insulating film region as a mask; and (C) forming the first and second impurities. A conductive film is deposited on the insulating film region, and a sidewall conductive film deposited on a step side wall portion between the first insulating film region and the second insulating film region to be at least immediately above the base region by anisotropic etching. Forming a control electrode while leaving a film; (D) introducing and activating a first conductivity type impurity using the control electrode and the second insulating film region as a mask to form an emitter region and a collector extraction electrode region; (E) Pulling of the control electrode and the base region Step of Electrically Connecting to Outgoing Electrode (Example of Embodiment) Hereinafter, the present invention will be described based on an example of an embodiment.

FIG. 1 is a cross-sectional view showing the structure of a lateral bipolar transistor with a control electrode manufactured by the method of manufacturing a semiconductor device according to the present invention. FIGS. FIG. 7 is a cross-sectional view showing a manufacturing process of the lateral bipolar transistor with electrodes.

Here, the structure of an NPN-type lateral bipolar transistor with a control electrode and a method of manufacturing the same will be described.

In FIG. 1, reference numeral 101 denotes an insulating substrate;
Is an N-type semiconductor layer, and 103 is a film thickness T _ox2Second insulating film
The regions 104 and 105 have a film thickness T_ox1(T_ox1<T_ox2)
The first insulating film region 106 is a P-type region serving as a base region.
Area, 108 is a side wall, 109 and 110 are
N-type high-concentration areas that serve as
Area. Horizontal bipolar transistor with control electrode according to the present invention
Transistor uses sidewall 108 as control electrode
Have been.

Next, a description will be given of a method of manufacturing the lateral bipolar transistor with a control electrode having the above configuration.

[0017] First, as shown in FIG. 2, on the semiconductor layer 102 of N-type on the insulating substrate 101, a first insulating film region 104 of the second insulating film region 103 and the thickness T _ox1 a thickness T _ox2 ,
105 is provided. At this time, T _ox1 and T _ox2 satisfy the following relationship.

T _ox1 <T _ox2 Next, as shown in FIG. 3, using the second insulating film region 103 as a mask, a P-type impurity such as boron is ion-implanted to form a P-type region 106. The P-type region 106
Is a base region, and this ion implantation determines the base concentration of the lateral bipolar transistor. Therefore, the concentration of the P-type region 106 is preferably 1E17 cm ⁻³ or more.

Thereafter, a conductive film 107 such as polycrystalline silicon having a high impurity concentration is deposited (FIG. 4), and a sidewall 108 is formed by anisotropic etching (FIG. 5). At this time, the sidewall on the collector electrode side is removed. For example, the resist can be removed by etching only by providing a resist on the base side. Since the width of the second insulating film region 103 may be about 1 μm, it can be sufficiently processed by a micron-order exposure technique.

Next, using the side wall 108 and the second insulating film region 103 as a mask material, N-type high concentration regions 109 and 110 are formed by ion implantation (FIG. 6). In FIG. 6, 109 is an emitter region, 110 is a collector extraction electrode region, and 106 is a base region. Since the base width is determined by the width of the sidewall 108, a base width of 0.3 μm or less can be realized without using a fine exposure technique. Further, since the side wall serving as the control electrode is used as a mask, the control electrode can be formed immediately above the base region in a self-aligned manner. As a result, the capacitance between the control electrode and the emitter can be reduced. Further, since the second insulating film region 103 exists, the capacitance with the collector can be reduced.

There are several possible means for electrically coupling the control electrode and the base extraction electrode.
It can be realized by doing as follows. FIG. 7A is a perspective view showing a connected state, and FIG. 7B is a plan view. In the figure, 111 is a metal wiring such as aluminum, and 112 is a lead electrode of the base. Reference numeral 113 denotes a boundary line of element isolation such as a selective oxidation portion edge. 114 is the base region 10
6 is a region having the same concentration as that of the base extraction electrode 11.
2 is in the high concentration P-type impurity region 114. A metal film is deposited on a part of the side wall 108, the potential of the control electrode is taken, and the control electrode and the base extraction electrode are connected by the metal film.

[0022]

According to the present invention, by including at least the above-described steps according to the present invention in the device manufacturing process, the side wall portion is used as a control electrode, and the base region is formed in a self-aligned manner immediately below the control electrode. The purpose of the present invention is to manufacture a lateral bipolar transistor with a control electrode having a width of 0.3 μm or less, a low-voltage, high-drive device having an inexpensive process without using a fine exposure processing technique.
It is possible to manufacture a lateral bipolar transistor with a control electrode of 3 μm or less.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) This embodiment will be described with reference to FIGS.

First, the underlying silicon oxide film 201 on the silicon substrate 200 has a thickness of 400 nm and the silicon layer 202
SIM with a film thickness of 200 nm and a substrate concentration of 2E15 cm ^-3
Complete dielectric isolation between the elements was performed on the OX substrate by a selective oxidation separation method. Next, a thermal oxide film 204 having a thickness of 10 nm is formed on the substrate (FIG. 8).
Thereafter, a 500 nm NSG film 203 was deposited and partially removed (FIG. 9). R1 in FIG. 9 indicates a resist film. In the figure, the width of the second insulating film region 203 was about 1 μm. After removing the resist film R1, thermal oxidation was performed again to form a 10-nm silicon oxide film (FIG. 10). FIG.
At 0, 205 is the first insulating film region (thickness T _ox1 )
And the NSG film 203 + the thermal oxide film 204 is a second insulating film region (thickness T _ox2 ). At this time, T _ox1 = 10n
m, T _ox2 = 510 nm, and satisfies T _ox1 <T _ox2 .

As shown in FIG. 11, boron ions were implanted using the second insulating film region (203 + 204) as a mask to form a P-type impurity region 206 corresponding to the base concentration. The ion implantation was performed under the following conditions: ion species: B ¹¹⁺ / implantation energy: 70 KeV / dose: 5E12 cm ⁻² . As a result, the impurity concentration of the P-type region 206 became 4E17 cm ⁻³ .

Next, as shown in FIG. 12, a polycrystalline silicon film is deposited to a thickness of 400 nm, and phosphorus is dosed at 8E15 cm.
^-2 / Ion implantation at an implantation energy of 70 KeV to form a polycrystalline silicon conductive film 207. Only the polycrystalline silicon on the side walls was left by anisotropic etching to form side walls 208 and 208 '(FIG. 13). Then, FIG.
As shown in FIG. 4, the side wall 208 on the base portion was covered with the resist R2, and the side wall 208 'on the collector electrode side was removed to form a structure as shown in FIG. Reference numeral 213 in FIG. 14 denotes a selective oxidized portion edge. At this time, the thickness of the side wall was about 260
nm.

Next, as shown in FIG. 16, an element portion was opened with a resist R3, and ion implantation of an emitter / collector electrode was performed using the side wall 208 and the second insulating film region 203 as a mask. The ion implantation conditions are ion species: A
s / implantation energy: 150 KeV / dose: 5E1
It was 5 cm ^-2 . In order to form a base electrode, FIG.
As shown in FIG. 8, except that a part of the base region is opened, the base region is covered with a resist R4 and boron is implanted at an energy of 20K.
The ion implantation was performed under the condition of eV / dose amount: 1E15 cm ⁻² . After the ion implantation, a heat treatment was performed at 1000 ° C. for 10 minutes in a nitrogen atmosphere to activate the impurities. As a result, the structure shown in FIG. 17 was formed. In the figure, a P-type impurity region 206 is a base region, a high-concentration N-type impurity region 209 is an emitter region, and a high-concentration N-type impurity region 210 is a collector extraction electrode region. The base width was determined by the thickness of the sidewall, and was about 260 nm in this example.

Next, in order to electrically connect the control electrode and the base lead electrode, a contact 212 for taking the base lead electrode was opened. After depositing Al by sputtering, as shown in FIG.
The wiring 211 was formed. PSG 50 as interlayer insulating film
After depositing 0 nm, a contact hole was opened in order to take each electrode of the emitter, base and collector, and then a second layer of Al was deposited by 800 nm by sputtering and patterned to form electrodes and wiring. FIG. 19 is a plan view thereof. In the figure, 215, 216, and 217 are contact holes for the emitter, base, and collector electrodes, respectively, and 218, 219, and 220 are the second-layer Al wirings for the emitter, base, and collector electrodes. (Embodiment 2) This embodiment will be described with reference to FIGS.

A SIMOX substrate having a substrate concentration of 2E15 cm ^{-3 with} a thickness of the underlying silicon oxide film 301 on the silicon substrate 300 of 400 nm and a thickness of the silicon layer 302 of 200 nm was completely separated by selective oxidation. Dielectric separation was performed. Next, a 10 nm thermal oxide film 305 is formed on the substrate, a 10 nm silicon nitride film 304 is deposited thereon, and an NSG film 3 is further formed thereon.
03 was deposited to a thickness of 500 nm (FIG. 20). NSG film 303
Was partially removed to form a second insulating film region 303 (FIG. 21). In the figure, R1 indicates a resist film, and the width of the second insulating film region 303 was about 1 μm. The resist R1 is removed, and boron ions are implanted using the second insulating film region 303 as a mask, as shown in FIG.
A P-type impurity region 306 corresponding to the base concentration was formed.

Thereafter, by the same process as in the first embodiment,
The sectional structure and the planar structure shown in FIGS. 23 and 24 were formed.

In each figure, 309, 306, 310
Are the emitter, base, and collector regions, respectively. The control electrode 308 immediately above the base region 306 is made of a polysilicon sidewall, and has a width of about 260 n.
m. Therefore, the base width of this embodiment is also about 260 n.
m. 313 is the edge of the selective oxidation part,
Reference numeral 1 denotes an NSG interlayer insulating film.

Reference numeral 311 denotes a first-layer Al wiring connecting the control electrode and the base lead electrode.
Reference numeral 17 denotes a contact hole for leading each electrode of the emitter, base and collector, and 318, 319 and 320 denote 2 contact holes.
This is the Al wiring of the layer.

In the first embodiment, the oxide film near the control electrode located at the boundary between the first insulating film region and the second insulating film region is a discontinuous film, and many defects and the like occur. In some cases, some problems may occur in the leakage current and the withstand voltage. However, as a result of the film configuration shown in FIGS.
Since the insulating film interface near the control electrode is formed of a continuous film of a good thermal oxide film, the leakage current and the breakdown voltage of the insulating film could be improved. (Embodiment 3) This embodiment will be described with reference to FIGS.

The thickness of the underlying silicon oxide film 401 is 400
A SIMOX substrate having a thickness of 200 nm and a silicon layer 402 of 200 nm and a substrate concentration of 2E15 cm ^-3 was subjected to complete dielectric isolation between elements by a selective oxidation separation method. Next, a thermal oxide film 404 is formed on this substrate by 10 n.
m on which a silicon nitride film 403 is formed to a thickness of 600 nm.
Deposited and partially removed to form the structure shown in FIG. As in the first and second embodiments, a P-type region 406 corresponding to the base impurity concentration was formed by boron ion implantation.

Next, polycrystalline silicon was deposited by the CVD method, but the partial pressure of HCl as an etching gas was adjusted so that polycrystalline silicon could be more easily deposited on the silicon nitride film 403 than on the silicon oxide film 404. Deposition was performed below.
As a result, as shown in FIG. 26, the polycrystalline silicon on the silicon nitride film was thicker than on the silicon oxide film. First, sidewalls are formed by anisotropic etching.
The sidewall on the collector lead-out electrode region side was removed in the same manner as in the second embodiment. As a result, the structure shown in FIG. 27 was formed. Since the polycrystalline silicon on the silicon nitride film is thicker than the polycrystalline silicon on the silicon oxide film, the polycrystalline silicon remains on the silicon nitride film.

Thereafter, the sectional structure and the planar structure shown in FIGS. 28 and 29 were formed by the same process as in the first and second embodiments.

In each figure, 409, 406, 410
Are the emitter, base, and collector regions, respectively. The control electrode 408 immediately above the base region 406 is formed of a polysilicon sidewall, and has a width of about 260 n.
m. Therefore, the base width of this embodiment is also about 260 n.
m. Reference numeral 413 denotes an edge of the selective oxidation portion.
Reference numeral 21 denotes an NSG interlayer insulating film.

Reference numeral 411 denotes a first-layer Al wiring connecting the control electrode and the base lead electrode, and 415, 416, 41
Reference numeral 7 denotes a contact hole for leading each electrode of the emitter, base, and collector. Reference numerals 418, 419, and 420 denote second-layer Al wirings.

In the first and second embodiments, the control electrode has a high resistance. However, in this embodiment, a silicon nitride film is used for the second insulating film region 403, and a polycrystalline silicon which is a conductive film is used. Of silicon nitride film 4
The conductive film was also left on 03. As a result, the resistance could be made smaller than the resistance of the control electrode. Embodiment 4 In this embodiment, tungsten silicide is used for the control electrode, and the resistance of the control electrode is lower than that of the third embodiment. Hereinafter, this embodiment will be described.

FIG. 27 shows a process similar to that of the third embodiment.
The structure of was formed. After that, tungsten is deposited and H
Heat treatment was performed at 1000 ° C. for 20 minutes in an e-gas atmosphere. As a result, the side wall 408 of FIG.
It became ₂ . Except for the annealing conditions for activating the impurities in the emitter and collector, the same process as in the third embodiment was used. The heat treatment condition for activating the impurities in the emitter and collector was 900 ° C./30 minutes in a He gas atmosphere.

According to this embodiment, it is possible to form a control electrode having a resistance about one order of magnitude smaller than that of the third embodiment.
C characteristics are improved. Embodiment 5 In this embodiment, a bipolar transistor with an NPN control electrode and a CMOS circuit are simultaneously manufactured. Hereinafter, this embodiment will be described with reference to FIGS.

The thickness of the underlying silicon oxide film 501 is 400
For a SIMOX substrate having a thickness of 200 nm and a silicon layer 502 of 200 nm and a substrate concentration of 2E15 cm ^-3 , complete dielectric separation between elements was performed by a separation method using selective oxidation. Next, after forming a mask oxide of 10 nm, using a resist mask having an opening only in the region where the N-type MOS transistor of the CMOS circuit is formed, the dose amount is 8E11c.
Boron ions of m ⁻² and implantation energy: 20 KeV were implanted to form a P-type region with a substrate concentration of 3E16 cm ⁻³ . Similarly, using a resist mask having an opening only in a region where a P-type MOS transistor of a CMOS circuit is formed,
Dose amount: 4E11 cm ^-2 , implantation energy: 60 Ke
V phosphorus ion implantation was performed to form an N-type region of 1E16 cm ⁻³ .

Next, a thermal oxide film 504 is formed on the substrate.
Was formed to a thickness of 10 nm. FIG. 30 shows a cross-sectional structure after a thermal oxide film is formed. The left side of the figure is a lateral bipolar transistor section with a control electrode, and the right side is a CMOS section (N-type M).
FIG. 3 is a schematic diagram for both an OS transistor and a P-type MOS transistor). On top of this, a silicon nitride film 503 is
m was deposited, and only the silicon nitride film 503 in the lateral bipolar transistor region with the control electrode was partially removed to form the structure shown in FIG. As in the first and second embodiments, a P-type region 506 corresponding to the base impurity concentration was formed by boron ion implantation. Since the CMOS region is masked with the silicon nitride film 503, this boron is not ion-implanted.

Only the bipolar transistor region with the control electrode was covered with a resist mask, the silicon nitride film 503 in the CMOS region was removed, and polycrystalline silicon was deposited by the CVD method as in the third embodiment. That is, the partial pressure of HCl as an etching gas was adjusted, and deposition was performed under conditions where polycrystalline silicon was more likely to be deposited on the silicon nitride film 503 than on the silicon oxide film 504. As a result, as shown in FIG. 32, the polycrystalline silicon on the silicon nitride film was thicker than on the silicon oxide film.

As in the first, second, and third embodiments, phosphorus was ion-implanted into the polycrystalline silicon to increase the conductivity of the polycrystalline silicon.

Next, the CMOS region was covered with a resist mask, and side walls were formed in the lateral bipolar transistor region with control electrodes by anisotropic etching. CM
Since the polycrystalline silicon in the OS region is covered with the resist mask, it remains as it is (FIG. 33). Next, FIG.
By using the resist R1 as a mask, the side wall on the collector side of the lateral bipolar transistor with a control electrode was removed and a CMOS gate electrode 508 'was formed as shown in FIG. Next, an emitter-collector portion in a lateral bipolar transistor region with a control electrode and an N-type MO in a CMOS region
N-type impurities were ion-implanted using a resist mask having openings in the source / drain portion of the S transistor and the channel electrode portion of the P-type MOS transistor. The ion implantation conditions are as follows: ion species: As / implantation energy: 150 Ke
V / dose amount: 5E15 cm ^-2 . As a result, FIG.
5, an emitter region 510, a collector extraction electrode region 510, and a source region 50 of an N-type MOS transistor.
9 ', the drain region 510', and the channel electrode of the P-type MOS transistor were formed. After the removal of the resist, a new resist film is formed with openings in the base electrode portion of the lateral bipolar transistor region with the control electrode, the channel electrode portion of the N-type MOS transistor in the CMOS region, and the source / drain portion of the P-type MOS transistor. : 2
0 KeV / dose amount: boron ion implantation of 1E15 cm ^-2 was performed. As a result, a high concentration impurity region of each electrode was formed. After the resist was stripped, a heat treatment was performed at 1000 ° C. for 10 minutes in a nitrogen atmosphere to activate the impurities. As a result, the structure shown in FIG. 35 was formed.

As shown in FIG. 36, similarly to the third embodiment, after electrically connecting the control electrode and the base electrode, a 500 nm PSG film is deposited as an interlayer insulating film 521, and a lateral bipolar transistor with a control electrode is formed. Emitter 509
A base / collector electrode 510, an N-type MOS transistor, a source hole 509 'for a P-type MOS transistor, a drain 510', and a contact hole for drawing out a channel electrode were formed. A second layer of Al was deposited, and each electrode (5
18, 520, 518 ', 520', 519 ') and wiring. A PSG film of 500 nm was deposited as a passivation film 522, and a contact hole for a pad was opened.

[0048]

As described above, according to the present invention,
For example, 0.3 micron exposure processing technology
A lateral bipolar transistor having a control electrode of μm or less can be manufactured, and a bipolar transistor circuit that can be driven at a low voltage can be manufactured at low cost.

Further, the manufacturing method of the present invention is very close to a CMOS manufacturing process, and a Bi-CMOS circuit can be manufactured by an inexpensive manufacturing process as compared with a conventional Bi-CMOS circuit.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a configuration of a lateral bipolar transistor with a control electrode manufactured by a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a lateral bipolar transistor with a control electrode according to a method of manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing a step of manufacturing a lateral bipolar transistor with a control electrode according to the method of manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing a step of manufacturing a lateral bipolar transistor with a control electrode according to the method of manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing a step of manufacturing a lateral bipolar transistor with a control electrode according to the method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view showing a step of manufacturing a lateral bipolar transistor with a control electrode according to the method of manufacturing a semiconductor device of the present invention.

FIGS. 7A and 7B are a perspective view and a plan view showing a manufacturing process of a lateral bipolar transistor with a control electrode according to a method of manufacturing a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a cross-sectional view showing a manufacturing step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 14 is a plan view showing a manufacturing step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 15 is a sectional view showing a manufacturing step of the first embodiment of the method of manufacturing the semiconductor device of the present invention.

FIG. 16 is a plan view showing a manufacturing step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 17 is a cross-sectional view showing a manufacturing step of the first embodiment of the method of manufacturing the semiconductor device of the present invention.

FIG. 18 is a plan view showing a manufacturing step of the first embodiment of the method of manufacturing the semiconductor device of the present invention.

FIG. 19 is a plan view showing a manufacturing step of the first embodiment of the method of manufacturing the semiconductor device of the present invention.

FIG. 20 is a cross-sectional view showing a manufacturing step of the second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 21 is a cross-sectional view showing a manufacturing step of the second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 22 is a cross-sectional view showing a manufacturing step of the second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 23 is a cross-sectional view showing a manufacturing step of the second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 24 is a plan view showing a manufacturing step of a second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 25 is a cross-sectional view showing a manufacturing step of the third embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 26 is a sectional view illustrating a manufacturing step of a third embodiment of the method of manufacturing a semiconductor device according to the present invention;

FIG. 27 is a sectional view illustrating a manufacturing step of a third embodiment of the method of manufacturing a semiconductor device according to the present invention;

FIG. 28 is a sectional view illustrating a manufacturing step of a third embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 29 is a plan view showing a manufacturing step of the third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 30 is a cross-sectional view showing a manufacturing step of the fifth embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 31 is a sectional view showing a manufacturing step of the fifth embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 32 is a cross-sectional view showing a manufacturing step of the fifth embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 33 is a sectional view illustrating a manufacturing step of a fifth embodiment of the method of manufacturing a semiconductor device according to the present invention;

FIG. 34 is a cross-sectional view showing a manufacturing step of the fifth embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 35 is a cross-sectional view showing a manufacturing step of the fifth embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 36 is a cross-sectional view showing a manufacturing step of the fifth embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 37 is a typical Bi-CMOS circuit diagram.

FIG. 38 is a diagram showing a relationship between an input waveform and an output waveform of the Bi-CMOS circuit.

FIG. 39 is a sectional structural view of a conventional lateral bipolar transistor with a control electrode.

DESCRIPTION OF SYMBOLS 101 Insulating substrate 102 N-type semiconductor layer 103 Second insulating film region 104 First insulating film region 105 First insulating film region 106 P-type region (P-type region) 107 Conductive film 108 Side wall 109 N-type high-concentration region (emitter region) 110 N-type high-concentration region (collector extraction electrode region) 111 Metal wiring 112 Base extraction electrode 113 Element separation boundary line 114 P-type impurity region

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/73 (58) Investigation field (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 21/20 H01L 21/8249 H01L 21/84 H01L 27/06 H01L 29/73

Claims (1)

(57) [Claims] An emitter region, a base region and a collector region of a lateral bipolar transistor are formed on a semiconductor layer formed on an insulating surface, and a control electrode for controlling a potential of the base region is formed via an insulating film. A method of manufacturing a semiconductor device, comprising: at least the following steps (A) to (E). (A) Forming a first insulating film region and a second insulating film region thicker than the first insulating film region on a first conductivity type semiconductor layer provided on an insulating surface. Step (B) Step of introducing and activating a second conductivity type impurity under the first insulating film region using the second insulating film region as a mask (C) The first and second insulating film regions A conductive film is deposited thereon, and an anisotropic etching is performed to leave a sidewall conductive film deposited on a step sidewall portion of at least the first insulating film region and the second insulating film region to be immediately above the base region. Step of forming control electrode (D) Impurity of the first conductivity type is introduced and activated using the control electrode and the second insulating film region as a mask to form an emitter region and a collector extraction electrode region. Step (E) connecting the control electrode and the extraction electrode in the base region Electrical connection process