JP3197158B2 - Semiconductor memory device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an array structure composed of a plurality of memory cells functioning as a nonvolatile memory and a method of driving the same.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device having a nonvolatile memory cell mounted thereon, for example, Japanese Patent Application Laid-Open No. Hei 5-28778.
As disclosed in Japanese Unexamined Patent Application Publication No. Hei. 4-15953, a source decoder is also connected to a source line connected to a source of a memory cell constituting a nonvolatile memory cell. Hereinafter, a conventional semiconductor memory device equipped with a nonvolatile memory cell will be described with reference to FIGS. FIG. 31 is a block diagram showing a schematic configuration of a conventional semiconductor memory device. 101 is a memory cell array, 102 is a row decoder circuit, 103
Denotes a column decoder circuit, and 104 denotes a source decoder circuit. FIG. 32 is a circuit diagram showing a part of a memory cell array 101 of a conventional semiconductor memory device. Here, T11 to T
mn is a transistor built in the nonvolatile memory cell, W
1 to Wm are word lines, B1 to Bn are bit lines, S1 to S
m is a source line, and ST1 to STn are column selection transistors. As shown in FIG. 31, each of the transistors T11 to T11
mn is composed of a source, a drain and a gate, and a capacitor (floating gate) is arranged below the gates of the transistors T11 to Tmn to form a nonvolatile memory cell. The memory cell array 101 is configured by arranging memory cells containing the transistors T11 to Tmn in a matrix of m rows and n columns. The gates of the transistors T11 to T1n arranged in the first row are connected to the word line W1, the gates of the transistors T21 to T2n arranged in the second row are connected to the word line W2, and the transistors Tm1 to Tm1 arranged in the m-th row. The gates of Tmn are connected to word lines Wm, respectively. Further, the transistors T arranged in the first row
The sources of 11 to T1n are connected to the source line S1, the sources of the transistors T21 to T2n arranged in the second row are connected to the source line S2,
The sources of the transistors Tm1 to Tmn arranged in the m-th row are connected to the source lines Sm, respectively. Furthermore, the first
The drains of the transistors T11 to Tm1 arranged in the column are connected to the bit line B1, and the transistors T12 to Tm1 arranged in the second column.
The drain of Tm2 is connected to the bit line B2, and the drains of the transistors T1n to Tmn arranged in the n-th column are connected to the bit line Bn. That is, the word lines W1 to Wm
And a bit line B1 to Bn. Here, the word lines W1 to Wm and the source lines S1 to Sm extend in the same direction.
To Wm are the row decoders RD of the row decoder circuit 102.
1 to RDm, the source lines S1 to Sm are connected to the source decoders SD1 to SDm of the source decoder circuit 104, while the bit lines B1 to Bn are orthogonal to the word lines W1 to Wm and the source lines S1 to Sm. To the column decoder circuit 10 via the sense amplifiers SA1 to SAn.
3 is connected. As described later, paths P11 to Pmn from one part of each bit line B1 to Bn to each source line S1 to Sm via each transistor T11 to Tmn include:
When the potential of the gate is equal to or higher than the threshold and the potential between the drain and the source is equal to or higher than a predetermined value, the memory state of the capacitor is “1”.
, A current flows, and no current flows when the memory state of the capacitance section is “0”.

Next, a data reading method of a conventional semiconductor memory device will be described with reference to FIG. E
In a semiconductor memory device represented by an EPROM, writing and erasing are performed by greatly changing the threshold value of a transistor. Generally, a state in which a transistor is at a threshold voltage higher than the read power supply voltage Vcc is referred to as a "0" state, and a state in which a transistor is at a threshold voltage lower than the read power supply voltage Vcc is referred to as a "1" state. I will.

For example, a conventional reading method for reading a memory cell having a transistor T22 therein (hereinafter referred to as a memory cell (T22)) will be described. First,
The selected word line W2 is read and the power supply voltage Vcc (for example, 5
V) and the unselected word lines W1 and Wm are connected to the ground potential Vss.
(For example, 0 V). At the same time, the selected source line S2 is set to the ground potential Vss, and the unselected source lines S1 and Sm are read out to the intermediate potential Vrm (for example, 1 V), or are floated while being kept at the intermediate potential Vrm. Further, the selected bit line B2 is set to the intermediate potential Vrm via the sense amplifier,
The unselected bit lines B1 and Bn are set to the ground potential Vss, or are floated while being kept at the ground potential Vss. Actually, since the sense amplifier is connected to the bit line, the potential of the bit line slightly fluctuates from the intermediate potential Vrm. However, it is assumed here that the voltage is constant for the sake of simplicity. Although the unselected source line and the unselected bit line may be floated, for simplicity, the unselected source line is set at the read intermediate potential Vrm and the unselected bit line is set at the ground potential Vss. If the memory cell (T22) is in the "0" state, no current flows through the memory cell (T22),
No current flows through the bit line B2. Memory cell (T22)
Is "1", the memory cell (T2
A current flows to the source line S2 through 2). Bit line B
The data is read by detecting the presence or absence of the second current by the sense amplifier.

In a semiconductor device having such a structure,
Since the potential of the source line S1 is intermediate Vrm and the same potential as the bit line B2, current hardly flows from the bit line B2 to the source line S1, and there is little possibility of erroneous reading of the unselected memory cell (T12). And the read margin is wide.

[0006]

However, in a semiconductor memory device equipped with a nonvolatile memory cell, the characteristics of the memory cell vary greatly even when the writing and erasing operations are controlled, and the memory cell is excessively depleted (threshold). Value voltage is negative). That is, in the manufacturing process of the semiconductor memory device, the threshold value is caused to some extent due to the variation in the impurity concentration and the variation in the size of each part. However, with the high integration of the semiconductor storage device, the error in the size and the like causes the variation in the threshold value. Tends to be larger. Moreover,
When the degree of integration is increased, the operating voltage of a semiconductor memory device tends to be reduced in order to reduce power consumption for the purpose of suppressing heat generation and the like. It is shifting to the voltage side. Such causes are superimposed, and with the miniaturization and high integration of the semiconductor memory device, the probability of occurrence of depletion in some memory cells is increasing.

For the reasons described above, for example, when the unselected memory cell (T12) connected to the selected bit line B2 shown in FIG. When reading out T22),
A current flows through the bit line B2, and the potential of the bit line B2 decreases. At that time, a current flows from the source line S1 at the read intermediate potential to the bit line B2 through the memory cell (T12), and the potential of the bit line B2 is returned to the read intermediate potential.
If the potential of the bit line B2 does not change, the sense amplifier SA2 connected to the bit line B2 determines that the memory cell (T22) in the "1" state is in the "0" state, which may cause erroneous reading. There is. In other words, in a conventional semiconductor memory device, if there is a memory cell that has been depleted, there is a possibility that erroneous reading may occur.

In view of the above, a first object of the present invention is to
An object of the present invention is to prevent such erroneous reading by preventing generation of current in a non-selected memory cell at the time of reading.

Further, in the conventional semiconductor memory device equipped with nonvolatile memory cells, in the read operation shown in FIG. 33, for example, even when the non-selected memory cell (T11) is weakly depleted, as shown in FIG. Source line S
A current flows from 1 to the bit line B1. Since this current flows through the non-selected bit line B1, no erroneous reading occurs, but the power consumption increases. In the conventional nonvolatile semiconductor memory device, a case where an unselected source line or an unselected bit line is set to a floating state is described. However, there is a problem that a transient current is generated every time reading is performed and power consumption cannot be reduced by reading at high speed. Was.

A second object of the present invention is to reduce power consumption by preventing a leak current in an unselected memory cell.

[0011]

Means for Solving the Problems The first object and the second object are described.
Means taken by the present invention in order to achieve the object of the present invention is to provide a semiconductor memory device having an array structure in which a nonvolatile memory cell having a transistor including a gate, a source, and a drain and a capacitor is arranged in a matrix. At least a part of each path from the bit line to the source line via each transistor shows different voltage-current characteristics depending on the level of the voltage applied to both ends, and shows a forward direction in which a current easily flows and a reverse direction in which a current hardly flows. And providing a different direction resistance portion having the following.

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: an array in which non-volatile memory cells having at least a transistor including a gate, a source, and a drain; and a capacitor are arranged in a matrix, and in a row direction of the array. A plurality of word lines connected to the gates of the arranged transistors; a plurality of bit lines connected to the drains of the transistors arranged in the column direction of the array; and a plurality of bit lines connected to the row direction of the array. A plurality of source lines connected to the source of the transistor; a decoder circuit for selecting the word line; a decoder circuit for selecting the bit line; a decoder circuit for selecting the source line; is provided between a bit line and each transistor, the voltage varies depending on the level of the voltage applied across - shows the current characteristics, Ya current flows There forward and have have a direction opposite the current does not easily flow, countercurrent to the transistor from the bit line
A different direction resistance portion having a forward direction as a contact direction is provided.

[0013] The above-mentioned different-direction resistance portion can be constituted by a diode which allows a current to flow in only one direction .

The diode is connected to each of the transistors .
It can be constituted by a Schottky diode formed by depositing a conductive film directly on the surface of the region of the semiconductor substrate constituting the drain .

The diode is connected to each of the transistors .
It can be constituted by a PN diode formed between a region in the semiconductor substrate constituting the drain and a contact region of the semiconductor substrate.

According to a second semiconductor memory device of the present invention, there is provided an array in which non-volatile memory cells having at least a transistor having a gate, a source, and a drain and a capacitor are arranged in a matrix, and in a row direction of the array. A plurality of word lines connected to the gates of the arranged transistors; a plurality of bit lines connected to the drains of the transistors arranged in the column direction of the array; and a plurality of bit lines connected to the row direction of the array. A plurality of source lines connected to the source of the transistor; a decoder circuit for selecting the word line; a decoder circuit for selecting the bit line; a decoder circuit for selecting the source line; It is provided at least at a part of each path from the bit line to the source line through each transistor, and depends on the level of the voltage applied to both ends. Te different voltage - shows the current characteristics,
A different direction resistance portion having a forward direction in which a current easily flows and a reverse direction portion having a reverse direction in which the current hardly flows, wherein the different direction resistance portion is formed between one of a source and a drain of each transistor and a channel region below a gate. The offset region is formed by introducing impurities of the same conductivity type as the channel region.

In the first semiconductor memory device, the drains of each pair of memory cells of the memory cells are connected to a common bit line, and the pair of memory cells are arranged alternately in the column direction. To form an array structure arranged in a checker pattern matrix, wherein one source line is arranged at a ratio of two word lines to two word lines adjacent to each one source line. May be connected in common to the respective source lines .

According to a third aspect of the present invention, there is provided a semiconductor memory device comprising: an array in which non-volatile memory cells having at least a transistor including a gate, a source, and a drain; and a capacitor are arranged in a matrix, and in a row direction of the array. A plurality of word lines connected to the gates of the arranged transistors; a plurality of bit lines connected to the drains of the transistors arranged in the column direction of the array; and a plurality of bit lines connected to the row direction of the array. A plurality of source lines connected to the source of the transistor; a decoder circuit for selecting the word line; a decoder circuit for selecting the bit line; a decoder circuit for selecting the source line; It is provided at least at a part of each path from the bit line to the source line through each transistor, and depends on the level of the voltage applied to both ends. Te different voltage - shows the current characteristics,
A different direction resistance portion having a forward direction in which a current easily flows and a reverse direction in which a current hardly flows, a sense amplifier requiring a reference potential, and a dummy cell for reference on the bit line, and one of bit lines adjacent to each other It is configured to generate the reference potential.

Further, a method of driving a semiconductor memory device according to the present invention.
Means that the potential of the selected bit line and the potential of the selected source line are set so that the potential relationship between them coincides with the forward direction of the different-direction resistance portion of the memory cell, and the high potential side is set to the read potential. The potential of the non-selected source line is set to be equal to or higher than the lower potential of the selected bit line and the selected source line and equal to or lower than the read potential.

A first method of driving a semiconductor memory device according to the present invention.
Plurality, which are connected at least a gate, a source, and an array formed by arranging a non-volatile memory cells in a matrix having a transistor and a capacitor portion made of a drain, the gates of the transistors arranged in the row direction of the array A plurality of bit lines connected to the drains of the transistors arranged in the column direction of the array, and a plurality of source lines connected to the sources of the transistors arranged in the row direction of the array. A decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and interposed between the bit line and each transistor. , The voltage that varies depending on the level of the voltage applied to both ends
Shows the current characteristics, have to have a reverse direction of current flow easily forward and current hardly flows, Trang from the bit line
As a method of driving a semiconductor memory device having a different direction resistance part whose forward direction is toward the transistor, a bit line connected to a memory cell from which data is desired to be read is selected by the column decoder circuit. The source line connected to the memory cell is selected by the source decoder circuit,
The potentials of the selected bit line and the selected source line are set so that the potential relationship between them coincides with the forward direction of the different direction resistance portion of the memory cell, and the high potential side is set to the read potential, In this method, the potential is set to be equal to or higher than the potential on the lower potential side of the selected bit line and the selected source line and equal to or lower than the read potential.

A second method for driving a semiconductor memory device according to the present invention.
Plurality, which are connected at least a gate, a source, and an array formed by arranging a non-volatile memory cells in a matrix having a transistor and a capacitor portion made of a drain, the gates of the transistors arranged in the row direction of the array A plurality of bit lines connected to the drains of the transistors arranged in the column direction of the array, and a plurality of source lines connected to the sources of the transistors arranged in the row direction of the array. A decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and a circuit extending from the bit line to the source line via each transistor. It is interposed at least at a part of each path and shows different voltage-current characteristics depending on the level of the voltage applied to both ends, and the current flows A sense amplifier that requires a reference potential; a dummy cell for reference on the bit line; and a reference potential on one of bit lines adjacent to each other. As a method of driving a semiconductor memory device configured to generate a dummy memory cell connected to a bit line adjacent to the selected bit line, a selected bit line is selected from among unselected bit lines. The potential of the adjacent bit line is set to the same potential as the potential of the selected bit line, and the potential of the bit line and the source line connected to the selected dummy cell is set to the selected dummy cell so that the potential relationship is in the forward direction of the different direction resistance portion of the dummy cell. This is a method of setting a potential of a connected source line and generating a reference potential on the adjacent bit line.

In the first method for driving a semiconductor memory device,
Therefore , at the time of reading, all word line potentials can be set to the ground potential .

A third method for driving a semiconductor memory device according to the present invention.
Plurality, which are connected at least a gate, a source, and an array formed by arranging a non-volatile memory cells in a matrix having a transistor and a capacitor portion made of a drain, the gates of the transistors arranged in the row direction of the array A plurality of bit lines connected to the drains of the transistors arranged in the column direction of the array, and a plurality of source lines connected to the sources of the transistors arranged in the row direction of the array. A decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and interposed between the bit line and each transistor. , The voltage that varies depending on the level of the voltage applied to both ends
Shows the current characteristics, have to have a reverse direction of current flow easily forward and current hardly flows, Trang from the bit line
A different direction resistance portion having a direction toward the transistor as a forward direction, and a method of driving a semiconductor memory device in which the forward direction of the different direction resistance portion is formed such that the bit line side has a higher potential.
The threshold voltage of the memory cell in the erased state is set to a negative value, the bit line connected to the memory cell for which data writing is desired is selected by the column decoder circuit, and the source line connected to the memory cell is selected. Selected by the source decoder circuit, all word line potentials are set to the ground potential, the selected bit line is set to the high potential, the potential of the selected source line is set to the ground potential, the unselected bit lines are set to the ground potential, -A method in which hot electrons are generated by flowing a current between the selected source lines to change the threshold voltage of the desired memory cell to a high value.

[0024]

In the first or second semiconductor memory device , in the array in which the memory cells are arranged in a matrix, the voltage-current characteristics differ depending on the direction of the current and the transistor of the memory cell in each path between the bit line and the source line. It has a structure in which a different direction resistance part is connected in series. Therefore, the magnitude of the current flowing in the direction opposite to the read operation can be reduced or cut off, and even if any of the memory cells is depleted, the unselected source line is switched to the unselected bit line or the unselected source line. Unnecessary current flowing from the line to the selected bit line in the opposite direction to the read operation is reduced or prevented. Thereby, erroneous reading is prevented, and power consumption is reduced.

In the first semiconductor memory device, the memo
The drain of each pair of memory cells of the
The memory cells of each pair in the column direction.
Arranged in a checkered pattern
Of the array structure, and one word line for the two word lines.
The source lines are arranged at a ratio of one source line and
Of a memory cell connected to two adjacent word lines
Connected to the one source line in common.
In addition, since each pair of memory cells is connected to a common bit line, the area occupied by the memory cells is reduced.
Since only one source line is required for one word line, the area occupied by the memory cells is further reduced.

In the third semiconductor memory device, the sensitivity of the sense amplifier can be set high. Therefore,
The effect of preventing erroneous reading becomes significant.

Driving method of first or second semiconductor memory device
In the above, the driving of the semiconductor storage device utilizing the structure of each of the above semiconductor storage devices is performed. At this time, even if some of the non-selected memory cells are depleted, a different-direction resistance portion is provided in the path between the bit line and the source line passing through the memory cells, and when reading, the non-selected memory is used. Since the potential relationship between the bit line and the source line of the cell is set so as to be in the opposite direction of the different direction resistance portion, the leak current in the non-selected memory cell is reduced or prevented. Therefore, erroneous reading due to the leak current of the unselected memory cell is prevented, and the power consumption is reduced.

According to the third method of driving a semiconductor memory device , recovery of a written or depleted memory cell using the structure of the first aspect of the present invention is performed smoothly.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a semiconductor memory device and a reading method thereof according to a first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the block circuit diagram of the semiconductor memory device according to the present embodiment is the same as the block circuit diagram of the conventional semiconductor memory device equipped with the nonvolatile memory cells shown in FIG. FIG. 1 is a circuit diagram showing a part of a memory cell array of a flash EEPROM according to a first embodiment of the present invention, in which a plurality of non-volatile memory cells (T11) to T9 to Tmn and a capacitor section are incorporated. (Tmn)
Have the structure of a memory cell array arranged in a matrix of m rows and n columns. In FIG. 1, each bit line B1-B
n, word lines W1 to Wm, source lines S1 to Sm, each memory cell (T11) to (Tmn), each column selecting transistor S
T1 to STn, each sense amplifier SA1 to SAn, each row decoder RD1 to RDm, and each source decoder SD1 to
The structure and arrangement of the SDm are shown in FIG.
This is the same as the structure shown in FIG.

Here, a feature of this embodiment is that diodes D11 to D11 that allow only current flow from the bit line side to the transistor side are provided between the drains of the transistors T11 to Tmn and the bit lines B1 to Bn. Dmn are arranged respectively. The diodes T11 to Dmn cause the transistors T11 to Tmn to pass through the paths P11 to Pmn.
The current characteristic that the current flowing from the drain of Tmn in the source direction (forward direction) is almost equal to the operating current of the transistor, and the current flowing from the source in the drain direction (reverse direction) is almost cut off or reduced. That is, this diode is the different-direction resistance section referred to in the present invention. However, the different-direction resistance section does not necessarily have to have a function as a diode in which the current value in the reverse direction is almost completely cut off, as long as the current value in the reverse direction is smaller than that in the forward direction. However, in the following embodiments, all are expressed as diodes for convenience.

Next, the steps of manufacturing the semiconductor memory device having such a structure will be described with reference to FIGS.
This will be described with reference to (a) to (c). In each figure, 1 is a P-type semiconductor substrate, 2 is a tunnel SiO2 film, 3
Is a floating gate, 4 is a capacitor insulating film, 5 is a control gate (polycide) made of a conductive material such as a polycide film, 6 is a SiO2 film, 7 is a resist, and 9 is n-
Layer 10, 10 resist, 21 n + layer, 22 SiO2
Film, 23 is resist, 24 is sidewall, 25 is W
Six film.

First, as shown in FIG. 2A, a tunnel SiO 2 film 2 is formed on the surface of a P-type semiconductor substrate 1 by thermal oxidation, and the floating gate 3 is patterned. Insulating film 4
Is formed using a CVD method, a thermal oxidation method, or the like, and a conductive material film such as polycide forming the control gate 5 so as to cover the floating gate 3 and S as a protective film.
An iO2 film 6 is formed. After that, the control gate 5 and the SiO
2 The film 6 is patterned, and using the patterned control gate 5 and the SiO2 film 6 as a mask, the capacitor insulating film 4, the floating gate, and the tunnel SiO2 film 2 are etched in a self-aligned manner by an anisotropic etching method. The structure shown in FIG. 2A is the same as the gate structure conventionally called a stack type floating gate EEPROM.

Next, a resist 7 is applied to the diode D
An opening is formed in a region for forming an n-layer 9 and P @ + ions are implanted to form an n @-layer 9 adjusted to a desired concentration (FIG. 2B).
reference). A resist 10 is applied, an opening is left except for a region where a diode is to be formed, and As + ions are implanted to form a high concentration n + layer 21 (see FIG. 2C).

Next, the SiO 2 film 22 is formed as a protective film by CV.
After the deposition by the method D (see FIG. 3A), the resist 2
3 is applied to open a region where a diode is to be formed, and the SiO2 film 22 is etched back by anisotropic etching to leave a sidewall 28 on the gate side wall in the region where a diode is to be formed (see FIG. 3B). And FIG.
As shown in FIG. 1C, a WSix film 25 is deposited on a semiconductor substrate and then patterned to form a Schottky diode. The WSix film 25 may be patterned as a wiring layer or may be patterned as a contact burying layer. In the memory cell shown in FIG. 3C, a Schottky diode is formed in a region corresponding to the source or drain region of a conventional memory cell transistor having a stacked floating gate structure. However, it is not possible to increase the area of the entire memory cell. Absent.

Next, a reading method of the semiconductor memory device in the first embodiment will be described with reference to FIG. In that case, the region where the Schottky diode is formed may be a source or a drain. Here, a reading method in the case where the Schottky diode is formed in the drain will be described. A reading method when a Schottky diode is formed on the source will be described in a second embodiment.

Here, the case where the memory cell (T22) is read will be described. The memory cells (T11) and (T12) are excessively depleted (threshold value is negative).
The case where the memory cell (T22) is read will be described assuming that the reading is performed. The selected word line W2 is set to the read power supply voltage Vcc (for example, 5 V), and the unselected word lines W1, Wm
To the ground potential Vss (for example, 0 V). At the same time, the selected source line S2 is grounded to Vss, and the unselected source lines S1 and Sm are read and set to the intermediate potential Vrm (for example, 1 V). Also, the selected bit line B2 is set to the read intermediate potential Vrm via the sense amplifier, and the unselected bit lines B1, Bn are set to the ground potential Vss.
To Actually, since the sense amplifier is connected to the bit line, the potential of the bit line slightly fluctuates from the intermediate potential Vrm. However, in order to simplify the description, the potential of the bit line is set to a constant voltage Vrm. And

If the memory cell (T22) is in the "0" state, the memory cell (T22) does not operate and no current flows. Although the memory cell (T12) is excessively depleted, no current flows through the memory cell (T12) because the potentials of the bit line B2 and the unselected source line S1 are the same. Therefore, no current flows through the selected bit line B2, and it can be detected without error that the memory cell (T22) is in the "0" state.

On the other hand, if the memory cell (T22) is in the "1" state, the memory cell (T22) operates and a current flows, and the potential of the selected bit line B2 slightly decreases. At this time, a potential difference occurs between the non-selected source line S1 and the selected bit line B2, but even if the non-selected memory cell (T12) is excessively depleted, the potential is opposite to that of the diode D connected to the drain of the memory cell (T12). Memory cell (T1
No current flows in 2), and the potential of the selected bit line B2 does not return to the read intermediate potential of 1V. Therefore, it can be detected that the memory cell (T22) is in the "1" state by the current flowing through the selected bit line B2. Also,
The memory cell (T11) is also excessively depleted, and the potential difference between the unselected source line S1 and the unselected bit line B1 is 1V.
However, since the bias is reverse biased to the diode D11 connected to the drain of the memory cell (T11), no current flows to the memory cell (T11), no current flows to the unselected bit line B1, and extra Power consumption does not occur.

As described above, even if a memory cell array excessively depleted occurs in the memory cell array, it is read out without error whether the selected memory cell is in the "0" state or the "1" state by the current of the selected bit line. Since no current flows through the unselected bit lines, no extra power is consumed.

In the reading method of the first embodiment, the potential of the selected bit line and the potential of the unselected source line are set to the read intermediate potential Vrm, but may be set to the read power supply voltage Vcc.

Next, with reference to FIG. 5, a description will be given of a method of collectively reading out all the memory cells connected to the word line in this embodiment. Here, it is assumed that the memory cells (T11) and (T12) are excessively depleted (threshold value is negative), and a case where all the memory cells connected to the word line W2 are read collectively will be described. I do. Reads the selected word line W2 and reads the power supply voltage Vcc
(For example, 5 V) and the unselected word lines W1 and Wm are set to the ground potential Vss (for example, 0 V). At the same time, select source line S
2 is set to the ground potential Vss, and the unselected source lines S1 and Sm are read and set to the intermediate potential Vrm (for example, 1 V). All the bit lines B1, B2, Bn are set to the intermediate potential Vrm via the sense amplifier. Actually, since the sense amplifier is connected to the bit line, the potential of the bit line slightly fluctuates from the intermediate potential Vrm. However, in order to simplify the description, the potential of the bit line is set to a constant voltage Vrm. And If the memory cell is in the "0" state, no current flows through the bit line, and the potential of the bit line does not change. If the memory cell is in the "1" state, a current flows through the memory cell and the potential of the bit line slightly decreases. The difference between the potentials of the bit lines is detected using a sense amplifier connected to each bit line. If the unselected memory cells (T11) and (T12) are excessively depleted, a potential difference occurs between the unselected source line S1 and the selected bit line B2, but the unselected memory cell (T12) is excessively depleted. However, since a reverse bias is applied to the diode D12 connected to the drain of the memory cell (T12), no current flows to the memory cell (T12), and the potential of the selected bit line B2 is read out and returned to the intermediate potential of 1 V. Never. Therefore, it can be detected without error that the memory cell (T22) is in the "1" state by the current flowing through the selected bit line B2.

Although a slight leakage current flows through the diode D11 even with a reverse bias, such a method of reading out all the memory cells connected to the word line all at once is as follows.
Since the potentials of the unselected source line S1 and all the bit lines are equal, leakage current can be suppressed and power consumption can be reduced. In the above-mentioned reading method, the potential of the bit line and the potential of the unselected source line are set to the read intermediate potential Vrm, but both may be set to the read power supply voltage Vcc. In each claim, these are collectively referred to as a read potential.

Next, a description will be given of a method of reading data with the word line potential kept at the ground potential in this embodiment. The read method is a method in which all the word lines W1 to Wm are set to the ground potential Vss (for example, 0 V) in the read method shown in FIG. 4 or FIG. 5, and the drawings for the explanation only are omitted. If the threshold voltage of the memory cell in the “1” state of the present embodiment is set to be negative, the memory cell can be set to have the word line potential set to the ground potential Vss (for example, 0 V).
Since current flows in the "1" state and no current flows in the "0" state, all word lines W1 to Wm are set to the ground potential Vss (for example, 0 V) in the read method shown in FIG. 4 or FIG. Also, data can be read by detecting the state of the memory cell and the bit line current. That is, the selected source line S2 is set to the ground potential Vss, and the non-selected source lines S1,
The memory selected by the source line and the bit line by setting Sm to the read intermediate potential Vrm (for example, 1 V), setting the potential of the selected bit line B2 to the read intermediate potential Vrm via the sense amplifier, and setting the non-selected bit line to Vss. The cell can be read. Therefore, there is no change in the word line potential at the time of reading, so that lower power consumption and lower power supply voltage can be achieved.

Although the potential of the bit line and the potential of the non-selected source line are set to the read intermediate potential Vrm in the reading method of the first embodiment, both may be set to the read power supply voltage Vcc.

Next, a description will be given of a method of writing with the word line potential kept at the ground potential. If the threshold voltage of the memory cell in the “1” state of this embodiment is set to a negative value, a current flows through the memory cell even when the potential of the word line is set to the ground potential Vss (for example, 0 V). The selected memory cell is set by setting the selected bit line to the high potential, setting the unselected bit line to the ground potential Vss, setting the selected source line to the ground potential, and setting the unselected source line to the high potential or floating while the word line is grounded. To generate hot electrons,
The memory cell in the “1” state can be changed to the “0” state.

Note that the above-mentioned method of writing with the potential of the word line kept at the ground potential may be used to return the threshold voltage of the excessively depleted memory cell to a high level.

In the above description, the writing to the memory cell was performed by injection of hot electrons.
Writing may be performed using a −N current. However, in this embodiment, since the diode D is provided on the drain side, the writing method using the FN current performed by generating a high electric field between the drain and the floating gate is more difficult than the writing method using the hot electrons in the conventional flash EEPROM. The writing method is more suitable.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. 6 (a) to 6 (d), FIGS. 7, 8, 9 and 10. FIG.

FIGS. 6A to 6D show a manufacturing process of the semiconductor memory device according to the second embodiment. In FIGS. 6A to 6D, reference numeral 25 denotes a resist, 27 denotes an n + layer, 28 denotes a sidewall, 29 denotes an offset region, and 30 denotes an n + layer. FIG. 6A shows a state where a stacked floating gate structure is formed in the same manner as the state shown in FIG. 2A.
A resist 25 is applied on the substrate in this state, an opening is left except for a region for forming a diode, and As @ + ions are implanted to form a high concentration n @ + layer 27 (see FIG. 6B).
Next, a sidewall 28 is formed by depositing a SiO2 film and etching back (see FIG. 6C).
S + ion implantation is performed to form a high concentration n + layer 30 (see FIG. 6D). In the state shown in FIG.
0 is offset from the floating gate 3 in the horizontal direction, and the distance of the offset region 29 is controlled by the film thickness of the sidewall 28.

Next, the n + layer 30 shown in FIG.
It will be explained that the portion of the offset region 29-channel region has a function almost similar to that of the diode. FIG.
This is a simulation of the voltage-current characteristics of a memory cell incorporating such an offset region. The vertical axis represents the operating current of the memory cell, and the horizontal axis represents the gate (floating gate) voltage. The gate length is 0.5 microns, the offset amount is 0.2 microns, and the drain-source voltage is 1V. In the figure, the solid line shows the voltage-current characteristic when the potential of the n + layer 30 adjacent to the offset region 29 is set to a high potential, and the dotted line shows the potential of the n + layer 30 adjacent to the offset region 29 is set to a low potential. The voltage-current characteristics in the case are shown. As shown in the figure, it can be seen that the current value differs by two or more digits in the forward direction and the reverse direction. That is, different current characteristics are obtained depending on the relationship between the voltage levels of the source and the drain. The structure of the memory cell in this embodiment is, as shown on the right side of FIG.
It can be represented by a structure in which a diode is attached to the 0 side. However, actually, the structure has a portion corresponding to a diode between the source and the drain.

Therefore, in the structure of the memory cell including the offset region according to the second embodiment, the function of cutting off one current is inferior to that of the memory cell having the Schottky diode according to the first embodiment. Since the resistance value is extremely different depending on the direction in which the current flows, it can be seen that almost the same function as the memory cell structure of the first embodiment can be obtained. In particular, the structure of the memory cell of the second embodiment is different from the example of the memory cell of the first embodiment.
There is an advantage that the number of steps for exposing the resist is small.

Next, a reading method of the semiconductor memory device of the second embodiment will be described with reference to FIGS. Also in the case of this embodiment, similarly to the first embodiment, the n + layer 30 adjacent to the offset region 29 may be either a source or a drain. In the second embodiment, a case will be described in which the n + region 30 adjacent to the offset region 29 is the source. When the n + region adjacent to the offset region 29 is a drain, the same reading method as in the first embodiment can be applied.

FIG. 8 shows the structure of the memory cell array in this embodiment. Each memory cell allows only a current from the source to the drain (that is, from the source line to the bit line) on the source side of the memory cell. In this configuration, a diode D is connected. The current flowing from the source to the drain is substantially equal to the operating current of the memory cell, and the current flowing from the drain to the source is almost cut off by the diode D.

Next, a reading method in this embodiment will be described with reference to FIG. Here, it is assumed that the memory cells (T11) and (T12) are excessively depressed (the threshold value is negative), and the case where the memory cell (T22) is read will be described. The selected word line W2 is set to the read power supply voltage Vcc (for example, 5 V), and the unselected word lines W1 and Wm are set to the ground potential Vss (for example, 0 V). At the same time, the selected source line S2 is read and set to the intermediate potential Vrm (for example, 1 V), and the unselected source lines S1 and Sm are set to the ground potential Vss.
To Further, the selected bit line B2 is set to the ground potential Vss via the sense amplifier, and the non-selected bit lines B1 and Bn are read to the intermediate potential Vrm. Actually, since the sense amplifier is connected to the bit line, the potential of the bit line slightly fluctuates from the ground potential Vss. However, in order to simplify the description, the potential of the bit line is set to a constant voltage Vss. And If the memory cell (T22) is in the "0" state, no current flows through the memory cell (T22). In addition, the memory cell (T12)
Is excessively depleted, but no current flows through the memory cell (T12) because the potentials of the bit line B2 and the unselected source line S1 are the same and Vss. Therefore, no current flows through the selected bit line B2, and it can be detected without error that the memory cell (T22) is in the "0" state.

On the other hand, when the memory cell (T22) is in the "1" state, the memory cell (T22) operates and a current flows, and the potential of the selected bit line B2 slightly rises. At this time, a potential difference occurs between the selected bit line B2 and the non-selected source line S1,
Even if the unselected memory cell (T12) is excessively depleted, the memory cell (T1) is reverse-biased to the diode D connected to the source of the memory cell (T12).
2), no current flows, and the potential of the selected bit line B2 is set to Vss
Will not return to. Therefore, when a current flows through the selected bit line B2, it is possible to detect that the memory cell (T22) is in the "1" state without causing an erroneous read. The memory cell (T11) is also excessively depleted, causing a potential difference of 1 V between the unselected bit line B1 and the unselected source line S1, but opposite to the diode D11 connected to the drain of the memory cell (T11). No current flows through the memory cell (T11) because of the bias, and the unselected bit line B
No current flows through 1 and no extra power consumption occurs. In the reading method, the potential of the selected source line and the potential of the non-selected bit line are set to the read intermediate potential Vrm, but both may be set to the read power supply voltage Vcc.

In the above reading method, the potential of the selected bit line is set to the ground potential Vss via the sense amplifier. However, when the sense amplifier requires the reference potential, the potential of the selected bit line is set to the ground potential Vss. It may be set to be larger than the read intermediate potential.

Next, a method of reading all memory cells connected to a word line in this embodiment at once will be described with reference to FIG. Here, it is assumed that the memory cells (T11) and (T12) are excessively depressed (the threshold value is negative), and a case where all the memory cells on the word line W2 are read at once will be described.
The selected word line W2 is read and the power supply voltage Vcc (for example, 5
V) and the unselected word lines W1 and Wm are connected to the ground potential Vss.
(For example, 0 V). At the same time, the selected source line S2 is read and set to the intermediate potential Vrm (for example, 1 V), and the unselected source lines S1 and Sm are set to the ground potential Vss. All bit lines B
1, B2 and Bn are set to the ground potential Vss via the sense amplifier. Actually, since the sense amplifiers SA1 to SAn are connected to the bit lines B1 to Bn, the bit lines B1 to
Although the potential of Bn slightly fluctuates from the ground potential Vss, here, it is assumed that the potential of the bit line is a constant potential Vss for the sake of simplicity.

For example, when the memory cell (T2n) is in the "0" state, the memory cell (T2n) does not operate, so that no current flows through each bit line and the potential of the bit line does not change. On the other hand, when each of the memory cells (T21) and (T22) is "1",
Each of the memory cells (T21) and (T22) operates and a current flows, and the potential of the bit line B2 slightly increases. This difference in potential of the bit line is detected by a sense amplifier connected to the bit line. Although the unselected memory cells (T11) and (T12) are excessively depleted, the non-selected source lines S1
And all bit lines have the same potential and the ground potential Vss, so that no current flows. Although a slight leak current flows through the diode D even with a reverse bias, the above-described batch reading method for all memory cells on one word line can also suppress the leak current and reduce power consumption. In addition, unlike the conventional method of collectively reading all memory cells on one word line, voltage is applied only to the selected word line and the selected source line, so that low power consumption can be achieved at the time of starting reading. .

In the reading method of the second embodiment, the potential of the selected source line is read and the intermediate potential Vrm (for example, 1
V), but may be the read power supply voltage Vcc.

In the above reading method, the potential of the selected bit line is set to the ground potential Vss via the sense amplifier. However, when the sense amplifier requires the reference potential, the potential of the selected bit line is set to the ground potential Vss. It may be larger than the read intermediate potential and may be smaller than the read intermediate potential.

Next, a description will be given of a method of reading data with the word line potential kept at the ground potential in this embodiment. The read method is the same as the read method shown in FIG. 9 or 10 except that all the word lines are connected to the ground potential Vss (for example, 0 V).
The drawings are omitted. "1" in this embodiment
If the threshold voltage of the memory cell in the state is set to a negative value, a current flows in the memory cell even if the potential of the word line is set to the ground potential Vss (for example, 0 V) in the "1" state.
Since no current flows in the “0” state, even if all the word lines are grounded to Vss (eg, 0 V) in the read method shown in FIG. 9 or FIG. To read the data. That is, the selected source line S2 is read out to have the intermediate potential Vrm (for example, 1 V), and the unselected source lines S1 and Sm are set to the ground potential Vss.
And the selected bit line is connected to the ground potential Vss via the sense amplifier.
By setting the non-selected bit line to the read intermediate potential Vrm, the memory cell selected by the source line and the bit line can be read. According to this method, the power consumption and the power supply voltage can be further reduced without fluctuation of the word line potential at the time of reading. In the above reading method, the potential of the selected source line is read and the intermediate potential Vrm (for example, 1 V) is read.
However, the read power supply voltage Vcc may be used.

In the above reading method, the potential of the selected bit line is set to the ground potential Vss via the sense amplifier. However, when the sense amplifier requires the reference potential, the potential of the selected bit line is set to the ground potential Vss. It may be set to be larger than the read intermediate potential.

Next, a writing method using hot electrons in this embodiment will be described. In this embodiment, the channel current is not allowed to flow to the memory cell except from the source line. Therefore, the selected word line is set to the high potential, the unselected word line is set to the ground potential, the selected source line is set to the high potential, the unselected source line is set to the ground potential or floating, the selected bit line is set to the ground potential, Is set to a high potential, hot electrons are generated and current can be written by passing a current from the source side to the drain side of the selected memory cell.

Next, a description will be given of a method of writing data while keeping the word line potential at the ground potential. If the threshold voltage of the memory cell in the “1” state of this embodiment is set to a negative value, a current flows through the memory cell even when the potential of the word line is set to the ground potential Vss (for example, 0 V). A memory cell selected by setting the selected source line to the high potential, the unselected source line to the ground potential, the selected bit line to the ground potential, and the unselected bit line to the high potential or floating while the word line is kept at the ground potential. Hot electrons are generated at the same time, and the memory cell in the "1" state can be changed to the "0" state.

The above-mentioned method of writing with the potential of the word line kept at the ground potential may be used to return the threshold voltage of the memory cell excessively depleted to a high level.

In this embodiment, since the diode D is provided on the source side, a high electric field is easily generated between the drain and the floating gate, and the conventional flash type EEPROM is more effective than the above-mentioned hot electron method.
A writing method using an FN current at M is preferable.

(Third Embodiment) Next, a third embodiment will be described with reference to FIGS. 11 (a) to 11 (c) and FIG. FIGS. 11 (a) to 11 (c)
Shows a manufacturing process of the memory cell of the semiconductor memory device in the third embodiment. 11A to 11C, reference numeral 30 denotes an n + layer, reference numeral 31 denotes a resist, and reference numeral 33 denotes a p-layer. In the state shown in FIG. 11A, a stacked floating gate structure is formed similarly to the state shown in FIG. 2A. Then, a resist 3 is formed on the substrate in this state.
1 is applied, an opening is left to leave a region for forming a diode, and BF2 + ion implantation 32 is performed to form a p layer 33 (see FIG. 11B). BF2 + ion implantation is desirably performed at a large inclination angle, for example, 45 degrees, 60 KeV, 6E12at.
Perform under the condition of oms / cm2. However, it is not limited to this condition. Next, in the step shown in FIG.
A high concentration n + layer 30 is formed by performing s + ion implantation.
Two n + layers 3 serving as a source and a drain of a memory cell
By forming the p-layer 33 doped with a low concentration of impurity inside one of the n + layers 30 out of 0 and 30, the expansion of the depletion layer in this portion is suppressed, and a diode is formed between the source and the drain. The same effect as described above occurs. FIG.
This is a simulation of a voltage-current characteristic of a memory cell in which a low-concentration p-layer 33 is formed only on one of the above-mentioned ones.
The vertical axis represents the operating current of the memory cell, and the horizontal axis represents the gate (floating gate) voltage. The gate length is 0.5 micron, the concentration of the p-layer is 1E18 atoms / cm3, it is not in an offset state, and the drain-source voltage is 1V. In the figure, the solid line indicates the n + layer 3 adjacent to the p layer 33.
The voltage-current characteristics when the 0 side is set to a high potential are shown, and the dotted lines show the voltage-current characteristics when the n + layer 30 side adjacent to the p layer 33 is set to a low potential. As shown in the figure, it can be seen that the current value differs by one or more digits in the forward direction and the reverse direction. Therefore, the structure of the memory cell in this embodiment can also be represented by a structure in which a diode is attached to the n + layer 30 for convenience. However, in practice, the source
The structure has a portion corresponding to a diode between the drains.

It is to be noted that the concentration of p layer 33 is increased and n + layer 3
0 may be an offset. The example of the memory cell of FIG. 11 is characterized in that a sidewall process is not required as compared with the example of the memory cell of FIG.

Fourth Embodiment Next, a fourth embodiment will be described with reference to FIGS. 13 (a) to 13 (c) and FIGS. 14 (a) and 14 (b). FIG.
FIGS. 14A to 14C and FIGS. 14A and 14B show a process of manufacturing a memory cell of a semiconductor memory device according to the fourth embodiment. In the state shown in FIG.
As in the state shown in FIG. In this state, a resist is formed, and P @ + ions are implanted into a region where a diode D is to be formed, and an n @-layer 9 adjusted to a desired concentration is formed (see FIG. 13B). As + ions are implanted into the region to form a high concentration n + layer 21 (FIG. 13).
(C)). Next, a SiO2 film 22 is
Deposited by the VD method (see FIG. 14A), the SiO2 film 22 is etched back in the region where the diode D is to be formed, and the sidewall 28 is left on the gate side wall in the region where the diode D is to be formed (see FIG. 14E). ). In this state, a resist 31 is applied, a region for forming a diode is opened, and BF2 + ions are implanted to form a p-layer 61. FIG.
In the memory cell shown in FIG. 4B, a PN diode is formed in a region corresponding to the source or drain region of the conventional memory cell having a stacked floating gate structure, but the area of the memory cell is not increased.

In this case, diode characteristics are obtained,
A memory cell having this structure can be expressed as a memory cell provided with a diode adjacent to a source or a drain as shown on the right side of FIG.

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIGS.
(B), FIG. 17 (a), (b), FIG. 18 and FIG.

The block circuit diagram of the semiconductor memory device according to the present embodiment is the same as the block circuit diagram of the semiconductor memory device equipped with the conventional nonvolatile memory cell shown in FIG. 31, and a description thereof will be omitted. FIG. 15 is a circuit diagram showing a part of a memory cell array of a flash EEPROM according to the fourth embodiment. This embodiment is an improvement of the structure of the first embodiment for realizing high integration. In this embodiment, FIG.
As shown in FIG. 2, for example, two memory cells (T21a),
Diodes D21a and D21a are connected to the drains of (T21b).
One end of each of the diodes 21b is connected one by one, and the other ends of the diodes D21a and D21b are connected to a common bit line B1 via a common wiring. The source of the memory cell (T21a) is connected to the source line S2, and the source of the memory cell (T21b) is connected to the source line S3. That is, a pair of memory cells (T21a), (T21
The source b) is connected to individual source lines S2 and S3, while the drain is connected to a common bit line. The memory cells (T21a) and (T21a) are connected on the bit line B1 to which the pair of memory cells (T21a) and (T21b) are connected.
No memory cell is arranged in the adjacent region of (T21b). A pair of memory cells (T12a) and (T12b) and (T32a) and (T32b) are arranged at an interval of 2 bits with respect to the bit line B2. The drains of the memory cells (T12a) and (T12b) are connected to a common bit line B2 via diodes D12a and D12b, respectively, and the source of the memory cell (T12b) is connected to the memory cell (T12).
21a) and a common source line S2. The same applies to the connection state of one pair of memory cells (T32a) and (T32b).

As a result, the distance between the source lines S1 and S3 is 2
Word lines W1a and W1b are arranged between source lines S2 and S3, and two word lines W2a and W2b are arranged between bit lines B1 to B2.
3 is arranged so as to vertically intersect the word line and the source line. A set of 2-bit memory cells (T) is arranged in a checker pattern in an area on a matrix formed by these wirings. The gate of each memory cell (T) is connected to the word line W, and the memory cells are arranged in a NOR type. Also, word lines W1a, W1b to W3a, W3b
Are the row decoders RD1a, RD1b to RD3a, RD, respectively.
3b, the source lines S1 to S3 are respectively connected to the source decoder S
D1 to SD3 and bit lines B1 to B3 are connected to sense amplifiers SA1 to SA3 via column selection transistors ST1 to ST316, respectively, and connected to a column decoder.

In this embodiment, the reading method is the same as that in the first embodiment. Either the memory cell (T21a) or the like is read out in 1-bit units as shown in FIG. 16A (see arrow), or all memories connected to one word line W2a as shown in FIG. Batch read cells (see arrow). In the batch reading method for all memory cells on one word line, data is output every other bit line. Further, in this embodiment, as shown in FIG. 16C, two word lines W1b and W2a arranged on both sides of a certain source line S2 are simultaneously selected, and a memory cell (T12b) and a memory cell (T12b) are selected. It can be read in 2-bit units such as T21a) (see arrow). FIG.
As shown in (d), all the memory cells connected to the two word lines W1b and W2a can be read at once (see arrows). In the batch reading method for all memory cells on two word lines, data is output from all bit lines. In that case, sense amplifiers need to be arranged on all bit lines.

In this embodiment, each memory cell pair is arranged in a checker pattern. However, when the drains of a pair of memory cells are connected to a common bit line, the configuration is not necessarily limited to such a configuration. Not something. For example, if source lines are provided adjacent to each other between word lines, a pair of memory transistors may be arranged in a matrix without any gap.

Next, the memory cell (T) in this embodiment is
Will be described. FIG. 17A is a longitudinal sectional view in a section parallel to the bit line, and FIG. 17B is a plan view. FIG. 18 is a plan view showing the patterning of the floating gate. FIG. 19 is a vertical cross-sectional view of a cross section parallel to the word line direction of a single memory cell. In each figure, 1 is a semiconductor substrate, 2 is a tunnel SiO2 film, 3 is a floating gate, 4 is a capacitance insulating film, 5 is a control gate, 6 is an SiO2 film,
22 is a SiO2 film, 27 is an offset drain, 28 is a side wall, 30 is a source, 51 is an element isolation, 52
Is a source wiring, 53 is a protective insulating film, 54 is an interlayer insulating film,
55 is a bit line, 56 is a source line contact, 57 is a bit line contact, 58 is an active region, and 59 is a floating gate after patterning. As shown in FIG. 18, the long side direction is formed to be five times the design rule L and the short side direction is formed so as to fold the rectangular active region 58 of the design rule L, and the floating gate 59 is formed on the long side of the active region 58. Pattern linearly in the direction (first
Second patterning). As shown in FIG. 17B, the control gate 5 which is a word line is patterned at equal intervals by lines and spaces of the design rule. At this time, the capacitance insulating film 4, floating gate 3 and tunnel SiO2 film 2 are formed by themselves. Etching is performed consistently (second patterning of floating gate). Source 3
0 is formed by ion implantation, then a SiO2 film is deposited,
After a sidewall is formed by etch back, an offset drain 27 is formed by ion implantation. A wiring material and a SiO2 film 53 are deposited thereon, and the source wiring 5 is formed.
2 is patterned. After depositing the interlayer insulating film 54, it is etched back to open a contact hole for the bit contact 57 with an oversize. A wiring material is deposited thereon, and the bit wiring 55 is patterned. As shown in the plan view of FIG. 17B, the channel width direction of the memory cell is limited by the design rule of the bit line and the alignment margin of the mask of the bit contact 57. As shown in FIG. 19, in the structure of a memory cell in a section parallel to a word line, the floating gate 3 is asymmetric with respect to the active region. This is due to the fact that the floating gate 3 is linearly patterned in the long side direction of the active region 58. As the design rule becomes smaller, the linear shape is more easily patterned and has the advantage of being able to be miniaturized.

The layouts shown in FIGS. 17A and 17B assume that the alignment margin of the mask is half of the design rule, and the cell area is 11 times the square of the design rule. The alignment margin of the mask depends on the exposure technique, and need not be limited to half the design rule.

The memory cells shown in FIGS. 17A and 17B use the floating gate memory cell (the second embodiment) having the structure incorporating the offset region shown in FIG. , But not limited to this
The memory cells having the structures shown in the first, third, and fourth embodiments may be used.

In the present embodiment, the active region 58 is rectangular, but may be partially deformed as required by an exposure technique or the like.

Further, in this embodiment, the floating gate 3, the control gate 5, and the source wiring 52 are linear, but they may be partially deformed as required by an exposure technique or the like.

Although the source wiring 52 is made of a wiring material in this embodiment, it may be formed of a diffusion layer.

Sixth Embodiment Next, a semiconductor memory device according to a sixth embodiment and a reading method thereof will be described with reference to FIGS. 20, 21A to 21D and 22.
This will be described with reference to FIG. The block circuit diagram of the semiconductor memory device of this embodiment is the same as the block diagram of the conventional semiconductor memory device equipped with the nonvolatile memory cells shown in FIG. FIG. 20 is a circuit diagram showing a part of the memory cell array of the flash EEPROM according to the present embodiment. As shown in FIG. 20, the wiring connection structure and the arrangement state of the memory cells are basically the same as those in the fifth embodiment (FIG. 15).
Reference). However, the present embodiment is different only in that a diode D is provided between the source of each memory cell (T) and the source lines S1 to S3.

In this embodiment, the reading method is the same as that in the second embodiment. Either the memory cell (T21a) or the like is read out in 1-bit units as shown in FIG. 21 (a) (see arrows), or all the memories connected to one word line W2a as shown in FIG. 21 (b). Batch read cells (see arrow). In the batch reading method for all memory cells on one word line, data is output every other bit line. In this embodiment, FIG.
As shown in (c), two word lines W1b and W2a are simultaneously selected, and a memory cell (T12b) and a memory cell (T21b) are selected.
a) and the like can be read in 2-bit units (see arrows). Also, as shown in FIG. 21D, two word lines W1b and W2a can be read at once (see arrows). In the two word line batch reading method, data is output from all bit lines. In the case of batch reading, sense amplifiers need to be arranged on all bit lines.

[0085] Figure 22 is Ru longitudinal sectional view showing a structure in a cross section parallel to the bit lines of the memory cell of this embodiment. FIG.
The structure shown in FIG. 2 differs from the structure shown in FIG. 17 only in that a diode structure is provided on the source side. Note that the plan view and the structure in a cross section parallel to the word line of the memory cell alone are the same as in the fifth embodiment, so that the illustration is omitted.

Although the present embodiment employs the floating gate memory cell having the structure incorporating the offset region shown in FIG. 6 (second embodiment), the present invention is not limited to this. The structure of the fourth embodiment can be applied.

(Seventh Embodiment) Next, a semiconductor memory device according to a seventh embodiment will be described with reference to FIGS.
This will be described with reference to FIG. The block circuit diagram of the semiconductor memory device according to the present embodiment is the same as the block circuit diagram of the semiconductor memory device equipped with the conventional nonvolatile memory cell shown in FIG. 31, and the description is omitted. FIG. 23 is a circuit diagram showing a part of a memory cell array of a flash EEPROM according to a seventh embodiment of the present invention. 24 and 25 are diagrams illustrating a method for driving the semiconductor memory device.
FIG. 26A is a longitudinal sectional view showing a structure of a memory cell in a section parallel to a bit line, and FIG. 26B is a plan view thereof. In the present embodiment, the first embodiment has a folded bit line structure. In the present embodiment, as shown in FIG. 23, the structure in which each pair of memory cells is arranged in a checker pattern and the point that the drain of one memory cell is connected to a common bit line via a diode are the same as those in the first embodiment. This is the same as the structure of FIG. 15 described in the fifth embodiment. However, in this embodiment, two source lines (for example, S2a and S2b) are used instead of one source line (for example, S2) in FIG.
And a source decoder (eg, SD2a, SD2
2b) is located. The sources of the memory cell (T12b) and the memory cell (T21a) are connected to different source lines S1b and S2a, respectively. Also, each bit line has
A set of 2-bit dummy cells is arranged. For example,
One dummy cell (Tr1, Tr2) is arranged on the bit line B2, and the drains of the dummy cells (Tr1, Tr2) are connected to a common bit line B2 via diodes Dr1, Dr2, respectively. . The sources of the dummy cells (Tr1) and (Tr2) are individual source lines Sr1 and Sr1.
The source decoders SDr1 and SDr2 are arranged at the ends of the source lines Sr1 and Sr2. Further, the gates of the dummy cells (Tr1) and (Tr2) are connected to word lines Wr1 and Wr2, respectively, and row decoders RDR1 and RDR2 are provided at the ends of the word lines Wr1 and Wr2, respectively.

In this embodiment, the reading method is the same as that in the second embodiment. As shown in FIG. 24, for example, when reading the memory cell (T21a) in 1-bit units, the bit line B1 reads the memory cell (T21a) and the bit line B2 reads the dummy cell (Tr1). Further, as shown in FIG. 25, for example, when all the memory cells connected to one word line W2a are read at a time, the memory cells are read via the bit lines B1, B3, etc.
The dummy cells are read out via the bit lines B2, B4 and the like.

[0089] Next, FIG. 26 (a), the with reference to (b), that describes the structure of the memory cell of the semiconductor memory device of this embodiment. In the fifth embodiment, one for two word lines
While are disposed source lines of this, in the seventh embodiment Ri points Do different that are disposed source lines of two every two word lines, cell Le area increases. However, the folded bit line structure of this embodiment is characterized in that the sensitivity of the sense amplifier can be generally increased.

The layouts shown in FIGS. 26A and 26B assume that the alignment margin of the mask is half of the design rule, and the cell area is one square of the design rule.
Although it is 6.5 times, the alignment margin of the mask depends on the exposure technology, and need not be limited to half of the design rule.

Further, in this embodiment, the floating gate memory cell having the offset region shown in FIG. 6 (the second embodiment) is employed. However, the present invention is not limited to this. The structure of the memory cell described in the embodiment can be applied.

[0092] Furthermore, the floating <br/> gate and the control gate and the source wiring in the present embodiment is set to be linear, may be partially deformed as needed, such as exposure technique.

[0093] Further, the source wiring in the present embodiment was to be a wiring material, may be formed by diffusion layers.

(Eighth Embodiment) Next, a semiconductor memory device according to an eighth embodiment will be described with reference to FIGS.
This will be described with reference to FIG. The block circuit diagram of the semiconductor memory device according to the present embodiment is the same as the block circuit diagram of the semiconductor memory device equipped with the conventional nonvolatile memory cell shown in FIG. FIG. 27 is a circuit diagram showing a part of the memory cell array of the flash EEPROM according to the present embodiment. The structure of the memory cell array in this embodiment is basically the same as the structure in the seventh embodiment, except that a diode is provided on the source side of the memory cell.

In this embodiment, the reading method is the same as that in the second embodiment. As shown in FIG. 28, for example, when the memory cell (T21a) is read in 1-bit units, the memory cell (T21a) is read through the bit line B1, and the dummy cell (Tr1) is read through the bit line B2. As shown in FIG. 29, for example, when all the memory cells connected to one word line W2a are to be read at once, the memory cells are read via bit lines B1, B3, etc. The dummy cell is read through.

Next, the structure of the memory cell of this embodiment will be described with reference to FIG. The memory cell structure of the present embodiment is almost the same as the structure of the memory cell of the sixth embodiment shown in FIG. 22, except that one source line is arranged for every two word lines in the sixth embodiment. On the other hand, in this embodiment, two source lines are arranged for two word lines, and the cell area increases. However, the folded bit line structure of this embodiment is characterized in that the sensitivity of the sense amplifier can be generally increased.

In the layout shown in FIG. 30, the alignment margin of the mask is assumed to be half of the design rule, and the cell area is 16.5 times the square of the design rule. It depends on technology and does not have to be limited to half the design rule.

Although the present embodiment employs the floating gate memory cell having the offset region shown in FIG. 6 (second embodiment), the present invention is not limited to this. The structure of the memory cell described in the embodiment can be applied.

[0099]

According to the semiconductor memory device of the present invention, in an array in which memory cells are arranged in a matrix, a bit line-
In each path between transistors, the transistor direction is
In this configuration, the erroneous reading can be prevented and the power consumption can be reduced.

In particular, by connecting each pair of memory cells to a common bit line and arranging only one source line for two word lines, a remarkable improvement in the degree of integration can be achieved. Can be planned.

Further, by providing a dummy cell and a folded bit line structure, the sensitivity of the sense amplifier can be set high, and the effect of preventing erroneous reading can be remarkably exhibited.

According to the method for driving a semiconductor memory device of the present invention,
If, at the time of reading Heading, the potential relationship between the bit line and the source line of the non-selected memory cell has to be set so as to reverse different directions resistance portion, the reduction of the leakage current in the unselected memory cells, It is possible to prevent erroneous reading and reduce power consumption.

[0103] In particular, by writing that uses the injection of Ho Tsu door electrons, it is possible to achieve a smooth and recovery of writing and a depletion of the memory cell to the memory cell.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a memory cell array according to a first embodiment.

FIG. 2 is a longitudinal sectional view showing a change in the structure in a process up to the formation of an n + layer in the process of manufacturing the memory cell according to the first embodiment.

FIG. 3 is a longitudinal sectional view showing a change in the structure in the process from the formation of the SiO2 film to the formation of the Schottky diode in the memory cell manufacturing process according to the first embodiment.

FIG. 4 is an electric circuit diagram showing a 1-bit read operation of the memory cell array according to the first embodiment.

FIG. 5 is an electric circuit diagram showing a collective read operation of all memory cells on one word line of the memory cell array according to the first embodiment.

FIG. 6 is a vertical cross-sectional view showing a change in structure in a manufacturing process of a memory cell according to a second embodiment.

FIG. 7 is a diagram illustrating a simulation result of a voltage-current characteristic of a memory cell according to a second example.

FIG. 8 is an electric circuit diagram of a memory cell array according to a second embodiment.

FIG. 9 is an electric circuit diagram showing a 1-bit read operation of the memory cell array according to the second embodiment.

FIG. 10 is an electric circuit diagram showing a collective read operation of all memory cells on one word line of the memory cell array according to the second embodiment.

FIG. 11 is a longitudinal sectional view showing a change in a structure in a manufacturing process of a memory cell according to a third embodiment.

FIG. 12 is a diagram showing a simulation result of a voltage-current characteristic of a memory cell according to a third example.

FIG. 13 is a longitudinal sectional view showing a change in structure in a process up to the formation of an n + layer in the process of manufacturing the memory cell according to the fourth embodiment.

FIG. 14 is a longitudinal sectional view showing a structural change in a process from the formation of an SiO2 film to the formation of a PN diode in the memory cell manufacturing process according to the fourth embodiment.

FIG. 15 is an electric circuit diagram of a memory cell array in a fifth embodiment.

FIG. 16 is an electric circuit diagram showing a read operation of the memory cell array in the fifth embodiment.

FIG. 17 is a longitudinal sectional view and a plan view showing a structure of a memory cell according to a fifth embodiment in a section parallel to a bit line.

FIG. 18 is a plan view showing a state after a first patterning of a floating gate of a memory cell according to a fifth embodiment.

FIG. 19 is a longitudinal sectional view showing a structure of a memory cell according to a fifth embodiment in a section parallel to a word line.

FIG. 20 is an electric circuit diagram of a memory cell array according to a sixth embodiment.

FIG. 21 is an electric circuit diagram showing a read operation of the memory cell array according to the sixth embodiment.

FIG. 22 is a longitudinal sectional view showing a structure of a memory cell according to a sixth embodiment in a section parallel to a bit line.

FIG. 23 is an electric circuit diagram of a memory cell array according to a seventh embodiment.

FIG. 24 is an electric circuit diagram showing a 1-bit read operation of the memory cell array according to the seventh embodiment.

FIG. 25 is a diagram illustrating a collective read operation of all memory cells on a word line of a memory cell array according to a seventh embodiment.

FIG. 26 is a longitudinal sectional view and a plan view showing a structure of a memory cell according to a seventh embodiment in a section parallel to a bit line.

FIG. 27 is an electric circuit diagram of a memory cell array according to an eighth embodiment.

FIG. 28 is an electric circuit diagram showing a 1-bit read operation of the memory cell array according to the eighth embodiment.

FIG. 29 is an electric circuit diagram showing a collective read operation of all memory cells on a word line of the memory cell array according to the eighth embodiment.

FIG. 30 is a longitudinal sectional view showing a structure of a memory cell according to an eighth embodiment in a section parallel to a bit line.

FIG. 31 is a block diagram showing a schematic configuration of an entire conventional semiconductor memory device.

FIG. 32 is an electric circuit diagram of a conventional memory cell array.

FIG. 33 is an electric circuit diagram showing a read operation of a conventional memory cell array.

[Explanation of symbols]

 W word line B bit line S source line D diode SA sense amplifier ST column selection transistor SD source decoder RD row decoder 1 semiconductor substrate 2 tunnel SiO2 film 3 floating gate 4 capacitance insulating film 5 control gate 6 SiO2 film 7 resist 9 n- Layer 10 resist 21 n + layer 22 SiO2 film 28 side wall 25 WSix film 101 memory cell array 102 row decoder circuit 103 column decoder circuit 104 source decoder circuit

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Toshiki Mori 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-5-198190 (JP, A) JP-A-5-267687 (JP, A) JP-A-51-57255 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) G11C 16/00-16/34 H01L 27/10 H01L 29/78

Claims (11)

(57) [Claims] 1. An array in which nonvolatile memory cells each having at least a transistor including a gate, a source, and a drain and a capacitor are arranged in a matrix, and connected to a gate of each transistor arranged in a row direction of the array. A plurality of word lines, a plurality of bit lines connected to a drain of each transistor arranged in a column direction of the array, and a plurality of bit lines connected to a source of each transistor arranged in a row direction of the array. A source line, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and between the bit line and each transistor. interposed, different voltages by the level of the voltage applied across - shows the current characteristics, and the opposite direction is likely to forward the current flows It has a direction opposite the flow does not easily flow from the bit line
A semiconductor memory device, comprising: a different-direction resistance section whose forward direction is toward the transistor . 2. The semiconductor memory device according to claim 1, wherein said different-direction resistance section is a diode that allows a current to flow in only one direction. 3. The semiconductor memory device according to claim 2, wherein the diode is formed by directly depositing a conductive film on a surface of a region of a semiconductor substrate constituting a drain of each of the transistors. A semiconductor memory device being a Schottky diode. 4. The semiconductor memory device according to claim 2, wherein said diode is formed between a region in a semiconductor substrate constituting a drain of each of said transistors and a contact region of said semiconductor substrate. A semiconductor memory device comprising a PN diode. 5. An array in which non-volatile memory cells having at least a transistor comprising a gate, a source and a drain and a capacitor are arranged in a matrix, and connected to a gate of each transistor arranged in a row direction of the array. A plurality of word lines, a plurality of bit lines connected to a drain of each transistor arranged in a column direction of the array, and a plurality of bit lines connected to a source of each transistor arranged in a row direction of the array. A source line, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and the source via the transistor from the bit line. A voltage-current characteristic is provided at least at a part of each path leading to the line, and varies depending on the level of the voltage applied to both ends. A reverse direction resistance portion having a forward direction in which a current easily flows and a reverse direction in which a current does not easily flow, wherein the reverse direction resistance portion includes one of a source and a drain of each transistor and a channel region below a gate. A semiconductor memory device characterized by being an offset region formed by introducing an impurity of the same conductivity type as that of the channel region. 6. The semiconductor memory device according to claim 1, wherein the drains of each pair of memory cells of said memory cells are connected to a common bit line, and each of said pair of memory cells is connected to one bit in a column direction. An array structure is arranged alternately and arranged in a checker pattern matrix. One source line is arranged at a ratio of one source line to the two word lines, and is adjacent to each one source line. A semiconductor memory device, wherein a source of a memory cell connected to two word lines is commonly connected to each one of the source lines. 7. An array in which non-volatile memory cells having at least a transistor including a gate, a source, and a drain and a capacitor are arranged in a matrix, and connected to a gate of each transistor arranged in a row direction of the array. A plurality of word lines, a plurality of bit lines connected to a drain of each transistor arranged in a column direction of the array, and a plurality of bit lines connected to a source of each transistor arranged in a row direction of the array. A source line, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and the source via the transistor from the bit line. A voltage-current characteristic is provided at least at a part of each path leading to the line, and varies depending on the level of the voltage applied to both ends. A sense amplifier that requires a reference potential; a sense amplifier that requires a reference potential; and a dummy cell for reference on the bit line. On the other hand, a semiconductor memory device that generates the reference potential. 8. An array in which nonvolatile memory cells each having at least a transistor including a gate, a source, and a drain and a capacitor are arranged in a matrix, and connected to a gate of each transistor arranged in a row direction of the array. A plurality of word lines, a plurality of bit lines connected to a drain of each transistor arranged in a column direction of the array, and a plurality of bit lines connected to a source of each transistor arranged in a row direction of the array. A source line, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and a circuit between the bit line and each transistor. It is interposed and shows different voltage-current characteristics depending on the level of the voltage applied to both ends. If you are have a and direction, the bit line
And a different direction resistance portion having a forward direction from the transistor to the transistor, wherein a bit line connected to a memory cell from which data is desired to be read is selected by the column decoder circuit. Then, a source line connected to the memory cell is selected by the source decoder circuit, and the potentials of the selected bit line and the selected source line match in the forward direction of the different-direction resistance portion of the memory cell. And the high potential side is set to the read potential, and the potential of the unselected source line is set to be higher than the lower potential side of the selected bit line and the selected source line and lower than the read potential. And a method for driving a semiconductor memory device. 9. An array in which nonvolatile memory cells having at least a transistor including a gate, a source, and a drain and a capacitor are arranged in a matrix, and connected to a gate of each transistor arranged in a row direction of the array. A plurality of word lines, a plurality of bit lines connected to a drain of each transistor arranged in a column direction of the array, and a plurality of bit lines connected to a source of each transistor arranged in a row direction of the array. A source line, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and the source through the transistor from the bit line. It is interposed at least in part of each path leading to the line, and shows different voltage-current characteristics depending on the level of the voltage applied to both ends, A different direction resistance portion having a forward direction in which a current easily flows and a reverse direction in which a current hardly flows, a sense amplifier requiring a reference potential, and a dummy cell for reference on the bit line, and one of bit lines adjacent to each other A method for driving a semiconductor memory device configured to generate the reference potential, comprising: selecting a dummy memory cell connected to a bit line adjacent to the selected bit line; The potential of the bit line adjacent to the selected bit line is set to the same potential as the potential of the selected bit line, and the potential relationship between the bit line and the source line connected to the selected dummy cell is in the forward direction of the different direction resistance portion of the dummy cell. Setting the potential of the source line connected to the selected dummy cell as described above, and generating the reference potential on the adjacent bit line. A method for driving a semiconductor memory device. 10. The method of driving a semiconductor memory device according to claim 8, wherein all word line potentials are set to the ground potential at the time of reading. 11. An array in which non-volatile memory cells having at least a transistor having a gate, a source, and a drain and a capacitor are arranged in a matrix, and connected to a gate of each transistor arranged in a row direction of the array. A plurality of word lines, a plurality of bit lines connected to the drain of each transistor arranged in the row direction of the array, and a plurality of bit lines connected to the source of each transistor arranged in the row direction of the array. A source line, a decoder circuit for selecting the word line, a decoder circuit for selecting the bit line, a decoder circuit for selecting the source line, and a decoder circuit for selecting the source line .
Interposed between, different voltages by the level of the voltage applied across - shows the current characteristics, have to have a reverse direction of current flow easily forward and current hardly flows, the bit line
And a different direction resistance portion having a forward direction from the transistor to the transistor, wherein the different direction resistance portion is formed so that the forward direction of the different direction resistance portion is at a higher potential on the bit line side. The threshold voltage of the memory cell in the state is set to be negative, the bit line connected to the memory cell for which data writing is desired is selected by the column decoder circuit, and the source line connected to the memory cell is selected. Selected by a source decoder circuit, all word line potentials are set to ground potential, the selected bit line is set to high potential, the selected source line potential is set to ground potential, unselected bit lines are set to ground potential, A semiconductor device characterized in that hot electrons are generated by flowing a current between selected source lines to change the threshold voltage of the desired memory cell to a high level. The driving method of the memory device.