JP3186168B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a nonvolatile semiconductor memory device, for example, having two layers of electrodes, a floating gate and a control gate. The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device such as an EPROM in which a memory cell portion and a peripheral transistor having one gate electrode layer for controlling the memory cell are formed on the same semiconductor substrate.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor memory devices increases, miniaturization advances and the manufacturing process thereof becomes complicated. 2. Description of the Related Art In the manufacture of a nonvolatile semiconductor memory device, for example, an EPROM, the manufacturing process becomes complicated and more difficult due to the special structure of a MOS transistor manufactured therein. EPROM is a normal static RAM (SRAM)
Unlike a memory transistor used in a semiconductor device, the gate portion has a two-layer structure of a floating gate and a control gate, as described later.

[0003] As a basic circuit of an EPROM, for example, Japanese Patent Publication No. 51-31073 discloses a pair of P ^{+ -type} source / drain regions formed on the surface of an N-type silicon substrate and a thickness of 500 to 1000 mm. A floating gate type EPROM comprising a floating gate electrode formed via a gate insulating film and a silicon oxide surrounding the floating gate electrode is described. Further, as an EPROM having a higher integration density, an EPROM in which a control gate is formed on a floating gate is known (for example, JP-A-1-300570). Referring to FIG. 9, a method of manufacturing an EPROM in which a control gate is formed on a conventional floating gate will be described.

As shown in FIG. 9A, a plurality of memory cell MOS transistor regions 20 (only one memory cell MOS transistor region 20 is shown for the sake of illustration), and these memory cell MOS transistors are controlled. A plurality of peripheral MOS transistor regions 10 (only one peripheral MOS transistor region 10 is shown for illustrative purposes) are formed on the same silicon substrate 1. Therefore, silicon dioxide (SiO ₂ )
Is formed, a tungsten (W) polycide layer (or polysilicon layer) 5 is formed on the gate oxide film 3, a silicon dioxide film 7 is further formed, and a W polycide layer ( Alternatively, a polysilicon layer) 11 is formed. In order to form a gate electrode layer of the MOS transistor in the peripheral MOS transistor region 10, a photoresist film 15 is provided above the gate forming region of the peripheral MOS transistor. Similarly, in order to form a control gate in the memory cell MOS transistor region 20, a photoresist film 17 is provided above the control gate formation region.

As illustrated in FIG. 9B, dry etching is performed entirely on the resist film 15 and the resist film 17. As a result, the W polycide layer 5 and the silicon dioxide film 7 excluding the region protected by the resist film 15 in the peripheral MOS transistor region 10 are removed. The remaining portion of the W polycide layer 5 becomes the peripheral MOS transistor gate 19. Also in the memory cell MOS transistor region 20, the W polycide layer 11 and the silicon dioxide film 7 excluding the lower portion of the resist film 17 are removed. The remaining W polycide layer 11 becomes the control gate portion 21. The resist film 15 is formed by dry etching.
In addition, the head corner of the resist film 17 is considerably removed, and the head is rounded.

As illustrated in FIG. 9C, a photoresist film 51 is further coated on the upper portion. The etching is performed again from above the memory cell MOS transistor region 20 while leaving the peripheral MOS transistor region 10 as it is. As a result, the portion 17B indicated by the broken line is removed from the resist film 51 in the memory cell MOS transistor region 20. When the etching further proceeds, the W polycide layer 5 and the gate oxide film 3 under the resist film 17A in the memory cell MOS transistor region 20 are removed except for the resist film 17, as shown in FIG. A floating gate portion 27 is formed.

After that, as shown in FIG.
Transistor source region 31 and drain region 32
Is formed by LDD ion implantation to form silicon dioxide sidewalls 37A and 37B on the peripheral MOS transistor gate 19, and a peripheral MOS having a gate 19, a source region 31, and a drain region 32 on the peripheral MOS transistor region 10. A transistor is formed. The memory cell MOS transistor region 20
In this case, the cell MOS transistor source region 33 and the drain region 34 are formed by LDD ion implantation, and the side wall 38 of silicon dioxide is formed.
A and 38B are formed, and a source region 33, a drain region 34, a floating gate 27 and a control gate 21 are formed in the memory cell MOS transistor region 20.
Is formed. Thereafter, an insulating film, a contact, and the like are formed on the partial layer of the EPROM illustrated in FIG. 10 to complete the EPROM.

[0008]

As illustrated in FIG. 9C, when etching the memory cell MOS transistor region 20, the resist film 17 above the control gate portion 21 is considerably removed. In FIG. 9C,
The resist film 17 which was originally up to the resist film 17B shown by the broken line is thinned by the above etching to the thickness of the resist film 17A shown by the solid line. Further, as illustrated in FIGS. 9D and 10, at the stage of forming the floating gate portion 27, the control gate portion 21 </ b> B indicated by the broken line is removed and the thickness of the control gate portion 21 </ b> A alone is removed. To decrease. That is,
The control gate portion 21 above the floating gate portion 27 is etched in the above-described etching process, and its thickness is reduced, so that a problem that a desired thickness cannot be maintained is encountered.

The above-described problem is caused by the peripheral MOS transistor gate portion 19 as one electrode layer of the peripheral MOS transistor region 10 and the floating gate portion 2 formed of the same layer as the peripheral MOS transistor gate portion 19.
7 and the memory cell section having two layers of electrodes on the same silicon substrate 1 by the same process.

In the above-described example, an EPROM is exemplified as the nonvolatile semiconductor memory device. However, the present invention is not limited to the nonvolatile semiconductor memory device as well as the EPROM, and a plurality of layers of electrodes may be formed on the same semiconductor substrate by the same process. In the case of a semiconductor device in which an electrode region of a different layer is formed while partially sharing an electrode layer, the same problem as described above is encountered. Accordingly, the present invention relates to a nonvolatile semiconductor memory device such as an EPROM, for example, comprising a circuit having the above-described two-layered electrode and a transistor having a gate formed on the same layer as one of the two layers on the same semiconductor substrate. Of high quality EPROM, which solves the problem of
For example, it is an object of the present invention to be able to manufacture a nonvolatile semiconductor memory device. Another object of the present invention is to provide a semiconductor device having a plurality of electrode layers in which different electrode regions are formed in the same manner as in the above-described nonvolatile semiconductor memory device, and to be formed in the same manner as described above.

[0011]

According to a first aspect of the present invention, there is provided a memory cell having two electrode layers and a memory cell having one of the two electrode layers. In a method of manufacturing a nonvolatile semiconductor memory device in which a peripheral transistor having a common gate electrode layer is formed on the same semiconductor substrate, at least a first layer on the semiconductor substrate is provided.
A gate electrode layer is deposited, and the gate of the peripheral transistor section is formed.
After forming the gate electrode and the diffusion region,
Coated with titanium film or titanium silicide film
The upper electrode layer of the memory cell is formed
A method for manufacturing a nonvolatile semiconductor memory device is provided.

According to a second aspect of the present invention, there is provided a memory cell having two electrode layers and a peripheral transistor having a gate electrode layer common to any one of the two electrode layers. In the method for manufacturing a nonvolatile semiconductor memory device in which the semiconductor substrate is formed on the same semiconductor substrate, at least the semiconductor substrate
A first gate electrode layer is deposited on the
After forming the gate electrode and diffusion region of the star,
The surface of the side transistor is covered with tungsten film
A method for manufacturing a nonvolatile semiconductor memory device, wherein an upper electrode layer of the memory cell is formed in this state .

[0013]

For example, when patterning a control gate of an EPROM memory cell by etching,
A titanium film, a titanium silicide film, or a tungsten film is used as a protective film for protecting a gate portion of a peripheral transistor and a source and a drain of the peripheral transistor formed from the same material as the control gate from etching. As a result, the control gate can be formed by a simple process without damaging the peripheral transistor. That is, when a titanium layer, a titanium silicide layer, or a tungsten film is used as a protective film, removal after use is easy and selectivity is improved.

Titanium silicide is formed above the source and drain of the peripheral transistor to reduce the resistance,
Improve operating speed. When a titanium silicide film is formed above the source and drain of the transistor of the memory cell, the operation speed of the memory cell is also improved. The nonvolatile semiconductor storage device is preferably an EPROM.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention, a method for manufacturing an EPROM will be exemplified. This embodiment and an example in which a titanium or titanium silicide film is used as a protective film will be described. Figures 1-3 are EPROM
FIG. 4 is a manufacturing process diagram illustrating the manufacturing method of FIG. FIG. 3 particularly shows a partial cross-sectional view of the EPROM in a substantially final manufacturing stage.
The partial cross-sectional configuration of the EPROM shown in FIG.
A representative one of a plurality of peripheral MOS transistor regions 10 is shown, and a typical one of a plurality of memory cell MOS transistor regions 20 is shown. FIG.
The LOCOS region 36 shown in FIG.

In the EPROM, an element isolation (LOCOS) region 36 as shown in FIG. 10 is formed on the silicon substrate 1, and a peripheral MOS transistor region 10 and a memory cell MOS transistor region 20 are formed with the LOCOS region 36 as a boundary. Is done. The memory cell MOS transistor region 20 is formed by a memory cell MO formed on the silicon substrate 1.
S transistor source region 33 and drain region 3
4, a gate oxide film formed on the silicon substrate 1,
Floating gate portion 27, silicon dioxide film 7, control gate portion 21 formed on gate oxide film 3, and these gate oxide film 3, floating gate portion 27, silicon dioxide film 7, and formed on side walls of control gate portion 21. Silicon oxide sidewalls 38A, 3
8B. A titanium silicide (TiSi ₂ ) film 69B is formed above the control gate portion 21, and titanium silicide films 69A and 69C are formed also above the source region 33 and the drain region 34.

The peripheral MOS transistor region 10 is located within the silicon substrate 1 and has a titanium silicide film 67, respectively.
The source region 31 and the drain region 32 formed under A ′ and 67B ′, the gate oxide film 3 formed on the silicon substrate 1, the gate portion 19 formed on the gate oxide film 3, and the gate It has silicon dioxide sidewalls 37A and 37B formed on the sidewall of the portion 19. Peripheral MO
On the S transistor gate portion 19, a titanium silicide film 65 'is formed. Above the peripheral MOS transistor region 10 and the memory cell MOS transistor region 20, an insulating layer, an electrode layer connected via a contact, and the like are formed. However, since they are not directly related to the present invention, their illustration is omitted. I have.

A method for manufacturing an EPROM will be described with reference to FIGS. 1 to 3 illustrate a continuous manufacturing method, but the drawings are divided for the sake of illustration. FIG.
1A, a gate oxide film 3 is formed entirely on a silicon substrate 1, and a polysilicon layer 5 serving as a peripheral MOS transistor gate portion 19 and a floating gate portion 27 is formed thereon. For the peripheral MOS transistor region 10, a gate portion 19, silicon dioxide side walls 37A and 37B are formed, and a source region 31 and a drain region 32 are formed in an LDD structure. In the memory cell MOS transistor region 20, a silicon dioxide film 7 serving as a gate oxide film of the control gate portion 21 is formed on the polysilicon layer 5.

As shown in FIG. 1B, a titanium film 25 is entirely deposited. As an example of the deposition conditions for the titanium film 25, argon gas (Ar) 50 sccm, 0.47 Pa , DC power 4K by sputtering is used.
W, 200 degrees Celsius, deposition thickness 30 nm .
Thereafter, as shown in FIG. 1C, titanium in contact with silicon is reacted by a two-step annealing method to form a silicide to form a titanium silicide film. as a result,
Peripheral MOS transistor / source region 31, gate 1
Titanium silicide films 67A, 67B, 67C are formed on top of the drain region 9 and the drain region 32. Since the peripheral MOS transistor region 10 is covered with the silicon dioxide film 7, no titanium silicide film is formed.

As shown in FIG. 1D, a polysilicon layer 11 serving as a control gate portion 21 is deposited above the peripheral MOS transistor region 10 and above the silicon dioxide film 7 in the memory cell MOS transistor region 20. Further, a photoresist film 17 is provided above a portion where the control gate portion 21 is formed.

As shown in FIG. 2A, the control gate portion 21 is patterned. As an etching method in this patterning, it is preferable to etch the polysilicon layer 5 (SF ₆ + C ₂ Cl ₃ F).
₃ ) Perform dry etching using gas. An example of the etching conditions is as follows: SF ₆ / C ₂ Cl ₃ F ₃ =
This is dry etching at 75 sccm / 8 sccm, 6.7 Pa , 1350 W. Control gate section 21
During the formation, the polysilicon layer 11 above the peripheral MOS transistor region 10 is also removed by etching, but the peripheral MOS transistor / source region 31 and the gate portion 19 are removed.
And the drain region 32 has a titanium silicide film 67.
Since it is covered with A, 65, 67B, it is not damaged by the above etching.

As shown in FIG. 2B, the floating gate portion 27 is patterned by dry etching. Also in this etching, the peripheral MOS transistor gate portion 19, the source region 31, and the drain region 32 are protected by the titanium silicide films 67A, 65, and 67B, and the peripheral MOS transistor portion is not damaged. However, in the etching process, the titanium silicide films 67A, 65, and 67B are somewhat damaged, and the titanium silicide films 67A ',
Somewhat thinner, as shown as 65 ', 67B'. In the conventional method, in this patterning, it is necessary to provide a resist in order to protect the memory cell MOS transistor region 20, but in the present embodiment, it is unnecessary, and the process is simplified. Since titanium silicide (TiSi ₂ ) is not easily etched by a fluorine-based gas, the selectivity is 1 compared to a silicon-based material.
0 or more, excellent in selectivity. Thus, by using the titanium film 25, only the control gate portion 21 and the floating gate portion 27 in the memory cell MOS transistor region 20 can be selectively and effectively etched by self-alignment.

As shown in FIG. 2C, silicon dioxide is deposited on the entire surface, and then the entire surface is etched back.
Silicon dioxide sidewalls 38A and 38B are formed on the sidewalls of control gate portion 21 and floating gate portion 27 in memory cell MOS transistor region 20.

Preferably, a titanium film 69 is further deposited as shown in FIG. Thereafter, annealing is performed to form a titanium silicide film 69A, 69B, 6 on the source region 33, the control gate portion 21, and the drain region 34 of the memory cell MOS transistor region 20.
9C is formed, and the unnecessary titanium film is removed. As a result, the peripheral MOS transistor region 10 and the memory cell MOS transistor region 2 having the structure shown in FIG.
0 is formed. Thereafter, LDD implantation, LDD side wall formation, source / drain ion implantation, and the like are performed. Thereafter, processes such as formation of an insulating tank, contact hole making, and electrode connection are performed to complete the EPROM.

As described above, in the first embodiment, the titanium silicide film 67 formed above the peripheral MOS transistor gate 19, the source region 31 and the drain region 32 when the control gate 21 is formed.
A, 65, 67B form the control gate portion 21
It becomes a protective film against etching at the time that, around MO
The S transistor region 10 is prevented from being damaged. Further, according to the present embodiment, the problem that the thickness of the control gate portion 21 is reduced does not occur. Peripheral MOS transistor
The titanium silicide films 67A 'and 67B' formed on the source region 31 and the drain region 32 lower the resistance values of the source region 31 and the drain region 32 and improve the operation speed of the peripheral MOS transistor. FIG.
The titanium film 69 shown in FIG.
Titanium silicide films 69A and 69C are formed above source region 33 and drain region 34 of S transistor region 20.
Is formed to reduce the resistance value, thereby improving the operation speed of the memory cell MOS transistor. That is, the operation speed of the EPROM is increased.

Instead of the titanium film 25 as the protective film for the memory cell MOS transistor region 20 described above, for example, a nitride film can be used. However, after use, a chlorine-based gas is used to remove the film. This means that silicon, polycide or tungsten polycide is also etched at the same time, which is not preferable. On the other hand, in this embodiment, only the titanium film can be easily removed selectively, and there is an advantage that the selectivity is increased. An advantage of using the titanium film 25 instead of the nitride film is that the film thickness can be reduced as much as possible. When a gate mask is formed, patterning is performed using a resist in advance. However, if the gate mask is thick, a change in patterning between the resist patterning and the shape after etching is likely to occur. For example, a nitride film is tapered due to a large gate mask thickness, and when a gate mask thickness of 0.4 μm is used to form a 0.5 μm pattern, the gate mask width is 0.65 μm. Therefore, it is preferable that the thickness of the gate mask be as thin as possible. If the titanium film of this embodiment is used, the selectivity between the mask material and the gate electrode material is sufficiently large. There is.

Various modifications can be made to the embodiment described above. For example, in the above embodiment, the example in which the gate portion 19 of the peripheral MOS transistor region 10 is formed on the same layer as the floating gate portion 27 of the memory cell MOS transistor region 20 has been described. You can also.

In the above embodiment, the control gate 21, floating gate 27 and peripheral MOS
As a material for forming the transistor gate portion 19,
Although an example using polysilicon has been described, other suitable materials for the electrode material, for example, tungsten (W) polycide having a smaller resistance value than polysilicon can be used. As a second embodiment of the nonvolatile semiconductor memory device of the present invention, an example of a method of manufacturing an EPROM using tungsten polycide for the control gate portion 121 and the floating gate portion 127 is shown in FIGS. Since the second embodiment is substantially the same as the first embodiment described above, a detailed description thereof will be omitted, but in FIG. 4A, the layer to be the peripheral MOS transistor gate portion 119 and the floating gate portion 127 is made of tungsten poly. 4D, the layer serving as the control gate portion 121 is formed with the tungsten polycide layer 111. The control gate portion 121 of the tungsten polycide layer 111 and the floating gate portion 1 of the tungsten polycide layer 105
As a gas for dry etching 27, preferably, (SF ₆ +
C ₂ Cl ₃ F ₃ ) gas is used. FIG. 6 shows a partial cross section of the EPROM corresponding to FIG.

Also in the second embodiment, in the process of forming the control gate portion 12, the peripheral MOS transistor region 10 is not damaged, and the control gate portion 21 does not become thin. In addition, the same effects as those of the first embodiment can be obtained in the second embodiment.
In the second embodiment, the control gate portion 21 is formed of a tungsten polycide layer having a lower resistance than polysilicon, and the operation speed is improved. However, from the viewpoint of improving the operation speed, it is not necessary to particularly form the floating gate portion 127 with the tungsten polycide layer 105, and the floating gate portion 27 can be formed with the polysilicon layer 5 as in the first embodiment. .

As a third embodiment of the nonvolatile semiconductor memory device according to the present invention, an EPROM manufacturing process will be described with reference to FIGS. This embodiment shows an example in which tungsten (W) is used as the protective film instead of titanium.
The manufacturing process shown in FIG. 7A is the same as the manufacturing process shown in FIG. As shown in FIG.
Tungsten films 125A and 125A are formed on gate portion 19, source region 31 and drain region 32 of peripheral MOS transistor region 10 by D-selective tungsten growth.
B, 125C are formed. Since the memory cell MOS transistor region 20 is covered with the silicon dioxide film 7, no tungsten film is formed. The conditions for CVD selective tungsten growth are: WF ₆ / SiH ₄ = 10 scc
CVD at m / 8 sccm, film formation temperature 250 degrees Celsius
Selective growth was performed. These tungsten films 125A, 1
25B and 125C are the titanium silicide films 67A (67A '), 65 (6) in the first and second embodiments described above.
5 ') and 67B (67B'), it functions as a protective film for the peripheral MOS transistor region 10.

The processes shown in FIGS. 7C and 8A to 8C are the same as the processes of the first and second embodiments. However, the processes shown in FIGS. 2D and 5D are omitted. As a result, an EPROM shown in FIG. 8C is formed. This EPROM has a peripheral MO
The gate portion 19 and the source region 3 of the S transistor region 10
1 and the drain region 32 are tungsten films 125A,
It is protected by 125B and 125C.

Also in the third embodiment, a tungsten polycide layer 111 can be used in place of the polysilicon layer 11. Further, a tungsten polycide layer 105 can be used instead of the polysilicon layer 5.

In the above embodiment, an example has been described in which titanium and tungsten are used as the protective film for the peripheral MOS transistor region 10. However, the gate film, particularly,
Etch control gate 21 (SF ₆ +
C ₂ Cl ₃ F ₃₎ may be used other materials that are not affected by the etching gas such as a gas.

In the above embodiments, an EPROM is exemplified as a nonvolatile semiconductor memory device. However, the present invention is not limited to a nonvolatile semiconductor memory device such as an EPROM, but is applicable to a case where a plurality of electrode layers are formed on the same semiconductor substrate. The present invention can also be applied to a semiconductor device in which the layers are partially different, for example, two layers in one part and three layers in another part.
The present invention is also applicable to a case where a plurality of electrode layers are formed in a three-dimensional semiconductor device or the like.

[0035]

As is clear from the above examples, according to the present invention using a titanium film (titanium silicide film) or a tungsten film as a protective film for a peripheral transistor,
The electrode layer can be formed by a simple process without damaging the electrode layer. Further, according to the present invention, the operation speed of the nonvolatile semiconductor memory device can be improved.

[Brief description of the drawings]

FIG. 1 is a first partial view illustrating a method for manufacturing an EPROM according to a first embodiment of a nonvolatile semiconductor memory device of the present invention;

FIG. 2 is a second partial view illustrating the method for manufacturing the EPROM of the first embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 3 is a third partial view illustrating the method for manufacturing the EPROM of the first embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 4 is a first partial view illustrating a method of manufacturing an EPROM according to a second embodiment of the nonvolatile semiconductor memory device of the present invention;

FIG. 5 is a second partial view illustrating the method for manufacturing the EPROM of the second embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 6 is a third partial view illustrating the method for manufacturing the EPROM of the second embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 7 is a first partial view illustrating a method of manufacturing an EPROM according to a third embodiment of the nonvolatile semiconductor memory device of the present invention;

FIG. 8 is a second partial view illustrating the method of manufacturing the EPROM according to the third embodiment of the nonvolatile semiconductor memory device of the present invention;

FIG. 9 is a diagram illustrating a conventional EPROM manufacturing method.

FIG. 10 shows an EP manufactured by the manufacturing method shown in FIG.
FIG. 3 is a partial sectional view of a ROM.

[Explanation of symbols]

1. Silicon substrate, 3. Gate oxide film, 5. Polysilicon layer, 7. Silicon dioxide film, 10. Peripheral MOS transistor region, 11. Polysilicon layer, 15, 17, Resist film, 19: Peripheral MOS transistor gate section, 20: Memory cell MOS transistor area, 21, 121: Control gate section, 23: Silicon dioxide film, 25: Titanium film, 27, 127: Floating gate section, 31 ..Peripheral MOS transistor source region, 32..peripheral MOS transistor drain region, 33..memory cell MOS transistor source region, 34..memory cell MOS transistor drain region, 36..LOCOS region, 37A, 37B ..Silicon dioxide side walls, 38A, 38B Titanium silicide film 65 'Titanium silicide film 65' Titanium silicide film 67, 67A, 67B Titanium silicide film 69 Titanium film 69A 69B 69C Titanium silicide film 105 Tungsten Polycide layer, 111..tungsten polycide layer, 125A-125C..tungsten film.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] 1. A non-volatile memory wherein a memory cell having two electrode layers and a peripheral transistor having a gate electrode layer in a layer common to any one of the two electrode layers are formed on the same semiconductor substrate. In a method for manufacturing a semiconductor memory device, at least a first gate electrode layer is deposited on a semiconductor substrate.
The gate electrode and the diffusion region of the peripheral transistor section.
After the region is formed, the surface of the peripheral transistor
With the above film covered with a titanium film or a titanium silicide film.
Method of manufacturing a nonvolatile semiconductor memory device which is characterized in that the formation of the upper electrode layer of Moriseru. 2. A titanium silicide film is formed on a source and a drain region of the memory cell portion.
The manufacturing method of the nonvolatile semiconductor memory device according to the above. 3. A non-volatile memory wherein a memory cell having two electrode layers and a peripheral transistor having a gate electrode layer in a layer common to any one of the two electrode layers are formed on the same semiconductor substrate. In a method for manufacturing a semiconductor memory device, at least a first gate electrode layer is deposited on a semiconductor substrate.
The gate electrode and the diffusion region of the peripheral transistor section.
After forming the region, the surface of the peripheral transistor
While covering with the gustene film,
A method for manufacturing a nonvolatile semiconductor memory device, comprising forming an extreme layer . 4. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile semiconductor memory device is an EPRO.
M, the memory cell has a control gate as an upper electrode layer and a floating gate as a lower electrode layer, and the peripheral transistor is a transistor for controlling the operation of the memory cell, and the gate electrode is a gate layer of the transistor. The nonvolatile semiconductor memory device according to claim 1, wherein: