JP3181771B2 - Driving method of liquid crystal panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display.
More specifically, the present invention relates to a driving method of a simple matrix panel using an STN liquid crystal or the like. More specifically, the present invention relates to a driving method suitable for a multiple line simultaneous selection method.

[0002]

2. Description of the Related Art Liquid crystal display devices are characterized by their small size, light weight, thinness, and low power consumption, and have an advantage over other display devices. Liquid crystal display devices are roughly classified into an active matrix type and a simple matrix type. The former is a method in which a liquid crystal is driven by attaching a three-terminal element such as a thin film transistor or a two-terminal element such as an MIM to each pixel, and can obtain the same contrast as in the static driving even if the number of divisions of the pixel is increased. However, since a thin film semiconductor element is formed for each pixel, the structure becomes complicated and the manufacturing cost increases as the area increases.
On the other hand, in the latter, a TN liquid crystal or an STN liquid crystal is held between a row-shaped scanning electrode and a column-shaped signal electrode, and has an advantage that the manufacturing cost is relatively low. However,
Since time division driving is performed by the voltage averaging method, when the number of divisions increases, the difference between the effective values at the time of ON and at the time of OFF becomes small, and the contrast decreases.

For reference, a brief description will be given of a voltage averaging method conventionally used as a driving method of a simple matrix type liquid crystal display device. In this method, each scan electrode is sequentially set to one.
The data signals corresponding to ON / OFF are supplied to all the signal electrodes in accordance with the selection timing. As a result, the voltage applied to each pixel is once (1) in one frame period for selecting all the scanning electrodes (N lines).
/ N minutes) high applied voltage and the remaining time ((N
-1) / N) is a constant bias voltage. When the response speed of the liquid crystal material used is low, a change in luminance according to the effective value of the applied voltage waveform in one frame period is obtained. However, if the frame frequency is lowered by increasing the number of divisions, the difference between the one-frame period and the response time of the liquid crystal becomes small, and the liquid crystal responds to each applied pulse, and a flicker of luminance called a frame response phenomenon appears and the contrast is reduced. descend. FIG. 15 is a graph showing the frame response phenomenon, in which the transmittance increases when the scanning electrode is selected, and decreases in the subsequent non-selection period.

As measures to cope with the problem of the frame response phenomenon in the voltage averaging method, "higher frequency" in which the width of the high voltage pulse is narrowed and "bias level optimization" in which the potential difference between the high voltage pulse and the bias voltage is reduced. Has been proposed. FIG. 16 is a graph showing the change in transmittance when the frequency is increased. As compared with the graph of FIG. 15, the frame frequency increases by the amount corresponding to the reduction of the pulse width. Since the high voltage pulse at the time of selection is applied in a short cycle, the next high voltage pulse is supplied before the transmittance is completely reduced, and the overall transmittance increases. However, there is a limit to this high frequency method, and the uniformity of an image is significantly impaired due to an increase in distortion of an applied waveform.

FIG. 17 is a graph showing a change in transmittance when bias level optimization is performed. By increasing the bias voltage level during the non-selection period, the difference between the effective value at the time of selection and at the time of non-selection becomes small, and FIG.
5, the decrease in the transmittance at the time of non-selection is reduced. However, there is a limit to this bias level optimization method, and changing the bias level lowers the ON / OFF voltage ratio, which is accompanied by deterioration of contrast.

As a consistent solution to such a problem of the voltage averaging method, the "multiple line simultaneous selection method (Multipl
e Line Selection) "has been proposed. For example, SI
Reported by Optrex in D1992
(SID '92 DIGEST pp232-235,1992). In a similar method, In Focus Systems, Inc. of the United States called the "Active Addressing Method".
(SID '92 DIGEST pp228-231, 1992). These simultaneous selection methods are based on the principle of higher frequency, but the conventional one
By selecting a plurality of lines at the same time instead of selecting each line, an effect equivalent to apparently increasing the frequency can be obtained. Since a plurality of lines are selected at the same time instead of selecting each line, a device is required to obtain an arbitrary display. That is, the original image signal needs to be processed and supplied to the signal electrode. The basic calculation method is TN
Ruckmongathan published in 1988 (1988 IDR
C, pp80-85, 1988).

Further, a “gray scale method by pulse voltage modulation of a simple matrix (Pulse-Height Modulation (PHM) Gray Shad” which can be combined with the above-described simultaneous selection method for a plurality of lines.
ingMethods for Passive Matrix). For example, in Japan Display 1992, there was a report by In Focus Systems of the United States (JAPAN DISP
LAY 1992-69). In this pulse voltage modulation gray scale method, a virtual scan line is provided in addition to a plurality of actual scan lines. Virtual display data is given to a pixel located on the virtual line. This virtual data is calculated based on display data (dot data) given to real pixels. On the other hand, the signal waveform to be supplied to each signal line is obtained by performing arithmetic processing on the actual display data and the virtual display data in accordance with the above-described multiple line simultaneous selection method. By providing the virtual line in this manner, a correct effective voltage according to the display data is applied to each pixel. In other words, the virtual line is provided for adjustment in order to apply a correct effective voltage according to the display data, and is not included in the actual liquid crystal panel electrode configuration.

[0008]

However, in order to apply the above-described method for simultaneously selecting a plurality of lines to driving of a simple matrix type liquid crystal panel, it is an object to realize a practical and efficient circuit configuration. Therefore, it is a first object of the present invention to provide a drive circuit configuration suitable for a multiple line simultaneous selection method.

In the multiple line simultaneous selection method, a matrix panel having a liquid crystal layer interposed between a row-shaped scanning electrode group and a column-shaped signal electrode group is driven based on dot data via a common driver and a segment driver. In this case, a set of orthogonal signals is sequentially supplied to a common driver to selectively drive scan electrode groups in a predetermined number of lines in a set order. A signal is supplied to a segment driver to drive a signal electrode group in synchronization with group sequential scanning. The common driver applies a set of orthogonal signals having a predetermined voltage level as scan signals to the scan electrodes. The segment driver receives a product-sum signal having a voltage level that varies according to dot data representing a display pattern, and supplies this as a data signal to a signal electrode. At this time, it is an issue to balance the breakdown voltage between the common driver and the segment driver in order to achieve the advantage of the hardware configuration and the common use of the driver IC components. Therefore, a second object of the present invention is to balance such a breakdown voltage.

In the multiple line simultaneous selection method, the quadrature signal applied to the scan electrode group may basically be of any waveform, but it is always necessary to scan all the simultaneously selected lines with voltage pulses of the same polarity. Occurs once during a cycle. On the other hand, the data signal waveform applied to each signal electrode line is obtained by the product-sum operation of the set of dot data and the set of orthogonal signals as described above. Therefore, if the dot data is an arbitrary display pattern, the bias voltage during the non-selection period is arbitrarily applied during a half cycle. However, if the display pattern is fully lit or completely unlit, the bias voltage during the non-selection period is simultaneously selected. All of the lines thus added are concentrated during the period of scanning with voltage pulses of the same polarity. For this reason, there is a problem that unevenness occurs in the optical response, and the contrast differs depending on the display pattern. Therefore, a third object of the present invention is to improve the unevenness of the optical response depending on the display pattern.

In the multiple line simultaneous selection method, the voltage applied to the scanning electrode line uses a quadrature signal as described above because the waveform of the simultaneously selected line must be different. Therefore, as the number of lines selected at the same time increases, the number of simultaneously selected lines 1
The frequency difference between the first line and the last line becomes large. On the other hand, the data signal applied to the signal electrode line is calculated by the product sum of the dot data and the orthogonal signal, and the bias voltage actually applied to the liquid crystal is a combination of the orthogonal signal and the data signal. When the number n of simultaneously selected lines is smaller than the square root of the number N of all lines, the voltage of the scanning electrode line becomes higher than the voltage of the signal electrode line, and the frequency of the synthesized waveform is dominated by the waveform on the scanning electrode line side. Conversely, when the number of simultaneously selected lines is larger than the square root of N, the voltage of the signal electrode line becomes higher than the scanning electrode line depending on the display pattern, and the frequency of the synthesized waveform is dominated by the waveform on the signal electrode side. In general, when driving a liquid crystal, there is a frequency characteristic, and the transmittance changes due to a difference in frequency. From the above, if the number n of simultaneously selected lines is relatively small compared to the number N of all lines, there is a difference in transmittance between the first line and the last line selected at the same time. There is a problem that uneven stripes appear horizontally depending on the width. Therefore, a fourth object of the present invention is to improve the unevenness of the stripe pattern due to such frequency dependency.

When gradation display is performed by pulse voltage modulation in the multiple line simultaneous selection method, virtual display dot data assigned to a virtual line is calculated based on actual dot data. In the case of gradation display, the dot data takes a continuous value from, for example, −1 to +1. In the pulse voltage modulation method, the value of the virtual dot data becomes maximum when the display dot data is 0, and is equal to the square root value of the total number N of lines. Accordingly, the value of the virtual dot data increases as the number N of all lines increases. For this reason, when the display pattern is at an intermediate level between the fully lit state and the completely unlit state, a voltage having a high pulse property is applied to the signal electrode line when the last plurality of lines including the virtual line are simultaneously selected. As mentioned above,
Since a high pulse voltage is applied to the signal electrode line depending on the display pattern, there is a problem that the frequency characteristic of the bias voltage applied to the liquid crystal changes, resulting in a difference in transmittance. Therefore, a fifth object of the present invention is to disperse a highly pulsed voltage generated when gradation display is performed by pulse voltage modulation and suppress a difference in transmittance due to frequency dependence of liquid crystal.

[0013]

A basic configuration of the present invention will be described with reference to FIG. As shown, the liquid crystal display device according to the present invention includes a matrix panel 1, a common driver 2, and a segment driver 3 as general components. The matrix panel 1 has a row of scanning electrode groups 4.
And a row of signal electrode groups 5 with a liquid crystal layer interposed therebetween. As the liquid crystal layer, for example, STN liquid crystal can be used. The common driver 2 is connected to the scanning electrode group 4 and drives the same. The segment driver 3 is connected to and drives the signal electrode group 5.

In order to achieve the first object of the present invention, a frame memory 6, orthogonal signal generating means 7, product-sum calculating means 8 and synchronizing means 9 are provided. The frame memory 6 holds the input dot data for each frame. The dot data is image data corresponding to a pixel (dot) defined at the intersection of the scanning electrode group 4 and the signal electrode group 5. The orthogonal signal generating means 7 generates a plurality of orthogonal signals having an orthogonal relationship to each other, sequentially supplies them to the common driver 2 in an appropriate combination pattern, and selects a scanning electrode group in a predetermined group according to the combination pattern. Drive. The drawing schematically shows an example in which three scanning electrodes are set as one set and driven simultaneously. The product-sum operation means 8 performs a predetermined product-sum operation between a set of dot data sequentially read from the frame memory 6 and a set of orthogonal signals transferred from the orthogonal signal generation means 7, and outputs the result to the segment driver 3. The signal is supplied to drive the signal electrode group 5. The synchronizer 9 synchronizes the timing of reading dot data from the frame memory 6 with the timing of signal transfer from the orthogonal signal generator 7. A desired image display can be obtained by repeating the group sequential scanning a plurality of times in one cycle. Note that the liquid crystal display device according to the present invention uses the R / W address means 10 to control writing / reading of dot data to / from the frame memory 6.
It has. The address means 10 is controlled by the synchronization means 9 and supplies a predetermined read address signal to the frame memory 6. In addition, it includes a drive control unit 11 and supplies a predetermined clock signal to the common driver 2 and the segment driver 3 under the control of the synchronization unit 9.

Hereinafter, a case in which four scanning electrodes are simultaneously selected in the multiple line selection method will be described. FIG. 2 is a waveform diagram of the simultaneous driving of four lines. F ₁ (t) to F ₈ (t) indicate voltage waveforms applied to each scanning electrode, and G ₁ (t) to
G ₃ (t) indicates a voltage waveform applied to each signal electrode. The scanning signal waveform is set based on the Walsh function which is a perfect orthonormal function at (0, 1). 0
Is -Vr, 1 is + Vr, and the non-selection period is 0V.
And Four pairs are selected from the top as one set, and the pairs are sequentially scanned downward. Four scans correspond to one cycle of the Walsh function, and the first half cycle ends. In the next one cycle, the polarity is inverted so that the latter half cycle is performed so that the DC component does not enter.

On the other hand, with respect to the voltage waveform applied to each signal electrode, each dot data is represented by I _ij (i represents the row number of the matrix, and j represents the same column number). _{If ij} = −1 and I _ij = + 1 when OFF, the data signal G _j (t) given to each signal electrode
Is basically set by performing the following product-sum operation processing.

[0017]

(Equation 7)

However, since the scanning signal voltage during the non-selection period is at the 0 level, the summation processing in the above equation is the sum of only the selected lines. Therefore, in the case of simultaneous selection of four lines, the potential that can be taken by the data signal is five levels. That is, the potential level required for the data signal is (the number of simultaneous selections +
1) It becomes pieces.

FIG. 3 is a waveform diagram showing the Walsh function. In the case of simultaneous selection of four lines, for example, four Wa
A scan signal waveform is created using the lsh function. As can be understood by comparing FIGS. 2 and 3, for example, F ₁ (t) is 1
This corresponds to the Walsh function W1. Since W1 is made all over one period a high level, F ₁
The four pulses of (t) are arranged as (1,1,1,1). F ₂ (t) corresponds to the second Walsh function W2. W2 goes high in the first half of one cycle and goes low in the second half. Accordingly, the pulses included in F ₂ (t) are arranged as (1,1,0,0). Similarly, F ₃ (t) is the third Walsh function W3
, And the pulses are arranged as (1, 0, 0, 1). Further, F ₄ (t) is the fourth Wals
h function W4, and its pulse is (1, 0,
1,0). As is apparent from the above description, the scanning signals applied to one set of scanning electrodes are appropriately combined patterns (1,1,1,1),
(1,1,0,0), (1,0,0,1), (1,0,
1,0). In the case of FIG. 2, the quadrature signal F ₅ according to the same combination pattern also applies to the second set.
(T) to F ₈ (t) are applied. Similarly, a predetermined scanning signal is applied to the third and subsequent sets according to the same combination pattern.

As described above, according to the multiple line simultaneous selection method, the interval between the high voltage pulses is reduced, and the same effect as that of the high frequency can be obtained without reducing the pulse width. Also, the potential difference between the high voltage pulse and the bias voltage decreases, and the ON / OFF
The bias voltage can be increased without deteriorating the selectivity,
Deterioration of contrast due to frame response can be suppressed. FIG. 4 is a graph showing the dependence of the contrast ratio on the row selection period of the scan electrode in 1/240 Duty drive. As is clear from the figure, the contrast ratio of the multiple line simultaneous selection method is improved as compared with the voltage averaging method. The features of the multiple simultaneous selection method include suppression of frame response in a high-speed driving liquid crystal display device, improvement in uniformity of display quality, reduction in supply voltage, removal of DC components, and the like.

Next, means for achieving the second object of the present invention will be described. That is, in the method of simultaneously driving a plurality of lines of a simple matrix type liquid crystal panel, a means of optimizing the number of lines of the scanning electrodes which are simultaneously selected for each group is taken.
A balance has been achieved between the withstand voltage of the segment driver and the withstand voltage of the common driver. Specifically, assuming that the total number of lines of the scan electrode group is N, the number n of lines of the scan electrodes included in each part is n
Is set near the square root of N. In general, as the number of lines of the scanning electrodes simultaneously selected for each set increases, the order of the orthogonal signal also increases accordingly. That is, since the number of selection pulses included in one cycle increases, the dispersion of the voltage proceeds,
The pulse voltage level of the quadrature signal decreases. Therefore, the larger the number of simultaneously selected lines, the lower the withstand voltage required for the common driver. On the other hand, as the number of simultaneously selected lines increases, the product-sum signal becomes more complicated and the number of required voltage levels increases.
As a result, when the number of simultaneously selected lines increases, the level of the product-sum signal increases, and the breakdown voltage required for the segment driver increases. Therefore, the withstand voltages of the common driver and the segment driver have a relationship opposite to each other with respect to the number n of simultaneously selected lines. Therefore, in the present invention, by optimizing the number n of simultaneously selected lines, the breakdown voltage of the segment driver and the breakdown voltage of the common driver are balanced.

Next, means for achieving the third object of the present invention will be described. In the multiple line selection method,
A plurality of lines are simultaneously selected from the top of the screen and scanned downward. At this time, by shifting the phase of the scanning signal waveform applied to the scanning electrodes when a plurality of scanning electrodes are simultaneously selected from the phase of the previously selected signal waveform, the bias applied to the liquid crystal during the non-selection period when all ON / OFF are displayed. Voltage is 1/2
Dispersion is performed without concentrating within one frame scanning period in a cycle. The phase difference is such that the function of the waveform applied to the scan electrode line is shifted by at least one cycle within one frame scanning period. Therefore, it is not always necessary to shift the phase between a plurality of adjacent lines, but it is also possible to shift the phase by one every several selections so as to shift one cycle within one frame scanning period. The same applies to the case where the screen is selected from bottom to top or randomly sequentially without scanning from top to bottom of the screen. In the multiple line selection method, as described above, the contrast differs depending on the display pattern, but the optical response becomes uniform by shifting the phase of the waveform of the scanning electrode line, so that all ON / O
The frame response and contrast at the time of FF can be improved.

Further, means for achieving the fourth object of the present invention will be described. In the multiple line selection method,
By simultaneously selecting a plurality of lines from the top of the screen and scanning downward, scanning from the top to the bottom a plurality of times allows one of the orthogonal functions
The cycle ends. At this time, the frequency of each line is made uniform by exchanging the waveform pattern of each line selected at the same time by using the scan signal waveform applied to the scan electrodes when a plurality of lines are simultaneously selected in the immediately preceding cycle and the next cycle. To eliminate the unevenness of horizontal stripes appearing in the width of the number selected at the same time. The replacement of the waveform pattern is such that the second pattern is shifted to the first line, the third pattern is shifted to the second line, and so on so that the orthogonal function pattern appears evenly on one line. It is best, but there is a certain effect simply by alternately switching the high frequency line and the low frequency line. Also, since the frequency of the waveform applied to the scanning electrodes is averaged, the waveform pattern of each line is replaced not only every cycle, but may be replaced every few cycles, and no DC component is applied to the liquid crystal. As long as the waveform pattern is selected in this manner, 1/2 cycle may be used. The above-described method is the same when the screen is selected from bottom to top or randomly sequentially without scanning from the top to the bottom of the screen. As described above, in the conventional method of selecting a plurality of lines, the stripe pattern unevenness occurs in the horizontal direction with the width of the number of lines selected at the same time. The frequency of the line averages,
The horizontal stripes disappear and the screen becomes uniform.

Finally, means for achieving the fifth object of the present invention will be described. That is, when performing gradation display by voltage modulation in the multiple line selection method, instead of providing a virtual line on the N + 1th line, a virtual line is provided every time a plurality of lines are selected, and the effective value concentrated on the N + 1th line is calculated. By dispersing the entire waveform, a high pulse voltage is not applied to the signal electrode line. Actually, the data of V _{(L + 1)} is calculated according to the following equation 8, and the data signal G _i (t) applied to the signal electrode line is calculated according to the following equation 9. That is, the voltage of the signal electrode line is determined by adding V _{(L + 1)} which is virtual data every time a plurality of lines are selected. At this time, V
_{(L + 1)} is √L / N times that of V _{(N + 1)} .
It is about 程度 L, and no high voltage is applied.

[0025]

(Equation 8)

[0026]

(Equation 9)

When gradation display is performed by the conventional multiple line selection method, there is a difference in transmittance depending on a display pattern. However, in the present invention, virtual line data is distributed and applied for each selection of a plurality of lines, so that actual data is applied. In the waveform applied to the liquid crystal, the frequency of the scanning electrode line becomes dominant irrespective of the display pattern, and the inside of the screen becomes uniform.

When a virtual line is provided every time a plurality of lines are selected, the effective value concentrated on the (N + 1) -th line is calculated every L lines and dispersed over the entire waveform, so that the signal electrode lines have high pulse characteristics. The voltage may not be applied. In this case, the data of V _kj is calculated according to the following equation 10, and the data signal G _j (t) applied to the signal electrode line is calculated according to the following equation 11. That is, the voltage of the signal electrode line is determined by calculating and adding V _kj , which is virtual data, for each selection of a plurality of lines. At this time, V _kj becomes ΔL at the maximum value, and no high voltage is applied.

[0029]

(Equation 10)

[0030]

[Equation 11]

When gradation display is performed by the conventional multiple line selection method, there is a difference in transmittance depending on the display pattern. In the waveform applied to the liquid crystal, the frequency of the scanning electrode line becomes dominant irrespective of the display pattern, and the inside of the screen becomes uniform.

As described above, the voltage of the signal electrode line is determined by calculating and adding virtual data V _kj for each selection of a plurality of lines. The V _kj added at this time may be calculated not from the selected L data but from the L data selected once or several times before as shown in the following Expression 12.

[0033]

(Equation 12)

By calculating the virtual data V _kj from the L data read from the memory at the time point selected once or several times before, the operation time in the drive circuit can be extended and simplified.

[0035]

According to the first aspect of the present invention, in order to perform practical and efficient driving suitable for simultaneous selection of a plurality of lines of a simple matrix type liquid crystal panel, a frame memory, a quadrature signal generating means and a product-sum calculating means are provided. It has synchronization means. The frame memory holds the input dot data for each frame. The orthogonal signal generating means generates a plurality of orthogonal signals having an orthogonal relationship with each other, sequentially supplies them to the common driver in an appropriate combination pattern, and selectively drives the scan electrode groups in a predetermined set according to the combination pattern. . The product-sum operation means performs a product-sum operation between the set of dot data and the set of orthogonal signals, and supplies the result to a segment driver to drive the signal electrode group. With such a configuration, a desired image is displayed by repeating the group sequential scanning a plurality of times in one cycle.

According to the second aspect of the present invention, a matrix panel having a liquid crystal layer interposed between a row-shaped scanning electrode group and a column-shaped scanning electrode group is provided based on dot data via a common driver and a segment driver. Drive. At this time, the sets of orthogonal signals are sequentially supplied to the common driver, and the scanning electrode groups are selectively driven for each predetermined number of lines. The product-sum signal obtained by the product-sum operation of the dot data set and the orthogonal signal set is supplied to the segment driver, and the signal electrode group is driven in synchronization with the set sequential scanning. In this case, the number of lines of the scanning electrodes that are simultaneously selected for each set is optimized to balance between the breakdown voltage of the segment driver and the breakdown voltage of the common driver. Specifically, assuming that the total number of lines of the scan electrode group is N, the number n of lines of the scan electrodes included in each set may be set near the square root of N.

According to the third aspect of the present invention, the phase of the orthogonal function is shifted every time a plurality of orthogonal functions are simultaneously selected, instead of using the same phase value of the orthogonal function in the entirety of a single scanning period. The bias voltage applied to the liquid crystal during the non-selection period when light-on or all-off display is performed is prevented from being concentrated in one scanning period in a half cycle. The phase difference is such that at least one orthogonal function defining the waveform of the scanning electrode line during one scanning is at least one.
It is shifted by the period. By replacing the phase of the waveform applied to the scanning electrode with the phase at the time of the previous selection, the difference in contrast depending on the display pattern can be suppressed, and the frame response can be reduced.

According to the fourth aspect of the present invention, the waveforms of the simultaneously selected scanning electrodes are exchanged every cycle, whereby
At the same time, it is possible to suppress the unevenness of the stripe pattern appearing in the horizontal direction with the width of the selected number, thereby making the screen uniform. In the multiple line simultaneous selection method, one cycle of the orthogonal function is completed by simultaneously selecting a plurality of lines from the top of the normal screen, scanning downward, and scanning a plurality of times from top to bottom. In this case, the scan signal waveform given to the scan electrodes when a plurality of scan electrodes are selected at the same time is
By replacing the waveform pattern of each line selected at the same time in the cycle and the next cycle, the frequency of each line is made uniform to eliminate the unevenness of the horizontal stripe pattern.

According to the fifth aspect of the present invention, in gradation display using pulse voltage modulation, instead of providing a virtual line at the (N + 1) th line, a virtual line is provided every time a plurality of lines are selected, and concentrated at the (N + 1) th line. By dispersing the effective value that has been applied to the entire waveform, a high pulse voltage is not applied to the signal electrode line. Therefore, a pulse having a high voltage is used only on the scanning electrode side which is not replaced by the display pattern, thereby making the screen uniform. Further, by calculating virtual dot data assigned to the virtual line for each of a plurality of lines selected at the same time, a voltage having a high pulse property is not applied to the signal electrode line. In this case, by calculating the virtual dot data based on past display data instead of present display data, it is possible to increase the speed and simplify the driving circuit.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 5 is a circuit diagram showing an embodiment embodying the basic circuit configuration shown in FIG. As shown in (A), this example includes a serial / parallel (S / P) conversion circuit 21 and converts input serial dot data into parallel dot data of every 8 bits. In addition,
The dot data is provided as a digital RGB signal.
The S / P conversion circuit 21 includes a plurality of memory units 22 to 2
5 is connected. Each memory unit corresponds to each row, and records dot data in units of 8 bits. For example, the first memory unit 22 records the dot data assigned to the first row by dividing the dot data into eight pieces. Similarly, the second memory unit 23 records the dot data assigned to the second row in units of 8 bits. Thus, the plurality of memory units 22 to 25 correspond to the frame memory 6 shown in FIG. In addition to a write timing generation circuit 26, which accepts a dot clock (Dot Clock), receives a frame signal FRM and clock signals CL1 and CL2 from the serial / parallel conversion circuit 21 and writes write signals WE, The write gate signal G and the read clock signal CK are output.

The clock signal CL1 corresponds to the bit arrangement of serial dot data, and the other clock signals CL2 correspond to 8-bit units. Further, a pair of a write address generation circuit 27 and a read address generation circuit 28 are provided, and are connected to the memory units 22 to 25 via an address switching circuit 29. The write address generation circuit 27 is connected to the write timing generation circuit 26 and receives the control thereof. As described above, the write timing generation circuit 26, the write address generation circuit 27, the read address generation circuit 28, and the address switching circuit 29 correspond to the R / W address means 10 shown in FIG. Incidentally, the read address generating circuit 28 is connected to the read timing generating circuit 30 and receives the control thereof. This read timing generation circuit 30
Corresponds to the synchronization means 9 shown in FIG.

As shown in FIG. 5B, the read timing generation circuit 30 is connected to a Walsh function generation circuit 31. This Walsh function generating circuit 31 corresponds to the orthogonal signal generating means 7 shown in FIG. Further, the read timing generation circuit 30 includes a drive signal generation circuit 32
And outputs a predetermined clock signal. This clock signal is used for drive control of the segment driver and the common driver. Therefore, the drive signal generation circuit 32 corresponds to the drive control unit 11 shown in FIG. The output of the Walsh function generation circuit 31 is connected to a common driver via a level conversion circuit 33. Finally, the output terminals of the memory units 22 to 25 and Walsh
Eight arithmetic unit units 34 to 41 are connected to the output terminal of the function generation circuit 31. These arithmetic unit units correspond to the product-sum operation means 8 shown in FIG. The eight computing unit units 34 to 41 correspond to each of the 8-bit dot data. For example, the first arithmetic unit 34 performs a product-sum operation on the signal electrodes in the first column to create corresponding data signals. Similarly, the second computing unit 35 performs a product-sum operation on the signal electrodes in the second column to create corresponding data signals. Similarly, the eighth computing unit 41 performs a product-sum operation on the signal electrodes in the eighth column to create corresponding data signals. The data signals for eight columns created in this way are transferred to the segment driver via the 8/4 conversion circuit 42.

The segment driver employed in this embodiment has a capability of receiving a data signal of 3 bits per dot and selecting a maximum of 8 voltage levels to output to the matrix panel. As described above, in the case of simultaneous selection of four lines, five levels are required as the signal voltage waveform, and this segment driver has the necessary capability. However, the number of data inputs at one time is limited to 3 bits × 4. Therefore, 8
Through the / 4 conversion circuit 42, signal data for four dots is transferred to the segment driver at one time. In this example, the common driver also has the same structure as the segment driver.

The operation of each part of the circuit shown in FIG. 5 will be described below in detail with reference to FIGS. FIG. 6 is a schematic block diagram for explaining the configuration and operation of each memory unit. Here, the first memory unit 22 is shown as an example, and includes a RAM memory 221. This RAM memory records, for example, dot data assigned to the first row in 8-bit units. An input buffer 222 is provided and 8
Temporarily holds dot data input in bit units.
The held dot data is recorded at a predetermined address of the RAM memory 221 based on a write address signal supplied from a write address generation circuit via an address switching circuit. Further, an output latch 223 is provided and the RAM 2
The dot data read from 21 is latched 8 bits at a time, and sequentially transferred and output to the arithmetic unit unit side. On this occasion,
The RAM memory 221 reads dot data via an address switching circuit in accordance with a read address signal supplied from a read address generation circuit. The input buffer 222 is controlled by the write gate signal G supplied from the write timing generation circuit,
23 is controlled by the read clock signal CK and RA
The M memory 221 is controlled according to the write signal WE.

FIG. 7 is a circuit diagram for explaining a specific configuration and operation of the Walsh function generation circuit 31. The function generating circuit 31 has four 4-bit dip switches (Dip Sw) 311 to 314. Further, three selectors 315, 316, 317 and one controller 318 are provided. The four dip switches 311 to 314 record desired combination patterns that satisfy the orthogonal relationship. This combination pattern is shown in FIG.
As shown in FIG.

The first dip switch 311 is set to the combination pattern 1, 1, 1, 1 in the first scan. That is, in the first scan, F ₁ , F ₂ , F ₃ , F
₄ are both logic level 1 pulses. The second dip switch 312 is set to the combination pattern 1, 1, 0, 0 in the second scan. That is, in the second scan, F ₁ = 1, F ₂ = 1, and F ₃ = 0
And F ₄ = 0. Similarly, the third dip switch 313 is set to the combination pattern 1, 0, 0, 1 for the third scan. That is, in the third scan, F ₁ = 1, F ₂ = 0, F ₃ = 0, and F ₄ = 1.

The fourth dip switch 314 is set to the combination pattern 1,0,1,0 for the fourth scan. In the fourth scan, F ₁ = 1, F ₂ = 0, F ₃ =
1, F ₄ = 0. The three selectors 315, 316,
Reference numeral 317 is controlled by the controller 318, and selects a predetermined dip switch for each scan.
The controller 318 controls the line line feed signal (Clock).
And switches and controls each selector in response to a scan start signal (Load). In the first scan, the first DIP switch 31 is supplied via selectors 315 and 317.
1 is selected and predetermined orthogonal signals F ₁ , F ₂ , F ₃ and F ₄ are output. These four orthogonal signals are supplied to a common driver as scanning signals via a level conversion circuit.

The level conversion circuit converts a 0/1 level orthogonal signal into a + Vr / 0 / -Vr level scanning signal. These quadrature signals are also transferred to the arithmetic unit. During the first scan, four orthogonal signals having a combination pattern of (1,1,1,1) are output in a set sequence. When shifting to the second scan, the selectors 315 and 317
The second DIP switch 312 is selected via
Four orthogonal functions F ₁ , F ₂ , F ₃ , F ₄ having predetermined patterns (1, 1, 0, 0) are output. Similarly,
In the third scan, the third DIP switch 313 is connected to the output side via the selectors 316 and 317. 4th
In the round scan, the fourth DIP switch 314 is connected to the output side via the selectors 316 and 317.

FIG. 8 is a circuit diagram for explaining the configuration and operation of the arithmetic unit. Here, the first arithmetic unit 34 is shown as an example. This operation unit 34 is composed of four exclusive OR circuits (XOR) 341 to 341
44. The first XOR 341 integrates the orthogonal function F ₁ assigned to the first row of the scan electrodes and the dot data I ₁₁ assigned to the intersection of the first row of the scan electrodes and the first column of the signal electrodes. Similarly, the second XOR 342 performs an integration process of the orthogonal function F ₂ assigned to the second row and the dot data I ₂₁ assigned to the second row / first column. The third XOR 343 performs an integration process of the orthogonal function F ₃ assigned to the third row and the dot data I ₃₁ assigned to the third row / first column. Finally, 4
The XOR 344 is the orthogonal function F ₄ assigned to the fourth row and the dot data I assigned to the fourth row / first column.
₄₁ integration processing is performed. A summing unit composed of a combination of four AND circuits 345 to 348 and five exclusive OR circuits 349 to 353 is connected to the subsequent stage of these four XORs. all were summing process, to create the data signal G ₁ to be assigned to the first column of the signal electrode. Similarly, the second arithmetic unit 35 shown in FIG. 5 creates a data signal G ₂ to be assigned to the second column.
As described above, there is a possibility that the data signal has five voltage levels, and in a digital format, it is given as 3-bit data as shown in FIG. The 3-bit data can be directly supplied to the segment driver.

Next, a description will be given of a horizontal shift multiple line simultaneous selection method. In the multiple line simultaneous selection method, an appropriate combination pattern can be used for the voltage waveform applied to the scanning electrode as long as the orthogonal relationship is maintained. However, in the combination pattern shown in FIG. 2, the case where all the simultaneously selected lines are scanned at + Vr or -Vr occurs once in a half cycle. For example, in the first scan of the first half cycle, +
Vr is applied, and in the first scan of the latter half cycle, all the simultaneously selected lines receive the applied voltage of -Vr. On the other hand, the voltage waveform applied to the signal electrode is calculated based on the above-described product-sum operation formula based on the dot data. Therefore, when the dot data represents an arbitrary display pattern, the bias voltage during the non-selection period is arbitrarily applied during a half cycle. However, if the display pattern is all ON or all OF
In the case of F, the bias voltage in the non-selection period is added intensively during the period in which all the simultaneously selected lines are scanned at + Vr or -Vr. For this reason, there is a possibility that the optical response will be uneven and the contrast will differ depending on the display pattern.

FIG. 9 shows a case where such a contrast difference due to the display pattern occurs. In the case of simultaneous selection of four lines, the voltage waveform actually applied to the liquid crystal by the display pattern and the optical response. Is schematically represented. (A) shows a case where an arbitrary pattern is displayed,
(B) is a case where all ON patterns are displayed. As is clear from the graph, in all the ON patterns, the bias voltage is concentrated during the first scanning period, causing a difference in contrast.

In order to cope with such a problem, a lateral shift method is effective. In the multiple line simultaneous selection method, a plurality of lines are simultaneously selected from the top of a normal screen and scanned downward. At this time, by shifting the phase of the scanning signal waveform applied to the scanning electrodes when a plurality of scanning electrodes are simultaneously selected from the phase of the scanning signal waveform selected immediately before, the liquid crystal is displayed during the non-selection period when all ON / OFF display is performed. Bias voltage is 1
It can be dispersed without concentrating on one frame scanning period in the / 2 cycle. This phase difference is such that the combination pattern of the waveforms applied to the scanning electrodes within one frame scanning period is shifted by at least one cycle. Therefore, even if the phase between a plurality of adjacent lines is not necessarily shifted, the phase may be shifted by one cycle every one selection by shifting one phase within one frame scanning period. The same applies to the case where the screen is selected from the bottom to the top or randomly and sequentially without scanning from the top to the bottom of the screen. In the multiple line selection method, when the combination pattern of orthogonal functions is fixed,
As described above, there is a difference in contrast depending on the display pattern, but by shifting the phase of the voltage waveform of the scanning signal, the optical response is made uniform, and the frame response at all ON / OFF can be suppressed and the contrast can be improved. It is.

FIG. 10 shows an example of a lateral shift drive waveform. When four lines are simultaneously selected, the voltage waveform of the scanning signal is set based on the Walsh function, and the phase is shifted by one every time the four lines are simultaneously selected.
In FIG. 10, F _i (t) represents a scanning signal waveform, and four lines are selected and the matrix panel is sequentially scanned from top to bottom. First, in the first scan, F ₁ , F
₂ , F ₃ , and F ₄ are represented by + Vr, + Vr, + Vr, + Vr, respectively.
Set to. Next _{F 5, F 6, F 7} , the F ₈ shifted first phase + Vr, + Vr, -Vr, sets -Vr. Similarly F ₉ thereafter applies the scanning signal obtained by shifting one by one phase to the scan electrodes. On the other hand, G ₁ (t) and G ₂ calculated according to the above-described product-sum operation formula are applied to the signal electrodes.
(T) and a data signal of G ₃ (t) are applied. G ₂ (t) at full ON and G ₃ (t) at full OFF shown in FIG.
Unlike this, the voltage applied to the signal electrode concentrated during the first frame scanning period is generated once every four times, and is evenly distributed over the entire １ ／ cycle.

Accordingly, the waveform applied to the liquid crystal layer when the display pattern is all ON is as shown in FIG. FIG. 9B
The unevenness of the optical response as shown in FIG.
The transmittance is the same as that of the arbitrary pattern shown in FIG. As described above, according to the lateral shift driving method, even in the case of all ON patterns, the light transmittance of the liquid crystal panel does not decrease in accordance with the frame scanning cycle, and a stable high level is maintained. Can be. In addition, the fluctuation of the transmittance is eliminated in all the ON patterns, and the optical response is the same as that in the arbitrary pattern. Therefore, there is no difference in contrast due to the display pattern, and the frame response can be suppressed.

FIG. 12 is a circuit diagram showing a specific configuration of a Walsh function generation circuit for realizing the horizontal shift combination pattern shown in FIG. Basically, it has the same structure as the Walsh function generating circuit shown in FIG. 7, and can be incorporated in the driving circuit of the liquid crystal display device shown in FIG. The difference is that the controller 318 has a horizontal shifter 319.
Is connected. The horizontal shifter 319 generates a clock signal (Cloc) generated in response to a scan start.
k) and a clear signal (Cle
ar) is supplied, and the phase shift of the combination pattern of the orthogonal signals is realized via the controller 318. Specifically, in the group sequential scanning, the first dip switch 31 is connected to the first group via the selectors 315 and 317.
1 is selected, and combination patterns 1, 1, 1, 1 are output. Therefore, F ₁ = 1, F ₂ = 1, F ₃ = 1, F ₄
= 1. For the next second set, selectors 315 and
The second DIP switch 312 is selected via 317, and the combination pattern 1, 1, 0, 0 is output. Therefore, as shown in FIG. 10, F ₅ = 1, F ₆ = 1, F ₇
= 0, F ₈ = 0.

Similarly, for the third set, the selector 31
The third dip switch 313 is selected via the switch 6, 317, and the combination pattern 1, 0, 0, 1 is selected. With respect to the fourth set, the fourth DIP switch 314 is selected via the selectors 316 and 317.
0, 1, 0 are output. Thereafter, the combination pattern is shifted for each group, and the first frame scanning is completed. 2
In the first frame scan, the start position shifts from the first DIP switch 311 to the second DIP switch 312 under the control of the horizontal shifter 319. Therefore, the first
For the set, the second DIP switch 312 is selected via the selectors 315 and 317, and the corresponding combination pattern 1, 1, 0, 0 is output. Therefore, FIG.
F ₁ = 1, F ₂ = 1, F ₃ = 0, F ₄ = 0 as shown in FIG.
Becomes Selectors 316 and 3 for the next second set
The third DIP switch 313 is selected via the switch 17 and the corresponding combination pattern 1, 0, 0, 1 is output. Therefore, F ₅ = 1, F ₆ = 0, F ₇ = 0, F ₈ =
It becomes 1.

Finally, the vertical shift driving of the combination pattern of the orthogonal functions will be described. In the case of using a scanning signal of a fixed combination pattern shown in FIG. 2, the scanning signal F ₁ applied to the first row scanning electrodes in accordance with a first Walsh function W1 shown in FIG. 3 1,1, It has an array pattern of 1,1. The polarity of this array pattern is inverted as it is after １ ／ cycle. Therefore, in the first half of the second cycle, an array pattern of ₁ , ₁ , ₁ , ₁ is similarly obtained, and F ₁
Is a signal of one cycle period. Second scanning signal F ₂
Has an array pattern according to the second Walsh function W2, and is 1,1,0,0. Therefore, F ₂ is a signal having a サ イ ク ル cycle period. Similarly, F ₃ is a signal having a half cycle period. However, F ₂ and the phase is shifted.
The fourth scanning signal F ₄ has an array pattern according to the fourth Walsh function W4, and 1,0,
It has an array pattern of 1,0. Therefore, F ₄ is a signal 1/4 cycle period. As described above, when the fixed combination pattern is repeatedly used for each cycle, F
₁ frequency is four times that of F _4, the frequency of the F ₂ and F ₃ is twice the F _4. The response characteristic of the liquid crystal has frequency dependence, and there is a possibility that a variation in frame response occurs between the individual scanning electrodes, which adversely affects display quality. This is particularly noticeable when the number of simultaneously selected lines is smaller than the total number of lines.

In the multiple line selection method, any waveform can be basically used for the scanning electrode line, but since the waveforms of the lines selected at the same time must be different waveforms,
An orthogonal function or the like is used. Therefore, as the number of lines selected at the same time increases, the difference in frequency between the first line and the last line selected at the same time by the waveform applied to the scanning electrode lines increases. The data signal applied to the signal electrode line is calculated by the product sum of the display pattern and the orthogonal function, and the waveform actually applied to the liquid crystal is a combination of the scanning electrode line and the signal electrode line. When the number n of simultaneously selected lines is smaller than √N, the voltage of the scanning electrode line becomes higher than the voltage of the signal electrode line, and the frequency of the synthesized waveform is dominated by the waveform of the scanning electrode line.
Conversely, when the number of simultaneously selected lines is greater than N, the voltage of the signal electrode line becomes higher than the scanning electrode line depending on the display pattern, and the frequency of the synthesized waveform is dominated by the waveform of the signal electrode. Further, when driving the liquid crystal, there is a frequency characteristic as shown in FIG. 18, and a difference in transmittance appears due to a difference in frequency. From the above, the number n of simultaneously selected lines is equal to the total number N of lines.
If it is relatively small as compared to the above, a difference in transmittance appears between the first line and the last line selected at the same time, and uneven stripes appear horizontally on the screen with the width of the number selected at the same time.

Therefore, in order to equalize the frequency of the scanning signal applied to each scanning electrode, the vertical shifting method shown in FIG. 13 is effective. As shown, in the first half of the first cycle, a combination pattern similar to that of FIG. 2 is obtained. That is, F ₁
Corresponds to W1, F ₂ corresponds to W2, F ₃
Corresponds to W3, F ₄ corresponds to W4.
In the second half of the first cycle, the polarity is simply inverted. Next, in the second cycle, the arrangement pattern is vertically shifted, and the combination pattern of W1, W2, W3, and W4 is W4, W1, W2, and W3. That, F ₁ is an array pattern of 1,0,1,0 accordance W4, F ₂ is an array pattern of 1,1,1,1 accordance W1, F ₃ is next 1,1,0,0 accordance W2, F
₄ becomes 1,0,0,1 according to W3.

Note that polarity inversion is performed in the latter half of the second cycle. In the subsequent third cycle, another vertical shift is performed, so the combination pattern is W3, W4, W1, W
It is represented by 2. Similarly, in the fourth cycle, the combination pattern is represented by W2, W3, W4, and W1. In the fifth cycle, the combination pattern W1,
It will return to W2, W3, W4. As is clear from the timing chart of FIG. 13, different frequency components are mixed in each of F ₁ , F ₂ , F ₃ , and F _{4 when} viewed through each cycle, and the frame response can be made uniform. It is needless to say that the orthogonal relationship is maintained regardless of the vertical shift in any cycle. or,
In this vertical shifting method, instead of shifting sequentially, replacement may be performed for each cycle. Further, the vertical shift may be performed not every cycle but every few cycles.

FIG. 14 is a view showing a Wal shift suitable for the above-described vertical shift.
FIG. 3 is a circuit diagram illustrating a configuration example of an sh function generation circuit. Basically, it has the same structure as the Walsh function generation circuit 31 shown in FIG. 7, and can be directly incorporated in the drive circuit shown in FIG. The difference is that a vertical shifter 310 is added at the subsequent stage of the selector 317. This vertical shifter 310 outputs a signal (C
ycycle), and performs the above-described vertical shift. In the first half of the first cycle, the four scanning signals output from the selector 317 are directly transferred to the corresponding scanning electrodes. In the latter half of the first cycle, the polarity is inverted. Next, in the second cycle, the four scanning signals output from the selector 317 are transferred to the scanning electrodes while being sequentially shifted one row at a time. After the polarity inversion is performed in the second half of the second cycle, the cyclic vertical shift is performed by one row in the same manner as in the first half of the third cycle.

FIG. 19 shows another example of the vertical shift drive waveform, and the shift direction is opposite to that of the example shown in FIG. In a case where four lines are simultaneously selected by the multiple line selection method, the Walsh function is used
The lower waveform pattern is set for each cycle. In FIG. 19, F _i (t) is a waveform to be applied to the scanning electrode, and four lines are selected and sequentially scanned from the top to the bottom of the liquid crystal panel. First, in the first cycle, the first line is set to (+ Vr, + Vr, + Vr, + Vr), and the second line is set to (+ Vr, + Vr, -Vr, -Vr).
The third line is set to (+ Vr, -Vr, -Vr, + Vr), and the fourth line is set to (+ Vr, -Vr, + Vr, -Vr). In the next cycle, the first cycle is 2
(+ Vr, + Vr, -Vr, -V
r), and simultaneously (+ Vr, -Vr,-
Vr, + Vr), and (+ Vr, -Vr, + Vr,
-Vr), the fourth (+ Vr, + Vr, + Vr, + V
r). Thereafter, the pattern is similarly shifted one by one every cycle and applied to the scanning electrodes. On the other hand, the signal electrodes G ₁ (t), G ₂ (t) and G ₃ obtained by multiply-accumulate by changing the pattern of F _i (t) every cycle.
Apply the data of (t). Therefore, a slight difference in transmittance is obtained every cycle, but no horizontal stripe pattern appears every four lines.

FIG. 20 shows the case where the Walsh function is used for the scan electrodes when the seven lines are simultaneously selected by the plural line selection method, and the first and seventh lines, the second and sixth lines, the third and fifth lines are performed every cycle. This is to set a waveform pattern in which the original is replaced. In FIG. 20, F _i (t) is a waveform applied to the scanning electrode, and seven lines are selected and the liquid crystal panel is sequentially scanned from top to bottom.

First, in the first cycle, (+ V
r, + Vr, + Vr, + Vr, -Vr, -Vr, -V
r, -Vr), and (+ Vr, + Vr, -Vr,-
Vr, -Vr, -Vr, + Vr, + Vr) and the third (+ Vr, + Vr, -Vr, -Vr, + Vr, + Vr,
-Vr, -Vr) and the fourth (+ Vr, -Vr, -V
r, + Vr, + Vr, -Vr, -Vr, + Vr) and the fifth (+ Vr, -Vr, -Vr, + Vr, -Vr, + Vr)
r, + Vr, -Vr) and the sixth line (+ Vr, -Vr, + Vr).
Vr, -Vr, -Vr, + Vr, -Vr, + Vr), 7
(+ Vr, -Vr, + Vr, -Vr, + Vr,-
Vr, + Vr, and -Vr).

In the next cycle, (+ Vr,-
Vr, + Vr, -Vr, + Vr, -Vr, + Vr, -V
r) The second (+ Vr, -Vr, + Vr, -Vr,-
Vr, + Vr, -Vr, + Vr) and the third (+ Vr,
-Vr, -Vr, + Vr, -Vr, + Vr, + Vr,-
Vr), and (+ Vr, -Vr, -Vr, + Vr,
+ Vr, -Vr, -Vr, + Vr) and the fifth (+ Vr
r, + Vr, -Vr, -Vr, + Vr, + Vr, -V
r, -Vr) and the sixth (+ Vr, + Vr, -Vr,-
Vr, -Vr, -Vr, + Vr, + Vr) and the seventh line (+ Vr, + Vr, + Vr, + Vr, -Vr, -Vr,
−Vr, −Vr). Next, the process returns to the first cycle and is repeatedly applied to the scan electrodes.

G ₁ obtained by the product-sum operation is applied to the signal electrode.
Data of (t), G ₂ (t), and G ₃ (t) are applied.
Although the horizontal stripes are not completely eliminated, the unevenness of the screen is practically no problem. Next, FIG. 21 is a schematic explanatory view showing a multiple line simultaneous driving method in which the number of scanning lines is optimized according to the present invention. The simple matrix panel 1 has a structure in which a liquid crystal layer is interposed between a scanning electrode group 4 in a row and a signal electrode group 5 in a column. The total number of lines of the signal electrode group 5 is generally represented by N. In the example shown, N is used for simplification.
= 16. On the other hand, the number of lines of the signal electrode group 5 is generally represented by M. In the illustrated example, M = 12 for simplification.
And For the liquid crystal layer, for example, STN liquid crystal can be used. The simple matrix panel 1 is driven via a common driver 2 connected to a scanning electrode group 4 and a segment driver 3 connected to a signal electrode group 5, and displays a desired image based on given dot data _Iij. Do. The dot data I _ij is assigned corresponding to the pixel defined at each intersection of the scanning electrode group 4 and the signal electrode group 5. i represents a row number and j represents a column number. In this example, the dot data I _ij indicates that the corresponding pixel is O
When N, a value of -1 is taken, and when OFF, a value of +1 is taken.

The set of orthogonal signals F _i is sequentially set to the common driver 2
, And selectively drives the scanning electrode group 4 in a set sequence for every predetermined number of lines. Meanwhile dot data I set the quadrature signal F _i set of product sum product sum signal G _j obtained by the calculation of the _ij is supplied to the segment driver 3 drives the signal electrodes 5 in synchronism with the set sequential scanning. In the present invention, the number of lines of the scanning electrodes that are simultaneously selected for each set is optimized to balance the breakdown voltage of the segment driver 3 and the breakdown voltage of the common driver 2. This optimization condition is generally expressed by approximately n = (square root of N), where N is the total number of lines of the scan electrode group 4 and n is the number of lines of the scan electrodes included in each group. For example, in the illustrated example, the total number of lines of the scanning electrode group 4 is 16, and its square root is 4. Therefore, the number of scanning electrode lines included in each set is set to four. That is, the 16 scanning electrodes are grouped every four, and the first group n1 and the second group n
2, a third set n3 and a fourth set n4 are obtained.

Next, the simultaneous driving of a plurality of lines will be described in detail with reference to the signal waveforms shown in FIG. F ₁
(T), F ₂ (t), F ₃ (t),..., F ₁₆ (t) indicate voltage waveforms of orthogonal signals applied to the corresponding scanning electrodes. Each orthogonal signal is set based on a Walsh function (FIG. 3) which is a complete orthonormal function at (0, 1). In this example, a set of orthogonal signals is set using the four orthogonal Walsh functions from the top in FIG. For example, with respect to the orthogonal signal given to the first set n1 of the scan electrode group, F ₁ (t) corresponds to the first Walsh function. Since the first Walsh function is at a high level in one cycle, F ₁ (t) is (1,
1, 1, 1).

In this example, the case of 1 is the voltage level of + Vr.
Level, and if 0, the voltage level is -Vr.
The period is set to 0 voltage level. Similarly, F_Two (T) is
The second Walsh function corresponds (1,1,0,
0). F_Three(T) is the third Wals
A pulse train corresponding to the h function (1, 0, 0, 1)
Become. F_Four (T) corresponds to the fourth Walsh function
It becomes a pulse train of (1, 0, 1, 0). Set sequential scanning
Is performed, first, the first set n1 is orthogonal to
Function F₁ (T) -F_Four The first pulse of (t) is applied.
Hereinafter, scanning is performed downward to select the second set n2. This
Orthogonal function F applied at the time_Five (T) -F ₈ (T) is the
F applied to one set n1₁ (T) -F_Four (T)
It has been shifted. This set sequential selection is performed by the fourth set n4.
The first scan is completed when all the steps are performed. And so on
The second scan, the third scan, and the fourth scan.
Driving corresponding to one cycle of the function is completed. Next cycle
Now, reverse the polarity of the orthogonal signal and perform similar group sequential scanning four times
The DC component is prevented from entering repeatedly.

On the other hand, in the timing chart of FIG. 21, G _j (t) indicates the voltage waveform of the product-sum signal applied to each signal electrode. The product-sum signal G _j (t) is represented by the following equation, and the set of dot data I _ij and the orthogonal signal F _i (t)
Is obtained by the product-sum operation of the set of.

[0071]

(Equation 13)

However, in this product-sum operation, since the voltage of the orthogonal signal in the non-selection period is at the 0 level, the sum is actually obtained only for the selected line. Therefore, in the case of simultaneous selection of four lines, the potential that the product-sum signal can take is five levels. That is, the potential level required for the product-sum signal as the data signal is (the number of simultaneously selected lines n + 1).

According to the multiple line simultaneous driving method,
The interval between the high-voltage pulses is reduced, and the same effect as the higher frequency can be obtained without reducing the pulse width. Further, the potential difference between the high voltage pulse and the bias voltage is reduced, the bias voltage can be increased without deteriorating the ON / OFF selection ratio, and the deterioration of the display contrast due to the frame response can be suppressed. Further, in the present invention, the number of lines of the scanning electrodes which are simultaneously selected for each set is optimized to balance the withstand voltage of the segment driver and the withstand voltage of the common driver.

For example, in the example shown in FIG.
The optimization is achieved by dividing the scanning electrodes into groups of four. As shown in the timing chart of FIG. 21, display of one screen can be performed by repeating group sequential scanning four times using four orthogonal signals that are orthogonal to each other. By performing the group sequential scanning four times, the selection pulses are dispersed, so that the voltage level of the orthogonal signal is kept low and the withstand voltage required for the common driver is not increased. Temporarily 2
When each group is grouped, one cycle is completed by repeating group sequential scanning twice. Therefore, the selection pulse is not dispersed and a large driving voltage is required. Conversely, if the groups are grouped every eight lines, the voltage can be further reduced as compared with the case where the groups are grouped every four lines. However, in this case, the voltage level of the product-sum signal applied to the segment driver increases. As described above, the number of voltage levels required for the product-sum signal is given by (the number of simultaneously selected lines n + 1). n =
In the case of 4, 5 levels are required, whereas n = 8
In this case, 9 levels are required, so that a higher voltage of the product-sum signal is inevitable, and the withstand voltage required for the segment driver also increases.

FIG. 22 is a graph showing the dependence of the driver breakdown voltage on the number n of simultaneously selected lines, which is based on actually measured data. In this actual measurement, a simple matrix type panel in which the total number of scanning electrode lines N = 240 is driven by the multiple line simultaneous selection method. At this time, the voltage levels of the quadrature signal and the product-sum signal when an arbitrary image is displayed by changing the number n of the simultaneously selected lines are actually measured, and the withstand voltage required for the segment driver and the common driver is obtained. . As is apparent from the graph, the withstand voltage of the common driver decreases with an increase in the number n of simultaneously selected lines, while the withstand voltage of the segment driver increases with an increase in the number n of simultaneously selected lines. In the vicinity of the region satisfying the relationship of n = (square root of N), both breakdown voltages are balanced with each other, and the value is about 15
V. When a common driver IC is used as the segment driver and the common driver, optimizing the number n of simultaneously selected lines can result in suppressing the driver breakdown voltage to the minimum level.

FIG. 23 shows the result of measuring the driver breakdown voltage when the total number of lines of the scanning electrode group is N = 400. As is clear from the graph, the common driver withstand voltage decreases with an increase in the number n of simultaneously selected lines, and the segment driver withstand voltage increases with an increase in the number n of simultaneously selected lines. Both breakdown voltages are balanced in a region near n = (square root of N). At this time, about 20 V is required as the driver withstand voltage.

Finally, a gray scale display by a multiple line selection method using voltage modulation will be described. To facilitate understanding of the present invention, first, the principle of gradation display will be described. Hereinafter, a case where L lines are simultaneously selected in the multiple line selection method will be described. FIG. 24 shows a conventional example of a waveform when three lines (L = 3) are simultaneously selected and driven. In FIG. 24, F ₁ (t) to F ₅ (t) indicate voltage waveforms applied to the scanning electrode lines, and G ₁ (t) to G ₃ (t) indicate voltage waveforms applied to the signal electrode lines. The waveform of the scanning electrode line is (0,
In 1), a Walsh function which is a perfect orthonormal function is used, and 0 is -Vr (V) and 1 is + Vr
(V), the non-selection period was set to 0 (V). L lines are selected from the top, and scanning is performed downward. One scan of the Walsh function is performed in several scans, and the polarity of the next cycle is inverted so that no DC component is input. As for the waveform of the signal electrode line, the total number of lines is N, and an arbitrary display pattern I _ij (i is the direction of the scanning electrode, j is the direction of the signal electrode) is displayed. If ≦ I _ij ≦ + 1, the data signal applied to each signal electrode line is basically determined so as to satisfy the following equation.

[0078]

[Equation 14]

[0079]

(Equation 15)

In the above equation, V _{(N + 1)} is the data of the virtual line provided in the _{(N + 1) th} line, and since the voltage of the scan electrode line in the non-selection period is 0 (V), it is actually the selected line. And the voltage G _j applied to the signal electrode line
For (t), only the first term may be calculated up to the (N / L-1) th time, and when the last L pieces are selected, the second term is added in addition to the first term according to the above equation. . The effects obtained by this multiple line simultaneous selection method are as follows.

(1) The interval between the high voltage pulses is reduced, and the same effect as that at the time of increasing the frequency can be obtained without reducing the pulse width. (2) The potential difference between the high voltage pulse and the bias voltage is reduced, the bias voltage can be increased without deteriorating the ON / OFF selection ratio, and deterioration of contrast due to frame response can be suppressed.

By the way, the virtual line (N
When calculating the data V of _{+1) (N + 1),} I ij is -1 to 1
Up to √N when I _ij is 0.
become. Therefore, as N increases, the value of V _{(N + 1)} also increases, and depending on the display pattern, the waveform of the signal electrode line does not apply or apply a highly pulsed voltage when the last plurality of lines are selected. Or The waveform actually applied to the liquid crystal is a composite U _ij (t) = F _i (t) -G _j (t) between the scanning electrode lines and the signal electrode lines, and FIG.
Of _{F 1 (t) -G 1 (} t), becomes as such as _{F 2 (t) -G 2 (} t). When the number L of simultaneously selected lines is smaller than √N lines, the voltage of the scanning electrode line becomes higher than the voltage of the signal electrode line, and the frequency of the synthesized waveform is dominated by the waveform of the scanning electrode line. Conversely, if the number of simultaneous lines L is greater than √N,
The voltage of the signal electrode line becomes higher than the scanning electrode line depending on the display pattern, and the frequency of the synthesized waveform is dominated by the waveform of the signal electrode. Further, when driving a liquid crystal, there is a frequency characteristic, and a difference in transmittance is caused by a difference in frequency. From the above, when the number L of simultaneously selected lines is relatively smaller than the total number N of lines, the waveform of the scanning electrode line is dominant, whereas in the conventional calculation as shown in the above equation, depending on the display pattern, When a highly pulsed voltage is applied to the signal electrode line, the frequency characteristic of the waveform applied to the liquid crystal changes, resulting in a difference in transmittance.

In view of the above, in the present invention, the product-sum operation method for gradation display is improved. FIG. 25 shows an example of the driving waveform of the present invention. 240 total lines
In this case, when the number of simultaneously selected lines is three, the Walsh function is used for the scanning electrodes. In FIG. 25, F _i (t) is a waveform applied to the scanning electrode, and three lines are selected and the liquid crystal panel is sequentially scanned from top to bottom. The first (+ Vr, + Vr, -Vr, -Vr) and the second (+
(Vr, -Vr, -Vr, + Vr), the third (+ Vr,
−Vr, + Vr, −Vr). (+ Vr, + Vr, + Vr, + Vr) is set in the virtual line.
On the other hand, the data signal G _j (t) applied to the signal electrode line is calculated by the following equation. The pattern of the non-selection period of the F ₄ (t) since the picture pattern as 0 to -th -1 / 2,3 to 1,2 knots in the first run scan lines as in the figure, -1, 0,
When calculated as 1/2, G ₁ (t) and G _{2 respectively}
(T) and G ₃ (t).

[0084]

(Equation 16)

[0085]

[Equation 17]

As shown in FIG. 24, in the conventional calculation method, a voltage as high as that of the scanning electrode line is applied to the signal electrode line G _j (t) depending on the display pattern. According to FIG. 25, a high voltage is not applied to the signal electrode line G _j (t) regardless of the display pattern. Therefore, the waveforms actually applied to the liquid crystal are represented by U ₁₁ (t), U ₂₂ (t), U
₃₃ (t), and the waveform becomes similar regardless of the display pattern.

FIG. 26 shows that when the total number of lines is 240 and the number of simultaneously selected lines is 7, the scanning electrodes
It uses an sh function. In FIG. 26, F _i
(T) is a waveform to be applied to the scanning electrodes, and seven lines are selected and scanned sequentially from the top to the bottom of the liquid crystal panel.

The first (+ Vr, + Vr, + Vr, + Vr
r, -Vr, -Vr, -Vr, -Vr) The second (+ Vr, + Vr, -Vr, -Vr, -Vr,
-Vr, + Vr, + Vr) The third (+ Vr, + Vr, -Vr, -Vr, + Vr,
+ Vr, -Vr, -Vr) The fourth line (+ Vr, -Vr, -Vr, + Vr, + Vr,
-Vr, -Vr, + Vr) The fifth (+ Vr, -Vr, -Vr, + Vr, -Vr,
+ Vr, + Vr, -Vr) The sixth (+ Vr, -Vr, + Vr, -Vr, -Vr,
+ Vr, -Vr, + Vr) The seventh line (+ Vr, -Vr, + Vr, -Vr, + Vr,
−Vr, + Vr, −Vr) The (+ Vr, + Vr, + Vr, + Vr, + Vr, +
(Vr, + Vr, + Vr, + Vr).

Data signal G _j applied to signal electrode line
(T) is calculated by the above equation. As shown in the figure, the display pattern is -1 for the first scanning line, -1/2 for the second scanning line, -４ for the third scanning line,-／ for the fourth scanning line, ０ for the fifth scanning line, １ ／ for the fifth scanning line, and ２ for the sixth scanning line. , The seventh line, and the pattern in the non-selection period after F ₄ (t) is calculated as −1, −２ ，, 0, G ₁ (t), G ₂ (t), G ₃ ( t). In this case, as in the case of selecting three pixels simultaneously, the waveform applied to each pixel is U
_ij (t), and the difference in waveform due to the display pattern can be minimized.

When a virtual line is provided every time a plurality of lines are selected, the effective value concentrated on the (N + 1) th line is calculated every L selections and dispersed over the entire waveform, so that the signal electrode lines have high pulse characteristics. The voltage may not be applied. In this case, the data of V _kj is calculated according to the following equation 18, and the data signal G _j (t) applied to the signal electrode line is calculated according to the following equation 19. That is, the voltage of the signal electrode line is determined by calculating and adding V _kj , which is virtual data, for each selection of a plurality of lines. At this time, V _kj becomes ΔL at the maximum value, and no high voltage is applied.

[0091]

(Equation 18)

[0092]

[Equation 19]

When gradation display is performed by the conventional multiple line selection method, there is a difference in transmittance depending on the display pattern. In the waveform applied to the liquid crystal, the frequency of the scanning electrode line becomes dominant irrespective of the display pattern, and the inside of the screen becomes uniform.

As described above, the voltage of the signal electrode line is determined by calculating and adding virtual data V _kj for each selection of a plurality of lines. The V _kj added at this time may be calculated not from the selected L data but from the L data selected once or several times as shown in the following Expression 20.

[0095]

(Equation 20)

By calculating the virtual data V _kj from the L data read from the memory at the point selected one or several times earlier, the operation time can be extended and simplified in the drive circuit. The voltage G _j applied to the signal electrode line
When calculating (t), the number of pixels of the panel is 240 × 32
Assuming 0 × 3 (RGB), when the frame frequency is 60 Hz, 72 ns per pixel. Therefore, if the signal voltage G _j (t) is directly supplied to the driver IC while being calculated without having a buffer memory for storing the calculation result, the calculation is completed in 288 ns in units of 4 pixels and 576 ns in units of 8 pixels. There is a need. Here, considering the reading from the data memory and the operation time, etc.
It is necessary to prepare a plurality of arithmetic circuits and calculate simultaneously. According to the method of calculating the virtual data V _kj according to the present invention, it is possible to use the data at the time of the previous selection and to perform the subtraction from L by squaring I _ij at the time of the previous selection. , And the square root can be calculated at the time of this selection, and time can be spared. Therefore, the number of pixels to be operated simultaneously can be reduced, and the driving circuit can be simplified.

[0097]

As described above, according to the present invention, orthogonal signal generating means is provided in a drive circuit of a simple matrix type liquid crystal panel to generate a plurality of orthogonal signals which are orthogonal to each other. Further, these are sequentially supplied to the common driver in an appropriate combination pattern, and the scanning electrode groups are selectively driven in a predetermined set order according to the combination pattern. Therefore, there is an effect that a plurality of lines of the simple matrix type liquid crystal panel can be simultaneously driven with a practical and efficient circuit configuration. An appropriate combination pattern of the orthogonal signals may be fixed and supplied repeatedly. However, depending on the case, a combination pattern shifted laterally for each sequential drive or a combination pattern shifted vertically for each cycle may be employed. The orthogonal signal generating means according to the present invention can create various combinations of patterns while maintaining the orthogonal relationship, and is extremely effective in suppressing the frame response and improving the contrast.

According to the present invention, a set of orthogonal signals is sequentially supplied to a common driver to selectively drive a scan electrode group for each predetermined number of lines, and a set of dot data and a set of orthogonal signals are selected. In a multiple-line simultaneous driving method in which the product-sum signal obtained by the product-sum operation is supplied to the segment driver and the signal electrode group is driven in synchronization with group sequential scanning, the number of scanning electrode lines simultaneously selected for each group is optimized. This has an effect that a balance between the withstand voltage of the segment driver and the withstand voltage of the common driver can be achieved.

Further, according to the lateral shift driving method of the present invention, even in the case of all ON patterns, the light transmittance of the liquid crystal cell does not decrease in accordance with the frame scanning cycle, and a stable high level is obtained. Can be maintained. In addition, the fluctuation of the transmittance seen in all the ON patterns as in the conventional example is eliminated, and the optical response at the time of an arbitrary pattern becomes the same. Therefore, there is no difference in contrast due to the display pattern, and the frame response is also reduced. Further, according to the vertical shift driving method according to the present invention, the horizontal stripes generated by the difference in the frequency of the waveform pattern applied to the scanning electrode lines can be eliminated, and a uniform screen can be obtained. In addition, according to the grayscale driving method of the present invention, the voltage of the scanning electrode line is dominant regardless of the display pattern, because the voltage applied to the liquid crystal does not have a high pulse property due to the display pattern. And the screen becomes uniform. At this time, the signal voltage G _j
The calculation of the virtual data V _kj required for the calculation of (t) can be started once or several times before the selection, and the reading from the data memory, the calculation, etc. are performed by dividing the selection into several selection times. The driving circuit can be simplified and downsized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart showing an embodiment of simultaneous driving of a plurality of lines.

FIG. 3 is a waveform diagram showing a Walsh function as an example of an orthogonal function.

FIG. 4 is a graph showing the dependence of the contrast ratio on the row selection time of the liquid crystal panel.

FIG. 5 is a circuit diagram showing a specific configuration example of the liquid crystal display device driving circuit shown in FIG.

6 is a circuit diagram showing a configuration example of a memory unit included in the drive circuit shown in FIG.

FIG. 7 shows Wal included in the drive circuit shown in FIG. 5;
FIG. 3 is a circuit diagram illustrating a configuration example of an sh function generation circuit.

8 is a circuit diagram showing a configuration example of an arithmetic unit included in the drive circuit shown in FIG. 5;

FIG. 9 is a graph showing the optical response of a simple matrix type liquid crystal panel.

FIG. 10 is a timing chart showing simultaneous driving of a plurality of lines based on a horizontal shift method.

FIG. 11 is a graph showing an optical response of a liquid crystal panel.

FIG. 12 is a circuit diagram showing a configuration example of a Walsh function generation circuit suitable for lateral shift driving.

FIG. 13 is a timing chart showing simultaneous driving of a plurality of lines based on a vertical shift method.

FIG. 14 is a circuit diagram showing a configuration example of a Walsh function generation circuit suitable for vertical shift driving.

FIG. 15 is a graph showing an optical response of a conventional simple matrix type liquid crystal display device.

FIG. 16 is a graph showing the optical response of a conventional simple matrix type liquid crystal display device.

FIG. 17 is a graph showing the optical response of a conventional simple matrix type liquid crystal display device.

FIG. 18 is a graph showing frequency dependence of a simple matrix type liquid crystal display device.

FIG. 19 is a timing chart showing another example of simultaneous driving of a plurality of lines based on the vertical shift method.

FIG. 20 is a timing chart showing another example of simultaneous driving of a plurality of lines based on the vertical shift method.

FIG. 21 is an explanatory diagram for optimizing the number of selected lines in a method for simultaneously driving a plurality of lines according to the present invention.

FIG. 22 is a graph showing a relationship between driver withstand voltage and the number of simultaneously selected lines.

FIG. 23 is a graph showing the relationship between the driver breakdown voltage and the number of simultaneously selected lines.

FIG. 24 is a timing chart showing a conventional gray scale display method using pulse voltage modulation.

FIG. 25 is a timing chart showing a gradation display method using pulse voltage modulation according to the present invention.

FIG. 26 is a timing chart showing another example of a gradation display method using pulse voltage modulation according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Matrix panel 2 Common driver 3 Segment driver 4 Scan electrode group 5 Signal electrode group 6 Frame memory 7 Quadrature signal generation means 8 Product sum operation means 9 Synchronization means 10 R / W address means 11 Drive control means 21 Serial / parallel conversion circuit 22 Memory unit 23 Memory unit 24 Memory unit 25 Memory unit 26 Write timing generation circuit 27 Write address generation circuit 28 Read address generation circuit 29 Address switching circuit 30 Read timing generation circuit 31 Walsh function generation circuit 32 Drive signal generation circuit 33 Level conversion circuit 34 Computing Unit 35 Computing Unit 36 Computing Unit 37 Computing Unit 38 Computing Unit 39 Computing Unit 40 Computing Unit 41 Computing Unit 42 8/4 conversion circuit

──────────────────────────────────────────────────の Continued on the front page (31) Priority claim number Japanese Patent Application No. 5-64425 (32) Priority date March 23, 1993 (1993.3.23) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-157449 (32) Priority date June 28, 1993 (1993.28.28) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-157450 (32) Priority date June 28, 1993 (June 28, 1993) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-157451 ( 32) Priority Date June 28, 1993 (June 28, 1993) (33) Priority Country Japan (JP) (72) Inventor Shuhei Yamamoto 6-31-1, Kameido, Koto-ku, Tokyo Seiko Electronics (56) References JP-A-6-27904 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 545 G02F 1/133 575 G09G 3/36

Claims (5)

(57) [Claims] A matrix type liquid crystal panel having a liquid crystal layer interposed between a row-shaped scanning electrode group and a column-shaped signal electrode group using a common driver and a segment driver based on dot data. In the case of driving, a set of orthogonal signals is sequentially supplied to a common driver to selectively drive a scan electrode group for each predetermined number of lines, and a sum of dot data sets and orthogonal signal sets is obtained. A method for driving a liquid crystal panel in which a sum-of-products signal is supplied to a segment driver to drive signal electrode groups in synchronization with group sequential scanning, wherein the number of scanning electrode lines simultaneously selected for each group is optimized and A method of driving a liquid crystal panel, wherein a balance between a withstand voltage and a withstand voltage of a common driver is balanced. 2. Assuming that the total number of lines of a scanning electrode group is N,
2. The liquid crystal panel according to claim 1, wherein the number n of lines of the scanning electrodes included in each set is set near a square root of N.
Method of driving a. 3. A method of driving a liquid crystal panel in which liquid crystal is interposed between a large number (N) of scanning electrodes and a large number of signal electrodes, wherein a plurality of (L) scanning electrodes are grouped together. And simultaneously selecting, supplying a scanning signal to each scanning electrode of the scanning electrode group, supplying a data signal to the signal electrode in synchronization with the scanning signal, and sequentially scanning the scanning electrode group to perform frame scanning. The scan signal applied to each scan electrode when the scan electrode group is selected has a plurality of voltage levels, and each scan signal of each scan electrode to which one of the plurality of voltage levels is assigned, The scanning electrode group forms an orthogonal combination pattern, and the combination pattern is repeated for each of a plurality of frame scans. A scanning signal Fi (t) and display data I are applied to the signal electrode.
Data signal voltage Gj calculated from ij by the following equation
(T) is applied, Here, V (L + 1) j is data of a virtual line added for every L lines, and is calculated by the following equation. A method for driving a liquid crystal panel, characterized in that data of a virtual line to be added to the (N + 1) th line is added by equally dividing the data of the virtual line each time L scanning electrodes are selected. 4. A method for driving a liquid crystal panel in which liquid crystal is interposed between a large number (N) of scanning electrodes and a large number of signal electrodes, wherein a plurality of (L) scanning electrodes are collectively arranged. And simultaneously selecting, supplying a scanning signal to each scanning electrode of the scanning electrode group, supplying a data signal to the signal electrode in synchronization with the scanning signal, and sequentially scanning the scanning electrode group to perform frame scanning. The scan signal applied to each scan electrode when the scan electrode group is selected has a plurality of voltage levels, and each scan signal of each scan electrode to which one of the plurality of voltage levels is assigned, The scanning electrode group forms an orthogonal combination pattern, and the combination pattern is repeated for each of a plurality of frame scans, and the signal electrode includes a scanning signal Fi (t) and a display data I.
Data signal voltage Gj calculated from ij by the following equation
(T) is applied, Here, Vkj is data of a virtual line added for every L lines, and is calculated by the following equation. A method for driving a liquid crystal panel, characterized in that data of a virtual line to be added to the (L + 1) th line is calculated and added from data of L lines each time L scanning electrodes are selected. 5. A method of driving a liquid crystal panel in which liquid crystal is interposed between a large number (N) of scanning electrodes and a large number of signal electrodes, wherein a plurality of (L) scanning electrodes are collectively arranged. And simultaneously selecting, supplying a scanning signal to each scanning electrode of the scanning electrode group, supplying a data signal to the signal electrode in synchronization with the scanning signal, and sequentially scanning the scanning electrode group to perform frame scanning. The scan signal applied to each scan electrode when the scan electrode group is selected has a plurality of voltage levels, and each scan signal of each scan electrode to which one of the plurality of voltage levels is assigned, The scanning electrode group forms an orthogonal combination pattern, and the combination pattern is repeated for each of a plurality of frame scans, and the signal electrode is provided with a scanning signal Fi (t) and display data I.
Data signal voltage Gj calculated from ij by the following equation
(T) is applied, Here, Vkj is virtual line data added for each L lines, and is calculated by the following equation. A method of driving a liquid crystal panel, wherein data of a virtual line to be added to the (L + 1) -th line is calculated and added from data of the L lines selected A times before each time the L scanning electrodes are selected. , A is a single digit integer).