JP3178930B2 - Double integral type A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double integration type A / D converter (analog / digital converter) for converting an analog signal into a digital signal, and in particular, a technique for compensating an offset voltage of an amplifier constituting a circuit. And the method of initializing the integrating circuit constituting the circuit.

[0002]

2. Description of the Related Art There are various types of A / D converters for converting an analog signal into a digital signal, such as a parallel type, an integral type, a successive approximation type, and a tracking comparison type. Among them, the double integral type A / D converter is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-62217.
As described in Japanese Unexamined Patent Application Publication No. 2000-163, a circuit that integrates a reference voltage after integrating an input voltage that is a voltage to be measured, and converts an analog signal into a digital signal based on a ratio of an integration time of the two voltages. . Such a double-integration type A / D converter has a feature that high accuracy and high resolution can be obtained relatively easily and the input voltage is integrated, so that it is resistant to input periodic noise. In this type of double integration type A / D converter, a double integration type A / D converter having an offset compensation function for compensating for an offset voltage of an amplifier constituting a circuit has been proposed.

FIG. 2 is a block diagram showing a configuration example of a conventional double integrating A / D converter with an offset compensation function. This double integration type A / D converter includes an analog switch 1 for setting a node N3 to a ground GND (0 V), an analog switch 2 for inputting an input voltage Vin as a measured voltage to a node N3, and GND. Input voltage Vi
It has an analog switch 3 for inputting a reference voltage Vref having a polarity opposite to that of n to the node N3. A node N3 commonly connected to the analog switches 1, 2, 3 is connected to a positive input terminal of an input buffer amplifier 4 having an offset voltage _Voff1, and an output terminal of the input buffer amplifier 4 is connected to a negative input terminal by feedback. ing. Input buffer amplifier 4
Is connected to an integration circuit 10 for integrating the output. The integrating circuit 10 includes an integrating resistor (resistor)
11, integrating capacitor (second capacitance element) 12,
Offset compensation first capacitor (first capacitance
Element 13 and an integrating amplifier 14 having an offset voltage V _off2 . One end of the integrating resistor 11 (first
Node) is connected to the output terminal of the input buffer amplifier 4, the other end is connected to the node (second node) N11. The node N11 is an output node (fourth node) of the integrating amplifier 14 via the integrating capacitor 12.
It is connected to a node (third node) N13 via a first capacitor 13 while being connected to N14.
The node N13 is connected to the negative input terminal of the integrating amplifier 14, and the positive input terminal is connected to GND. The node N13 is connected to the negative input terminal of the comparator 20 having the offset voltage _Voff3.
4 is connected to the positive input terminal of the comparator 20. An output side node (sixth node) N20 of the comparator 20 is an analog switch (second node) .
The second switch 21 is connected to the negative input terminal of the comparator 20 in a feedback manner. The output node N20 of the comparator 20 is connected to the control circuit 30.
The control circuit 30 has a function of outputting a control signal S30a for controlling ON / OFF of the analog switches 1, 2, 3, and 21, and a function of outputting a control signal S30b for controlling the operation of the counter 40. The counter 40 is a circuit that counts the clock CLK based on the control signal S30b, and the value of the counter 40 can be temporarily stored in the register 50.

FIG. 3 is a waveform diagram for explaining the operation of FIG. 2. Referring to FIG. 3, the double integration type A / D of FIG.
The operation of the converter will be described. The A / D conversion sequence includes an auto-zero stage Tr during a reset period, a first integration stage Ts during a Vin integration period, and a second integration stage Tm during a Vref integration period. The auto zero stage Tr is a reset period (that is, an initialization period) of the double integration type A / D converter, and at this time, the analog switches 1 and 21 are turned on. Input buffer amplifier 4, the integrating amplifier 14, and since the offset voltage of the comparator 20 is V _off1, V _off2, V _off3 respectively, each node in the auto zero stage Tr N11, N13, N1
4 voltage, the node N11 is -V _off1, node N13 is -V _off2, and the node N14 becomes -V _off2 + V _off3. When the potentials of the nodes N11, N13, N14 are stabilized, the auto-zero stage Tr ends, and the process shifts to the first integration stage Ts.

In the first integration stage Ts, the analog switches 1 and 21 are turned off and the analog switch 2 is turned on.
The input voltage Vin is taken into the input buffer amplifier 4,
The output is integrated by the integration circuit 10 for a certain period of time. Counter 40, the integration starts at the same time, starts counting up the clock CLK from 0 based on the control signal S30b from the control circuit 30. Node N during integration by integration circuit 10
The slope of the waveform 14 increases in proportion to the absolute value of the value of the input voltage Vin. After a lapse of a certain time, the first integration stage Ts ends, the process proceeds to the second integration stage Tm, and the count value n1 of the counter 40 at this time is temporarily stored in the register 50. In the second integration stage Tm, the analog switch 2 is turned off and the analog switch 3
Is turned on, the reference voltage Vref is taken into the input buffer amplifier 4, and the output is integrated by the integrating circuit 10. The counter 40 starts counting up the clock CLK again from 0. The input voltage Vin and the reference voltage Vref are
Since the polarity is opposite to GND, the potential of the node N14 changes in a direction opposite to that of the first integration stage Ts. The comparator 20 compares the voltage of the node N14 (the output terminal voltage of the integrating amplifier 14 ) with the voltage of the node N13 (the input terminal voltage). When the voltage of the node N14 exceeds the voltage of the node N13, The output of the comparator 20 is inverted. When detecting the inversion of the output of the comparator 20, the control circuit 30 uses the control signal S30b to output the counter 4
0 is stopped, and the second integration stage Tm ends.
The gradient of the voltage waveform at the node N14 in the second integration stage Tm is always constant because the reference voltage Vref is constant. Therefore, if the count value of the counter 40 at the end of the second integration stage Tm is n2, Vin / V
ref = n2 / n1. Since the count value n1 and the value of the reference voltage Vref are known, the count values n1 and n2
The input voltage Vin can be obtained from the ratio of A / D
Conversion is established. In the A / D conversion sequence as described above, in the auto-zero stage Tr, the potential of the node N11 is charged to the level of _-Voff1 , and this potential is also held in the first integration stage Ts and the second integration stage Tm. Since the output of the input buffer amplifier 4 has a value shifted by the voltage V _{off1 from the} positive input, the input voltage Vin or the reference voltage Vref is eventually applied to the integrating resistor 11.
The error _itself is added, and the error due to the offset voltage V _off1 is canceled. In this autozero stage Tr, the potential of the node N13, since is charged to -V _off2, the potential of the node N14 is charged to the level of -V _off2 + V _off3, the integration circuit 10 starts integration from this potential. The output of the comparator 20 is such that the level of the node N14 is -V
reversed in the place it became _off2 + V _off3, since the end of the integration, where the offset voltage V _off2 and V _off3 also be canceled. Thus, the offset voltages V _off1 , V
_off2, all V _off3 is canceled, it is possible to perform error-free A / D conversion by the offset.

[0006]

However, in the A / D converter having the above configuration, the integrating amplifier 14 and the comparator 20 are coupled in two stages in the auto-zero stage Tr. Since the negative feedback is applied to the integrating amplifier 14, there is a high risk of causing oscillation due to the phase shift of the integrating amplifier 14 and the comparator 20, and phase compensation is difficult. That is, there is a problem that it is difficult to keep the phase delay within 180 ° to make the total gain 0 dB. The present invention provides a dual-integration type A / D converter with an offset compensation function which solves the problem of the prior art that the phase compensation for preventing oscillation of the integrating amplifier 14 and the comparator 20 is difficult. To provide.

[0007]

To solve the previous SL problems SUMMARY OF THE INVENTION In the first aspect of the present invention, the double integral type A / D
The converter has an integrating circuit. The integration circuit
Comprises: a first node for inputting an input voltage and a reference voltage;
One end is connected to the first node and the other end is a second node
One end is connected to the second node.
And the other end is a first capacitance element connected to the third node.
And a negative input terminal connected to the third node and ground.
A positive input terminal to which a potential is supplied and a fourth node
An integrating amplifier having an output terminal connected to the second terminal;
And the other end is connected to the fourth node.
A second capacitance element, the third node and the fourth
A first switch for electrically connecting or disconnecting the
And a switch. Further, in the first invention,
Are connected to a positive input terminal connected to the fourth node and a fifth input terminal.
Negative input terminal connected to the node and connected to the sixth node
A comparator having an output terminal connected to the
5 and the other end is supplied with the ground potential.
A third capacitance element, the fifth node and the sixth
A second switch for electrically connecting or disconnecting the node
Switch and a counter connected to the sixth node.
Have. In the second invention, the double integral type of the first invention
In the A / D converter, the first node and the second node
A third switch for electrically connecting or disconnecting a node
It has a switch.

[0008]

According to the first aspect of the present invention, since the double integrating A / D converter is configured as described above, for example, during the reset period before the start of the integration, the input and output terminals of the integrating amplifier are connected.
While being shorted by the first switch, the input of the comparator, the output terminals are short-circuited by the second switch, no negative feedback across the two stages of the integrating amplifier and the comparator, the integrating amplifier and a comparator, each unique , The offset voltage is charged in the first and third capacitance elements for offset compensation, respectively. This facilitates phase compensation for preventing oscillation due to negative feedback. According to the second invention, the third switch connected in parallel with the integrating resistor, for example, turned on when initializing the integrating circuit, the resistor for integrating its initialization time is causing according It has a function of reducing a time constant composed of a capacitor , a second capacitance element for integration, and a first capacitance element for offset compensation. As a result, the integration circuit can be initialized at high speed, and the A / D conversion time can be reduced. Therefore, the above problem can be solved.

[0009]

EXAMPLES First Embodiment FIG. 1, first a block diagram of an offset compensation function double integral type A / D converter of an embodiment, conventional elements in Figure 2 of the present invention Common elements are denoted by common reference numerals. In this double integration type A / D converter, an integration circuit 10A having a configuration different from that of the conventional integration circuit 10 is provided .
5) is different from the conventional circuit in that a second capacitor (third capacitance element) 22 for offset compensation is added between N22 and GND, and the other circuits are the same as the conventional circuit. Configuration. In the conventional integrating circuit 10, the negative input terminal of the integrating amplifier 14 is connected to the negative input terminal of the comparator 20. On the other hand, in the integrating circuit 10A of the present embodiment, the negative input terminal side
The node (third node) N13 is not the negative input terminal of the comparator 20, but the output control signal S30a of the control circuit 30.
Analog switch (on the first switch)
H) The output terminal side of the integrating amplifier 14
(A fourth node) N14 , and the other configuration is the same as the conventional one.

The operation of the double integrating A / D converter shown in FIG.
The analog switch 15 is turned on in the auto zero stage Tr by the output control signal S30a of the control circuit 30, and the first
This is the same as the conventional FIG. 3 except that it is turned off in the integration stage Ts and the second integration stage Tm. However, by adding the second capacitor 22, the input buffer amplifier 4, the manner of holding the offset voltage V _off1, V _off2, V _off3 of the integrating amplifier 14, and the comparator 20 is different from the conventional. FIG. 4 is a waveform diagram for explaining the operation of FIG. The A / D converter sequence is, as in the conventional case, the auto-zero stage Tr, V
the first integration stage Ts during the in integration period, and Vre
It consists of a second integration stage Tm during the f integration period. In the auto zero stage Tr, the analog switches 1 and 21 are turned on based on the control signal S30a during the initialization period of the double integration type A / D converter. When the analog switch 1 is turned on, the node N3 goes to the GND level and the node N3
11 is charged to the level of -V _off1 , and this potential is charged by the capacitor 13 to the first integration stage Ts and the second integration stage Ts.
It is also held in the integration stage Tm. Since the output of the input buffer amplifier 4 has a value shifted by V _{off1 from} its positive input, the voltage applied to the integrating resistor 11 is consequently the input voltage Vin,
In the second integration stage Tm, when the analog switch 3 is turned on, the reference voltage becomes the reference voltage Vref itself, and the error _caused by the set voltage V _off1 of the input buffer amplifier 4 is canceled. In the auto zero stage Tr, the nodes N13 and N1
4 is charged to the -V _off2 level. Node N13
Of the first integration stage T by the capacitor 13.
s and the second integration stage Tm. In the first integration stage Ts, the analog switches 1, 15,
21 is turned off, the analog switch 2 is turned on, the input voltage Vin is taken into the input buffer amplifier 4, and integration is started by the integration circuit 10A. When the integration starts, the integration output on the output side node N14 of the integration amplifier 14 becomes -V
Start from _off2 level. Auto Zero Stage T
In r, the potential of the node N22 is charged to -V _off2 -V _off3 level, this potential is also held at the first integrator stage Ts and second integration stage Tm by the capacitor 22. In the second integration stage Tm, the analog switch 2 is turned off, the analog switch 3 is turned on, and the reference voltage V
ref is taken into the input buffer amplifier 4, and its output is integrated by the integration circuit 10A. Comparator 20
Is that the potential of the integration output on the node N14 (the output terminal voltage of the integrating amplifier 14) is -V _off2 (input terminal voltage).
, The offset voltage V _{off3 of the} comparator 20 is canceled here. Consequently, the potential of the integrated output on the node N14, to end at -V _off2 starting from -V _off2, wherein the offset voltage V _off2 of integrating amplifier 14 is also canceled. Thus, the input buffer amplifier 4 and the integrating amplifier 1
4, and the offset voltages V _off1 , V of the comparator 20
_off2, all V _off3 is canceled, it is possible to perform fewer A / D conversion of an error.

This embodiment has the following advantages. In this embodiment, there is no negative feedback over two stages of the integrating amplifier 14 and the comparator 20 as shown in FIG. the first offset voltage V _off2, V _off3 for offset compensation, and to charge each of the second capacitor 13 and 22. Therefore, phase compensation for preventing oscillation by negative feedback is easy, and the auto-zero stage T
The circuit at r can be operated stably, and
A / D conversion without errors due to the offset of the amplifiers (4, 14, 20) constituting the circuit can be performed. In the double integration type A / D conversion of this embodiment, the first integration stage T
Since the potential of the integrated output on the node N14 at the end of s is basically proportional to the input voltage Vin, it is necessary to initialize the value of the integrated output on the node N14 in the auto-zero stage Tr before the start of the integration. . However, as the values of the integrating resistor 11, the integrating capacitor 12, and the offset compensating first capacitor 13 increase, the potential of the integrated output on the node N14 is initialized to the level of V _off1 during the auto-zero stage Tr. It takes time, A
It is difficult to shorten the / D conversion time. Therefore, this problem is solved in the following second embodiment.

Second Embodiment FIG. 5 is a block diagram showing the configuration of a double integration type A / D converter having an offset compensation function according to a second embodiment of the present invention, and shows the first embodiment. Elements common to the elements in 1 are denoted by common reference numerals. This double integration type A / D converter includes an integration circuit 10B having a configuration different from that of the integration circuit 10A of the first embodiment. The integrating circuit 10B
In parallel with the integrating resistor 11 in the integrating circuit 10A of the embodiment, the output signal is turned on by the output control signal S30a of the control circuit 30.
Analog switch (third switch) that turns off 16
The configuration is the same as that of the first embodiment except that is connected.

Next, the operation will be described. The analog switch 16 added to the integration circuit 10B is turned on by the auto-zero stage Tr in FIG. 4, and both ends of the integration resistor 11 are short-circuited. Then, the potential of the node N11 between the integrating resistor 11 and the integrating capacitor 12 is changed to the input buffer amplifier 4
Is charged through the analog switch 16 and the integrating resistor 11, and finally _{reaches the} same level as the output voltage (V _off1 ) of the input buffer amplifier 4. The time required for the potential of the node N11 to be charged until it sufficiently approaches V _off1 in terms of A / D conversion accuracy is proportional to the time constant k in the following equation.

[0014]

(Equation 1) If R11≫R16, the potential of the node N11 can be charged to the V _off1 level in a very short time as compared with the conventional circuit without the analog switch 16. As described above, in the present embodiment, the node N11 is charged through the analog switch 16 having an on-resistance R16 much lower than the integrating resistor 11 in the auto-zero stage Tr. Even if it is set to be short, the node N11 is sufficiently set to V _off1.
A / D conversion time can be reduced. The present invention is not limited to the above embodiment. For example, another element may be added to the A / D converter shown in FIG. 1 or FIG. , 15, 16, and 21 can be variously modified, for example, by using other switches.

[0015]

As described above in detail, according to the first aspect, for example, before the start of integration, the first and second switches are switched.
Switch is turned on, and the first electrostatic capacitor for offset compensation is turned on.
The capacitive element stored offset voltage of the integrating amplifier, so the third capacitance device for offset compensation, and to store the offset voltage of the comparator relative to the output of the integrating amplifier, the integrating amplifier And comparator
No negative feedback is provided over the two stages, phase compensation for preventing oscillation by such negative feedback is easy, and the circuit can be operated stably during the reset period before the start of integration. it is possible to perform error-free a / D conversion by the configuration to that integrals for amplifier及 beauty comparator offset. According to the second invention, the third resistor is provided in the integrating resistor .
Since the switch are connected in parallel, for example, if the on state of the third switch when initializing the integrating circuit, the connection point of the second capacitance element for integration and the integrating resistor No.
2 nodes, is rapidly charged via the third switch. Therefore, setting the initialization time itself of the integrator circuit short, a second electrostatic for sufficiently integrating the integrator resistor
The second node at the connection point with the capacitor can be charged to a predetermined level, and the A / D conversion time can be reduced.

[Brief description of the drawings]

FIG. 1 shows a double integral type A / D showing a first embodiment of the present invention.
It is a structural block of a converter.

FIG. 2 is a configuration block diagram of a conventional double integration type A / D converter.

FIG. 3 is a waveform chart for explaining the operation of FIG. 2;

FIG. 4 is a waveform chart for explaining the operation of FIG. 1;

FIG. 5 shows a double integral type A / D showing a second embodiment of the present invention.
It is a structural block of a converter.

[Explanation of symbols]

1, 2, 3, 15, 16, 21 Analog switch 4 Input buffer amplifier 10A, 10B Integrator circuit 11 Integrating resistor 12 Integrating capacitor 13 First capacitor for offset compensation 14 Integrating amplifier 20 Comparator 22 For offset compensation Second capacitor 30 Control circuit 40 Counter 50 Register Vin Input voltage Vref Reference voltage

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (2)

(57) [Claims] A first input device for inputting an input voltage and a reference voltage;
One end is connected to the first node and the other end is connected to the first node.
A resistor connected to the second node and one end of the resistor connected to the second node.
And the other end is connected to a third node.
A capacitive element and a negative input connected to the third node
Terminal and the positive input terminal to which the ground potential is supplied and the fourth node
An integrating amplifier having an output terminal connected to
Is connected to the second node and the other end is the fourth node
A second capacitance element connected to the third node;
And the fourth node are electrically connected or disconnected.
An integration circuit including a first switch, a positive input terminal connected to the fourth node, and a fifth node.
Connected to the negative input terminal connected to the node and the sixth node
A comparator having an output terminal, one end connected to the fifth node, and the other end connected to the ground potential.
Is electrically connected to the third capacitance element to which the voltage is supplied and the fifth node and the sixth node.
Or a second switch to be disconnected and a counter connected to the sixth node.
A double integral type A / D converter. 2. The method according to claim 1, wherein said first node and said second node are connected to each other.
A third switch that electrically connects or disconnects
The double integral type A / according to claim 1, wherein
D converter.