JP3160792B2 - Power converter - Google Patents
Power converterInfo
- Publication number
- JP3160792B2 JP3160792B2 JP27607593A JP27607593A JP3160792B2 JP 3160792 B2 JP3160792 B2 JP 3160792B2 JP 27607593 A JP27607593 A JP 27607593A JP 27607593 A JP27607593 A JP 27607593A JP 3160792 B2 JP3160792 B2 JP 3160792B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor switches
- state
- semiconductor
- power supply
- series connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電源電圧を分割するコ
ンデンサーと４組の直列接続された半導体スイッチと中
性点電位をクランプするダイオードから構成され、３レ
ベルの電位を出力する電力変換装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter for outputting a three-level potential, comprising a capacitor for dividing a power supply voltage, four sets of semiconductor switches connected in series, and a diode for clamping a neutral point potential. About.
【０００２】[0002]
【従来の技術】電気車用の交流電動機を制御するＰＷＭ
インバータのスイッチング素子には、ゲートターンオフ
サイリスタ（以下、ＧＴＯと記す）を使用するのが一般
的である。しかし、近年では、高周波動作が可能な絶縁
ゲートバイポーラトランジスタ（以下、ＩＧＢＴと記
す）が実用可能となってきた。ところで、これらのスイ
ッチング素子からなるインバータ回路方式として、電源
電圧を分割するように直列に接続したコンデンサーと４
組の直列された半導体スイッチと、コンデンサーの中点
と半導体スイッチの１と２の間及び３と４の間をダイオ
ードで接続し、中性点電位にクランプする回路方式が知
られている。この回路方式の特徴として、４組の半導体
スイッチのオン・オフの組合せによって、電源電位、中
点電位、接地電位の３段階の出力をとり得ること、ま
た、電源電位をコンデンサーで分割するため、１組の半
導体スイッチには電源電位の１／２が印加されることが
挙げられる。この方式のインバータを３レベルインバー
タと呼ぶ。３レベルインバータは、上述したように４組
の直列された半導体スイッチから構成されるので、これ
ら半導体スイッチの直列接続には、個々の素子のオン・
オフ特性を合わせる必要がある。しかし、この特性合わ
せは困難を要する。また、この過度動作時の特性合わせ
の外に、定常状態の素子にかかる電圧分担が均等になる
ように配慮する必要がある。すなわち、半導体素子のオ
フ状態における洩れ電流のバラツキによって、単に半導
体素子を直列に接続しただけでは電圧分担が均等な分布
とならない。洩れ電流の大きな素子（等価インピーダン
スが小さい）の電圧が洩れ電流の小さな素子より小さく
なる。そこで、従来は、図４に示すように、半導体の等
価インピーダンスより小さくかつ抵抗値が等しい抵抗を
並列に接続することにより、半導体素子にかかる電圧を
均等にすることが一般的であった。図４において、１５
Ａ、１５Ｂ、１５Ｃ、１５Ｄは半導体素子、１６Ａ、１
６Ｂ、１６Ｃ、１６Ｄは並列抵抗、１５は電源を示す。
この例として、特開平１−１５２９７１号公報がある。
なお、半導体スイッチの直列接続時の均圧化技術につい
ては、刊行物「大学講義 パワーエレクトロニクス」宮
入庄太著、丸善株式会社出版の頁３８、３９等に見られ
る。2. Description of the Related Art PWM for controlling an AC motor for an electric vehicle
In general, a gate turn-off thyristor (hereinafter, referred to as GTO) is used as a switching element of an inverter. However, in recent years, an insulated gate bipolar transistor (hereinafter, referred to as IGBT) capable of high-frequency operation has become practical. By the way, as an inverter circuit system composed of these switching elements, a capacitor connected in series so as to divide a power supply voltage and a
There is known a circuit in which a series of solid-state switches are connected, and a diode is connected between the middle point of the capacitor and the solid-state switches 1 and 2 and between the solid-state switches 3 and 4 to be clamped to a neutral potential. As a feature of this circuit system, the power supply potential, the midpoint potential, and the ground potential can be obtained in three stages by the on / off combination of the four semiconductor switches, and the power supply potential is divided by a capacitor. One half of the power supply potential is applied to one set of semiconductor switches. This type of inverter is called a three-level inverter. Since the three-level inverter is composed of four sets of serially connected semiconductor switches as described above, the series connection of these semiconductor switches includes ON / OFF of individual elements.
It is necessary to match off characteristics. However, this characteristic matching is difficult. In addition to the characteristic adjustment at the time of the transient operation, it is necessary to consider that the voltage distribution applied to the element in the steady state becomes equal. That is, due to the variation of the leakage current in the off state of the semiconductor element, even if the semiconductor elements are simply connected in series, the voltage distribution is not evenly distributed. The voltage of an element having a large leakage current (small equivalent impedance) is smaller than that of an element having a small leakage current. Therefore, conventionally, as shown in FIG. 4, it is general to equalize the voltage applied to the semiconductor element by connecting in parallel a resistor having a smaller resistance than the equivalent impedance of the semiconductor and having the same resistance value. In FIG.
A, 15B, 15C, 15D are semiconductor elements, 16A, 1
6B, 16C and 16D indicate parallel resistors, and 15 indicates a power supply.
As an example of this, there is JP-A-1-152971.
The technology for equalizing the voltage at the time of series connection of the semiconductor switches can be found in the publication “University Lecture Power Electronics” by Shota Miyairi, pages 38 and 39 published by Maruzen Co., Ltd.
【０００３】[0003]
【発明が解決しようとする課題】３レベルインバータ
は、１相に着目すれば、半導体スイッチ４個の直列接続
であり、また、３レベルインバータの動作状態つまり４
個の半導体スイッチのオン、オフ状態（取り得るスイッ
チングのモード）によって、各半導体スイッチにかかる
電圧分布の状態が異なる。従って、洩れ電流を考慮して
分担電圧を均等にするために、各々の素子に並列に従来
技術のように単純に抵抗値が等しい抵抗を接続するのみ
では、３レベルインバータの動作状態には十分対応する
ことができない、という問題がある。また、従来技術で
は、半導体スイッチの直列数に比例して抵抗の数が増
え、高電圧化によって抵抗の容量は電圧の２乗に比例し
て大きくする必要がある、という問題がある。本発明の
目的は、３レベルインバータからなる電力変換装置にお
いて、４組の半導体スイッチに洩れ電流の差異があって
も、スイッチングのモードに対応するインバータ動作の
安定化を図り、かつ、半導体スイッチに接続される並列
抵抗数を低減するのに好適な電力変換装置を提供するこ
とにある。When focusing on one phase, the three-level inverter is a series connection of four semiconductor switches.
The state of the voltage distribution applied to each semiconductor switch differs depending on the on / off states (possible switching modes) of the semiconductor switches. Therefore, in order to equalize the shared voltage in consideration of the leakage current, simply connecting a resistor having the same resistance value in parallel to each element as in the prior art is sufficient for the operation state of the three-level inverter. There is a problem that it cannot be handled. Further, in the related art, there is a problem that the number of resistors increases in proportion to the number of series semiconductor switches, and the capacity of the resistors needs to be increased in proportion to the square of the voltage due to a higher voltage. SUMMARY OF THE INVENTION It is an object of the present invention to stabilize the inverter operation corresponding to the switching mode even if there is a difference in leakage current between four sets of semiconductor switches in a power conversion device including a three-level inverter, An object of the present invention is to provide a power conversion device suitable for reducing the number of connected parallel resistors.
【０００４】[0004]
【課題を解決するための手段】上記目的は、３レベルイ
ンバータの各相に直列接続された４組の半導体スイッチ
の各々に抵抗を並列接続し、内側の第２と第３の半導体
スイッチの抵抗に比し、外側の第１と第４の半導体スイ
ッチの抵抗の値を高くすることにより、また、各相に直
列接続された４組の半導体スイッチの中で、４組の半導
体スイッチが全てオフ状態のときの中間の第２と第３の
半導体スイッチの両端間のインピーダンスが夫々第１と
第４の各半導体スイッチの両端間のインピーダンスより
も小さくなるように、第２と第３の半導体スイッチのみ
に並列に抵抗を接続することにより、達成される。The above object is achieved by connecting a resistor in parallel to each of four sets of semiconductor switches connected in series to each phase of a three-level inverter, and connecting the resistors of the inner second and third semiconductor switches. By increasing the resistance values of the outer first and fourth semiconductor switches as compared to the above, and among the four semiconductor switches connected in series to each phase, all four semiconductor switches are turned off. The second and third semiconductor switches such that the impedance between both ends of the intermediate second and third semiconductor switches in the state is smaller than the impedance between both ends of the first and fourth semiconductor switches, respectively. This is achieved by connecting a resistor only in parallel.
【０００５】[0005]
【作用】３レベルインバータは、１相に着目すれば、半
導体スイッチ４組の直列接続であり、各半導体スイッチ
が分担する電圧の理想としては、各半導体スイッチの洩
れ電流を考慮して、３レベルインバータの取り得るスイ
ッチングのモードにおいて、常に安定した状態を維持す
ることにある。スイッチングのモードとして、例えば半
導体スイッチが全てオフしている状態のとき、内側の第
２と第３の半導体スイッチは電圧を持たず、外側の第１
と第４の半導体スイッチが電圧を負担することにある。
本発明は、内側の第２と第３の半導体スイッチの抵抗に
比し、外側の第１と第４の半導体スイッチの抵抗の値を
高くすることにより、また、４組の半導体スイッチが全
てオフ状態のときの中間の第２と第３の半導体スイッチ
の両端間のインピーダンスが夫々第１と第４の各半導体
スイッチの両端間のインピーダンスよりも小さくなるよ
うに、第２と第３の半導体スイッチのみに並列に抵抗を
接続するのみで、４組の半導体スイッチに洩れ電流の差
異があっても、３レベルインバータの安定した動作状態
を得ることができる。The three-level inverter is a series connection of four sets of semiconductor switches when focusing on one phase. Ideally, the voltage shared by each semiconductor switch is determined by considering the leakage current of each semiconductor switch. An object of the present invention is to always maintain a stable state in a possible switching mode of the inverter. As a switching mode, for example, when all the semiconductor switches are off, the inner second and third semiconductor switches have no voltage and the outer first switch does not have a voltage.
And the fourth semiconductor switch bears the voltage.
The present invention increases the resistance of the outer first and fourth semiconductor switches as compared to the resistance of the inner second and third semiconductor switches, and furthermore, all four semiconductor switches are turned off. The second and third semiconductor switches such that the impedance between both ends of the intermediate second and third semiconductor switches in the state is smaller than the impedance between both ends of the first and fourth semiconductor switches, respectively. Only when a resistor is connected in parallel to only the three-level inverter, a stable operation state of the three-level inverter can be obtained even if there is a difference in leakage current between the four sets of semiconductor switches.
【０００６】[0006]
【実施例】以下、本発明の実施例を説明する。図１は、
本発明の第一実施例を示し、３レベルインバータの１相
分の回路である。図１において、電源（図示せず）にコ
ンデンサー１、２を接続し、このコンデンサー１、２に
並列に半導体スイッチ３Ａ〜３Ｄを４個直列に接続し、
各々の半導体スイッチには、逆並列にフリーホイールダ
イオード４Ａ〜４Ｄを接続する。コンデンサー１、２の
中点と半導体スイッチ３Ａと３Ｂの中点にクランプダイ
オード５Ａ、コンデンサー１、２の中点と半導体スイッ
チ３Ｃと３Ｄの中点にクランプダイオード５Ｂを接続
し、半導体スイッチ３Ａ、３Ｄとクランプダイオード５
Ａ、５Ｂにスナバ回路６Ａ〜６Ｄを接続する。そして、
半導体スイッチ３Ａ〜３Ｄに並列に本発明が特徴とする
分圧抵抗７、８、９、１０を接続する。なお、スナバ回
路６Ａ〜６Ｄは、ダイオード、コンデンサー、抵抗から
構成される有極性方式で記載しているが、低損失型スナ
バ回路を用いてもよい。又、半導体スイッチのシンボル
は、ＩＧＢＴを用いているが、ＧＴＯでもバイポーラト
ランジスタでもよい。Embodiments of the present invention will be described below. FIG.
1 shows a first embodiment of the present invention and is a circuit for one phase of a three-level inverter. In FIG. 1, capacitors 1 and 2 are connected to a power source (not shown), and four semiconductor switches 3A to 3D are connected in series to the capacitors 1 and 2 in series.
Freewheel diodes 4A to 4D are connected to each semiconductor switch in antiparallel. The clamp diode 5A is connected to the middle point of the capacitors 1 and 2 and the middle point of the semiconductor switches 3A and 3B, and the clamp diode 5B is connected to the middle point of the capacitors 1 and 2 and the middle point of the semiconductor switches 3C and 3D. And clamp diode 5
A and 5B are connected to snubber circuits 6A to 6D. And
The voltage dividing resistors 7, 8, 9, and 10 which are characteristic of the present invention are connected in parallel to the semiconductor switches 3A to 3D . Although the snubber circuits 6A to 6D are described in a polar system including a diode, a capacitor, and a resistor, a low-loss snubber circuit may be used. Although IGBT is used for the symbol of the semiconductor switch, it may be GTO or bipolar transistor.
【０００７】以下、第一実施例の動作原理について述べ
る。ここで、コンデンサー１、２は各々電源電圧の１／
２に充電されているものとする。先ず、半導体スイッチ
３Ａ〜３Ｄが全てオフしている状態において、各半導体
スイッチ３Ａ〜３Ｄが分担する電圧の理想としては、ク
ランプダイオード５Ａ、５Ｂの作用により、半導体スイ
ッチ３Ｂと３Ｃは電圧を持たず、半導体スイッチ３Ａが
コンデンサー１の電圧、半導体スイッチ３Ｄがコンデン
サー２の電圧を負担していることである。ここで、分圧
抵抗７、８、９、１０が無い場合についてみると、半導
体スイッチ３Ａとフリーホイールダイオード４Ａの漏れ
電流の和が、半導体スイッチ３Ｂとフリーホイールダイ
オード４Ｂおよびクランプダイオード５Ａの漏れ電流の
和より大きい時（半導体の素子のバラツキでは１桁程度
異なることはよくある）、各半導体スイッチ３Ａ〜３Ｄ
の電圧分担は、図５に示すようになる。図５では、説明
を容易にするために、漏れ電流の大きい回路を短絡線
で、漏れ電流の小さい回路を抵抗で示し、破線の円で印
をしている。３Ａ′〜３Ｄ′は半導体スイッチとフリー
ホイールダイオードの合成に、５Ａ′、５Ｂ′はクラン
プダイオードに対応している。図５から明らかなよう
に、３Ａ′の電圧Ｖ3A′は０Ｖとなり、３Ｂ′の電圧Ｖ
3B′がコンデンサー１の電圧Ｖ1となる。負側について
も同様に、３Ｄ′の電圧Ｖ3D′は０Ｖとなり、３Ｃ′の
電圧Ｖ3C′がコンデンサー２の電圧Ｖ2となる。これ
は、前述した電圧分担と逆の形となっており、極めて不
安定な状態である。次に、３レベルインバータの半導体
スイッチが全てオフの状態から点弧を開始する状態にお
いては、最初に中間素子から点弧する。例えば、電源電
位を出力する時は、中間素子の半導体スイッチ３Ｂをオ
ンした後、半導体スイッチ３Ａをオンする。この時、上
記不安定状態となっていれば、瞬間的に半導体スイッチ
３Ｃが全電圧を負担することになり、素子破壊を起す恐
れがある。Hereinafter, the operation principle of the first embodiment will be described. Here, the capacitors 1 and 2 each have a voltage of 1 /
2 is charged. First, in a state where the semiconductor switches 3A to 3D are all off, ideally the voltage shared by the semiconductor switches 3A to 3D is that the semiconductor switches 3B and 3C have no voltage due to the action of the clamp diodes 5A and 5B. And the semiconductor switch 3A bears the voltage of the capacitor 1, and the semiconductor switch 3D bears the voltage of the capacitor 2. Here, looking at the case where there are no voltage dividing resistors 7, 8, 9, and 10, the sum of the leakage currents of the semiconductor switch 3A and the freewheel diode 4A is the leakage current of the semiconductor switch 3B, the freewheel diode 4B and the clamp diode 5A. When the difference is larger than the sum of the semiconductor switches (the difference of semiconductor elements often differs by about one digit), each of the semiconductor switches 3A to 3D
Are as shown in FIG. In FIG. 5, for the sake of simplicity, a circuit with a large leakage current is indicated by a short-circuit line, and a circuit with a small leakage current is indicated by a resistor, and is marked by a broken-line circle. 3A 'to 3D' correspond to a combination of a semiconductor switch and a freewheel diode, and 5A 'and 5B' correspond to a clamp diode. As is apparent from FIG. 5, the voltage V 3A ' of 3A' becomes 0 V, and the voltage V 3A '
3B 'is the voltage V 1 of the condenser 1. Similarly, on the negative side, the voltage V 3D ′ of 3D ′ becomes 0 V, and the voltage V 3C ′ of 3C ′ becomes the voltage V 2 of the capacitor 2. This is in a state opposite to the above-described voltage sharing, and is an extremely unstable state. Next, in a state where ignition starts from a state where all the semiconductor switches of the three-level inverter are off, first, the intermediate element is fired. For example, when outputting the power supply potential, the semiconductor switch 3B of the intermediate element is turned on, and then the semiconductor switch 3A is turned on. At this time, if the semiconductor device is in the unstable state, the semiconductor switch 3C momentarily bears the entire voltage, and there is a possibility that the device may be destroyed.
【０００８】そこで、本実施例では、分圧抵抗７、８、
９、１０を設け、この分圧抵抗７、８、９、１０の大き
さを上記漏れ電流から換算される等価インピーダンスよ
り十分小さく（２桁から３桁程度）、かつ、分圧抵抗
８、９に比べ、分圧抵抗７、１０の抵抗値を十分に高く
すると、図６のようになる。すなわち、この時、クラン
プダイオード５Ａ、５Ｂはオン状態を維持し、３Ａ′の
電圧Ｖ３Ａ′がコンデンサー１の電圧Ｖ１を分圧した電
圧Ｖ１′を、３Ｂ′の電圧Ｖ３Ｂ′がコンデンサー１の
電圧Ｖ１を分圧した電圧Ｖ１′′を、３Ｃ′の電圧Ｖ
３Ｃ′がコンデンサー２の電圧Ｖ２を分圧した電圧
Ｖ２′を、３Ｄ′の電圧Ｖ３Ｄ′がコンデンサー２の電
圧Ｖ２を分圧した電圧Ｖ２′′を負担する形になる。こ
こで、電圧Ｖ１′≫Ｖ１′、電圧Ｖ２′≫Ｖ２′′の関
係になるように、分圧抵抗７、８、９、１０の抵抗値を
設定する。これは、半導体スイッチ３Ａがコンデンサー
１の電圧の大部分を、半導体スイッチ３Ｄがコンデンサ
ー２の電圧の大部分を負担し、半導体スイッチ３Ｂと３
Ｃは殆ど電圧を持たないことになり、上述した所期の安
定した状態を得る。これに対し、従来技術のように４素
子に各々並列に等価インピーダンスの小さい抵抗を並列
に接続する揚合は、それぞれの抵抗の抵抗値が等しいの
で、各素子は１／４の電圧を負担することになり、結局
不安定な状態である。Therefore, in this embodiment, the voltage dividing resistors 7, 8,
9 and 10, the size of the voltage dividing resistors 7, 8, 9 and 10 is sufficiently smaller than the equivalent impedance calculated from the leakage current (about 2 to 3 digits), and the voltage dividing resistors 8 and 9 are provided. 6 when the resistance values of the voltage dividing resistors 7 and 10 are sufficiently increased. That is, when the clamp diodes 5A, 5B maintains the ON state, 'a, 3B' voltages V 1 which is dividing the voltage V 1 of the condenser 1 minute 'voltage V 3A of the' 3A voltage V 3B 'of the capacitor The voltage V 1 ″ obtained by dividing the voltage V 1 of FIG.
The 3C 'the voltage V 2 obtained by dividing the voltage V 2 of the condenser 2 minute', made into a form that will be borne by the voltage V 2 '' obtained by dividing the voltage V 2 of the condenser 2 minute 'voltage V 3D of' 3D. Here, the voltage V 1 '»V 1', so that the relationship between the voltage V 2 '»V 2'', setting the resistance value of the voltage dividing resistors 7, 8, 9, 10. This is because the semiconductor switch 3A bears most of the voltage of the capacitor 1, the semiconductor switch 3D bears most of the voltage of the capacitor 2, and the semiconductor switches 3B and 3B
C has almost no voltage, and the expected stable state described above is obtained. On the other hand, when the resistors having small equivalent impedances are connected in parallel to the four elements as in the prior art, each element bears a voltage of 1/4 since the resistance values of the respective resistors are equal. In other words, it is an unstable state after all.
【０００９】次に、半導体スイッチ３Ａ、３Ｂがオフ
し、半導体スイッチ３Ｃ、３Ｄがオンしている状態にお
いては、半導体スイッチ３Ａがコンデンサー１の電圧
を、半導体スイッチ３Ｂがコンデンサー２の電圧を負担
するのが理想である。この場合、図７に示すのようにな
る。分圧抵抗７、８は、電圧を負担するため抵抗のまま
表記している。３Ａ′の漏れ電流Ｉ3A′が３Ｂ′の漏れ
電流Ｉ3B′より大きい場合でも、分圧抵抗７の電流Ｉ7
とともに、分圧抵抗８に電流Ｉ8として分流し、さらに
クランプダイオード５Ａもオン状態を維持する。漏れ電
流の関係は（１）式となる。 Ｉ8＋Ｉ3B′＝Ｉ3A′＋Ｉ5A＋Ｉ7 （１） この作用によって、３Ａ′の電圧Ｖ3A′がコンデンサー
１の電圧Ｖ1を、３Ｂ′の電圧Ｖ3B′がコンデンサー２
の電圧Ｖ2を負担し、所期の安定した状態を得る。逆
に、半導体スイッチ３Ａ、３Ｂがオンし、半導体スイッ
チ３Ｃ、３Ｄがオフしている場合も同様になる。又、半
導体スイッチ３Ａ、３Ｄがオフし、半導体スイッチ３
Ｂ、３Ｃがオンしている場合は、クランプダイオードの
作用により、半導体スイッチ３Ａがコンデンサー１の電
圧を、半導体スイッチ３Ｄがコンデンサー２の電圧を各
々負担することは自明である。以上本実施例によれば、
内側の半導体スイッチに並列接続される分圧抵抗に比
べ、外側の半導体スイッチに並列接続される分圧抵抗の
抵抗値を十分に高くしたので、４個の半導体スイッチ素
子のスイッチングのモードに対応して、上述した所期の
安定した状態を得ることができる。Next, when the semiconductor switches 3A and 3B are off and the semiconductor switches 3C and 3D are on, the semiconductor switch 3A bears the voltage of the capacitor 1 and the semiconductor switch 3B bears the voltage of the capacitor 2. Is ideal. In this case, the result is as shown in FIG. The voltage dividing resistors 7 and 8 are shown as resistors to bear the voltage. Even if the leakage current I 3A ′ of 3A ′ is larger than the leakage current I 3B ′ of 3B ′ , the current I 7 of the voltage dividing resistor 7
Together with the partial flows as a current I 8 dividing resistor 8, further clamp diodes 5A also kept on. The relationship between the leakage currents is given by equation (1). I 8 + I 3B '= I 3A' + I 5A + I 7 (1) by this action, the voltage V 1 is the condenser 1 'voltage V 3A of the' 3A, 'voltage V 3B of the' 3B is a condenser 2
Bear the voltage V 2, to obtain the desired stable state. Conversely, the same applies when the semiconductor switches 3A and 3B are on and the semiconductor switches 3C and 3D are off. Also, the semiconductor switches 3A and 3D are turned off and the semiconductor switch 3
When B and 3C are on, it is obvious that the semiconductor switch 3A bears the voltage of the capacitor 1 and the semiconductor switch 3D bears the voltage of the capacitor 2 by the action of the clamp diode. According to the present embodiment,
The resistance value of the voltage dividing resistor connected in parallel to the outer semiconductor switch is sufficiently higher than that of the voltage dividing resistor connected in parallel to the inner semiconductor switch. Thus, the expected stable state described above can be obtained.
【００１０】図２は、本発明の第二実施例を示す。本実
施例は、第一実施例の分圧抵抗７、１０を除去した点で
異なり、その他は同じである。先ず、半導体スイッチ３
Ａ〜３Ｄが全てオフしている状態において、本実施例で
は、分圧抵抗８、の大きさを第一実施例と同様に上記漏
れ電流から換算される等価インピーダンスより十分小さ
く（２桁から３桁程度）すると、図８に示すようにな
る。すなわち、分圧抵抗８、９は短絡線８′、９′のよ
うにみなされる。この時、クランプダイオード５Ａ、５
Ｂはオン状態を維持し、３Ｂ′、３Ｃ′の電圧Ｖ3B′、
Ｖ3C′は０Ｖとなり、３Ａ′の電圧Ｖ3A′がコンデンサ
ー１の電圧Ｖ1を、３Ｄ′の電圧Ｖ3D′がコンデンサー
２の電圧Ｖ2を負担する形になり、所期の安定した状態
を得る。FIG. 2 shows a second embodiment of the present invention. This embodiment is different from the first embodiment in that the voltage dividing resistors 7 and 10 are removed, and the other parts are the same. First, the semiconductor switch 3
In the state where A to 3D are all turned off, in the present embodiment, the magnitude of the voltage dividing resistor 8 is sufficiently smaller than the equivalent impedance converted from the leakage current as in the first embodiment (from two digits to three digits). Then, as shown in FIG. That is, the voltage dividing resistors 8 and 9 are regarded as short-circuit lines 8 'and 9'. At this time, the clamp diodes 5A, 5A
B maintains the ON state, and the voltage V 3B ′ of 3B ′, 3C ′ ,
V 3C ′ becomes 0 V, and the voltage 3A ′ V 3A ′ bears the voltage V 1 of the capacitor 1 and the voltage 3D ′ V 3D ′ bears the voltage V 2 of the capacitor 2, and the expected stable state Get.
【００１１】次に、半導体スイッチ３Ａ、３Ｂがオフ
し、半導体スイッチ３Ｃ、３Ｄがオンしている状態にお
いては、上述したと同様、半導体スイッチ３Ａがコンデ
ンサー１の電圧を、半導体スイッチ３Ｂがコンデンサー
２の電圧を負担するのが理想である。この場合、図９に
示すのようになる。分圧抵抗８は、電圧を負担するため
抵抗のまま表記している。３Ａ′の漏れ電流Ｉ３Ａ′が
３Ｂ′の漏れ電流Ｉ３Ｂ′より大きい場合でも、分圧抵
抗８に分流し、さらにクランプダイオード５Ａもオン状
態を維持する。漏れ電流の関係は（２）式となる。 Ｉ ８ ＋Ｉ３Ｂ′＝Ｉ３Ａ′＋Ｉ５Ａ （２） この作用によって、３Ａ′の電圧Ｖ３Ａ′がコンデンサ
ー１の電圧Ｖ１を、３Ｂ′の電圧Ｖ３Ｂ′がコンデンサ
ー２の電圧Ｖ２を負担し、所期の安定した状態を得る。
逆に、半導体スイッチ３Ａ、３Ｂがオンし、半導体スイ
ッチ３Ｃ、３Ｄがオフしている場合も同様になる。又、
半導体スイッチ３Ａ、３Ｄがオフし、半導体スイッチ３
Ｂ、３Ｃがオンしている場合は、クランプダイオードの
作用により、半導体スイッチ３Ａがコンデンサー１の電
圧を、半導体スイッチ３Ｄがコンデンサー２の電圧を各
々負担することは自明である。以上本実施例によれば、
第一実施例の効果に加え、従来技術に比し、半導体スイ
ッチに接続される並列抵抗数を低減することができ、経
済的である。Next, in a state where the semiconductor switches 3A and 3B are off and the semiconductor switches 3C and 3D are on, the semiconductor switch 3A applies the voltage of the capacitor 1 and the semiconductor switch 3B uses the capacitor 2 It is ideal to bear this voltage. In this case, the result is as shown in FIG. The voltage dividing resistor 8 is shown as a resistor to bear a voltage. Even when greater than 'leakage current I 3B' of 3B 'leakage current I 3A' of 3A, flow dividing resistors 8 binary, further also kept on clamp diodes 5A. The relationship between the leakage currents is given by equation (2). By I 8 + I 3B '= I 3A' + I 5A (2) this effect, pay voltages V 1 of the capacitor 1 'voltage V 3A of the' 3A, 3B is a voltage V 2 of capacitor 2 'voltage V 3B of the' And obtain the expected stable state.
Conversely, the same applies when the semiconductor switches 3A and 3B are on and the semiconductor switches 3C and 3D are off. or,
When the semiconductor switches 3A and 3D are turned off, the semiconductor switch 3
When B and 3C are on, it is obvious that the semiconductor switch 3A bears the voltage of the capacitor 1 and the semiconductor switch 3D bears the voltage of the capacitor 2 by the action of the clamp diode. According to the present embodiment,
In addition to the effects of the first embodiment, the number of parallel resistors connected to the semiconductor switch can be reduced compared to the prior art, which is economical.
【００１２】図３は、図２の第二実施例を１相分とした
回路を並列接続して３相とし、出力を誘導電動機１６に
接続した電気車制御装置に適用した例である。図３にお
いて、各相１５Ｂ、１５Ｃは１５Ａと同一回路となる。
電源分割のフィルタコンデンサー１、２は一括して記載
し、スナバ回路６Ａ〜６Ｄは省略して記載している。フ
ィルタコンデンサー１、２は、架線１１とパンタグラフ
１２、遮断器１３、フィルタリアクトル１４を介して電
源１７に接続されている。誘導電動機１６は、半導体ス
イッチの容量によって複数並列接続する。インバータの
動作は、各相が電源電位、中間電位、接地電位をとり、
各々の組合せによって３相交流を出力する。個々の状態
の分圧抵抗の作用は、第二実施例の１相について説明し
た作用と同じになる。FIG. 3 shows an example in which the circuit of the second embodiment of FIG. 2 for one phase is connected in parallel to form three phases, and the output is connected to an induction motor 16 for an electric vehicle control device. In FIG. 3, each phase 15B, 15C has the same circuit as 15A.
The filter capacitors 1 and 2 for power supply division are collectively described, and the snubber circuits 6A to 6D are omitted. The filter capacitors 1 and 2 are connected to a power supply 17 via an overhead wire 11, a pantograph 12, a circuit breaker 13, and a filter reactor 14. A plurality of induction motors 16 are connected in parallel by the capacity of the semiconductor switch. In the operation of the inverter, each phase takes the power supply potential, the intermediate potential, and the ground potential,
A three-phase alternating current is output by each combination. The operation of the voltage dividing resistor in each state is the same as the operation described for one phase of the second embodiment.
【００１３】図１０は、本発明の第三実施例を示す。本
実施例は、第一および第二実施例において、分圧抵抗
８、９をクランプダイオード５Ａ、５Ｂに並列に接線し
た例である。なお、図１０では第一実施例の分圧抵抗
７、１０の記載およびスナバ回路は省略している。全半
導体スイッチがオフの時の動作の場合、第一実施例で
は、分圧抵抗８、９のインピーダンスは、半導体スイッ
チ３Ａ、３Ｄに比べ、かつ、図示しない分圧抵抗７、１
０の抵抗値に比べ十分小さいので、電圧は低く抑えら
れ、半導体スイッチ３Ｂ、３Ｃの電圧分坦は、第一実施
例と同様に殆どない。また、第二実施例では、分圧抵抗
８、９のインピーダンスは、半導体スイッチ３Ａ、３Ｄ
に比べ十分小さいので、電圧は低く抑えられ、結局、半
導体スイッチ３Ｂ、３Ｃの電圧分坦は、第二実施例と同
様にほぼ０Ｖとなる。半導体スイッチ３Ａ、３Ｂがオフ
し、半導体スイッチ３Ｃ、３Ｄがオンの場合、第一およ
び第二実施例とも、抵抗９が半導体スイッチ３Ｂに並列
に接続された形となり、第一および第二実施例で述べた
動作と同様の動作となる。逆に、半導体スイッチ３Ａ、
３Ｂがオンし、半導体スイッチ３Ｃ、３Ｄがオフしてい
る場合、又、半導体スイッチ３Ａ、３Ｄがオフし、半導
体スイッチ３Ｂ、３Ｃがオンしている場合も、第一およ
び第二実施例で述べた動作と同様の動作となる。FIG. 10 shows a third embodiment of the present invention. This embodiment is an example in which the voltage dividing resistors 8 and 9 are connected in parallel to the clamp diodes 5A and 5B in the first and second embodiments. In FIG. 10, the voltage dividing resistors 7 and 10 and the snubber circuit of the first embodiment are omitted. In the case of the operation when all the semiconductor switches are off, in the first embodiment, the impedances of the voltage dividing resistors 8 and 9 are smaller than those of the semiconductor switches 3A and 3D and are not shown.
Since the resistance value is sufficiently smaller than the resistance value of 0, the voltage is kept low, and the voltage distribution of the semiconductor switches 3B and 3C is almost nil as in the first embodiment. Further, in the second embodiment, the impedance of the voltage dividing resistors 8 and 9 is determined by the semiconductor switches 3A and 3D.
Therefore, the voltage is suppressed to be low, and the voltage distribution of the semiconductor switches 3B and 3C becomes substantially 0 V similarly to the second embodiment. When the semiconductor switches 3A and 3B are off and the semiconductor switches 3C and 3D are on, both the first and second embodiments have a configuration in which the resistor 9 is connected in parallel to the semiconductor switch 3B. The operation is similar to the operation described above. Conversely, the semiconductor switch 3A,
The case where the semiconductor switch 3B is on and the semiconductor switches 3C and 3D are off, and the case where the semiconductor switches 3A and 3D are off and the semiconductor switches 3B and 3C are on, are also described in the first and second embodiments. The operation is the same as the operation performed.
【００１４】図１１は、本発明の第四実施例を示す。本
実施例では、分圧抵抗を素子個別に接続するのでなく、
一括接続とすることにより、回路要素を低減した例であ
る。図１１も第一実施例の分圧抵抗７、１０の記載およ
びスナバ回路を省略して記載している。全半導体スイッ
チがオフの時の動作の場合、図１０で説明した第一およ
び第二実施例と同じ動作となる。半導体スイッチ３Ａ、
３Ｂがオフし、半導体スイッチ３Ｃ、３Ｄがオンの場
合、分圧抵抗８は、コンデンサー中点―クランプダイオ
ード５Ａ―分圧抵抗８の経路で半導体スイッチ３Ｂに並
列に接続されるので、同様の動作が得られる。逆に、半
導体スイッチ３Ａ、３Ｂがオンし、半導体スイッチ３
Ｃ、３Ｄがオフしている場合、又、半導体スイッチ３
Ａ、３Ｄがオフし、半導体スイッチ３Ｂ、３Ｃがオンし
ている場合も、同様の動作が得られる。以上第三および
第四本実施例によれば、第一実施例の効果に加え、従来
技術に比し、さらに半導体スイッチに接続される並列抵
抗数を低減することができ、経済的である。なお、以上
の説明では、３Ｖレベルインバータを構成する１相分に
つき、４個直列の半導体スイッチについて述べたが、こ
の半導体スイッチの組合せとして、さらに並列化・直列
化した３Ｖレベルインバータに適用することができる。FIG. 11 shows a fourth embodiment of the present invention. In this embodiment, instead of connecting the voltage dividing resistors individually to the elements,
This is an example in which circuit elements are reduced by performing collective connection. FIG. 11 also omits the description of the voltage dividing resistors 7 and 10 and the snubber circuit of the first embodiment. When the operation is performed when all the semiconductor switches are off, the operation is the same as that of the first and second embodiments described with reference to FIG. Semiconductor switch 3A,
When the semiconductor switch 3B is turned off and the semiconductor switches 3C and 3D are turned on, the voltage dividing resistor 8 is connected in parallel to the semiconductor switch 3B through the path of the capacitor middle point-the clamp diode 5A-the voltage dividing resistor 8; Is obtained. Conversely, the semiconductor switches 3A and 3B are turned on and the semiconductor switch 3
When C and 3D are off, the semiconductor switch 3
A similar operation is obtained when A and 3D are off and the semiconductor switches 3B and 3C are on. According to the third and fourth embodiments, in addition to the effects of the first embodiment, the number of parallel resistors connected to the semiconductor switches can be further reduced compared to the prior art, which is economical. In the above description, four series semiconductor switches are described for one phase constituting the 3V level inverter. However, the combination of the semiconductor switches is applied to a further parallelized / serialized 3V level inverter. Can be.
【００１５】[0015]
【発明の効果】本発明によれば、内側の半導体スイッチ
に並列接続される分圧抵抗に比べ、外側の半導体スイッ
チに並列接続される分圧抵抗の抵抗値を十分に高くする
こと、また、３Ｖレベルインバータを構成する４組直列
の半導体スイッチの中、分圧抵抗を中間の２半導体スイ
ッチ間に並列接続すること、また、クランプダイオード
に分圧抵抗を一または二組を並列接続することによっ
て、４組の半導体スイッチに洩れ電流の差異があって
も、４組の半導体スイッチオン、オフ状態（取り得るス
イッチングのモード）に対応して、３レベルインバータ
の安定した動作状態を得ることができる。また、本発明
は、３Ｖレベルインバータを構成する４組直列の半導体
スイッチの中、分圧抵抗を中間の２半導体スイッチ間に
並列接続するのみで、また、クランプダイオードに分圧
抵抗を一または二組を並列接続するのみで構成するの
で、従来技術に比し、その数を低減することが可能とな
り、経済的である。According to the present invention, the resistance value of the voltage dividing resistor connected in parallel to the outer semiconductor switch is made sufficiently higher than the voltage dividing resistor connected in parallel to the inner semiconductor switch. By connecting a voltage dividing resistor in parallel between two intermediate semiconductor switches among four sets of series semiconductor switches constituting a 3V level inverter, and connecting one or two sets of voltage dividing resistors to a clamp diode in parallel. Even if there is a difference in leakage current between the four sets of semiconductor switches, a stable operation state of the three-level inverter can be obtained corresponding to the four sets of semiconductor switches being turned on and off (possible switching modes). . In addition, the present invention merely connects a voltage dividing resistor in parallel between two intermediate semiconductor switches among four sets of series semiconductor switches constituting a 3V level inverter, and furthermore, connects one or two voltage dividing resistors to a clamp diode. Since the configuration is made only by connecting the sets in parallel, the number can be reduced as compared with the related art, which is economical.
【図１】本発明の第一実施例を示す１相分の回路図。FIG. 1 is a circuit diagram of one phase showing a first embodiment of the present invention.
【図２】本発明の第二実施例を示す１相分の回路図。FIG. 2 is a circuit diagram of one phase showing a second embodiment of the present invention.
【図３】本発明の第二実施例を用いた電気車制御装置の
主回路構成図。FIG. 3 is a main circuit configuration diagram of an electric vehicle control device using a second embodiment of the present invention.
【図４】従来技術による半導体スイッチの直列接続回
路。FIG. 4 shows a series connection circuit of semiconductor switches according to the prior art.
【図５】分圧抵抗が無い場合の動作を説明する図。FIG. 5 is a diagram illustrating an operation when there is no voltage dividing resistor.
【図６】本発明の第一実施例の全素子オフ時の動作を説
明する図。FIG. 6 is a diagram for explaining an operation when all elements are off according to the first embodiment of the present invention.
【図７】本発明の第一実施例の上側２素子がオフ、下側
２素子がオンの場合の動作を説明する図。FIG. 7 is a diagram illustrating the operation of the first embodiment of the present invention when the upper two elements are off and the lower two elements are on.
【図８】本発明の第ニ実施例の全素子オフ時の動作を説
明する図。FIG. 8 is a diagram illustrating an operation when all elements are off according to the second embodiment of the present invention.
【図９】本発明の第ニ実施例の上側２素子がオフ、下側
２素子がオンの場合の動作を説明する図。FIG. 9 is a diagram illustrating the operation of the second embodiment of the present invention when the upper two elements are off and the lower two elements are on.
【図１０】本発明の第三実施例を示す１相分の回路図。FIG. 10 is a circuit diagram of one phase showing a third embodiment of the present invention.
【図１１】本発明の第四実施例を示す１相分の回路図。FIG. 11 is a circuit diagram of one phase showing a fourth embodiment of the present invention.
１、２ コンデンサー ３Ａ〜３Ｄ 半導体スイッチ ４Ａ〜４Ｄ フリーホイールダイオード ５Ａ、５Ｂ クランプダイオード ６Ａ〜６Ｄ スナバ回路 ７、８、９、１０ 分圧抵抗 １１ 架線 １２ パンタグラフ １３ 遮断機 １４ フィルタリアクトル １５Ａ〜１５Ｃ ３レベルインバータの１相分の回路
図。 １６ 誘導電動機 １７ 直流電源1, 2 Condenser 3A-3D Semiconductor switch 4A-4D Freewheel diode 5A, 5B Clamp diode 6A-6D Snubber circuit 7, 8, 9, 10 Voltage dividing resistor 11 Overhead wire 12 Pantograph 13 Circuit breaker 14 Filter reactor 15A-15C 3 levels FIG. 2 is a circuit diagram of one phase of the inverter. 16 Induction motor 17 DC power supply
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H02M 7/48 H02M 7/515 H02M 7/521 H02M 7/5387 H02P 7/63 302 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H02M 7/48 H02M 7/515 H02M 7/521 H02M 7/5387 H02P 7/63 302
Claims (6)
電源手段と、第１から第４まで順に直列接続された４組
の半導体スイッチの直列接続体とからなり、前記第１と
第２の半導体スイッチがオン状態でかつ前記第３と第４
の半導体スイッチがオフ状態で前記電源手段の正電位
が、又その逆のスイッチング状態で前記電源手段の負電
位が、さらに前記第２又は第３の半導体スイッチがオン
状態でかつ前記第１と第４の半導体スイッチがオフ状態
で前記電源手段の中間電位がそれぞれ前記第２と第３の
半導体スイッチの直列接続点である交流端子に出力され
るように構成された電力変換装置において、 前記４組の半導体スイッチの各々に抵抗を並列接続し、
前記第１の半導体スイッチに接続される前記抵抗の抵抗
値を第２の半導体スイッチに接続される前記抵抗の抵抗
値より大きくし、前記第４の半導体スイッチに接続され
る前記抵抗の抵抗値を前記第３の半導体スイッチに接続
される前記抵抗の抵抗値より大きくしたことを特徴とす
る電力変換装置。1. A power supply means having three potentials, positive, negative, and intermediate potentials, and a series connection of four sets of semiconductor switches connected in series from a first to a fourth. The second semiconductor switch is in the ON state and the third and fourth switches are in the ON state.
The positive potential of the power supply means is in the off state of the semiconductor switch, the negative potential of the power supply means is in the opposite switching state, and the second or third semiconductor switch is in the on state, and the first and the second are in the on state In a power converter configured to output an intermediate potential of the power supply unit to an AC terminal that is a series connection point of the second and third semiconductor switches when the semiconductor switch of No. 4 is in an off state, A resistor is connected in parallel to each of the semiconductor switches of
The resistance value of the resistor connected to the first semiconductor switch is made larger than the resistance value of the resistor connected to the second semiconductor switch, and the resistance value of the resistor connected to the fourth semiconductor switch is increased. A power converter, wherein the resistance value of the resistor connected to the third semiconductor switch is larger than the resistance value.
電源手段と、第１から第４まで順に直列接続された４組
の半導体スイッチの直列接続体とからなり、前記第１と
第２の半導体スイッチがオン状態でかつ前記第３と第４
の半導体スイッチがオフ状態で前記電源手段の正電位
が、又その逆のスイッチング状態で前記電源手段の負電
位が、さらに前記第２又は第３の半導体スイッチがオン
状態でかつ前記第１と第４の半導体スイッチがオフ状態
で前記電源手段の中間電位がそれぞれ前記第２と第３の
半導体スイッチの直列接続点である交流端子に出力され
るように構成された電力変換装置において、 前記４組の半導体スイッチが全てオフ状態のときの前記
第２と第３の半導体スイッチの両端間のインピーダンス
が夫々前記第１と第４の各半導体スイッチの両端間のイ
ンピーダンスよりも小さくなるように、前記第２と第３
の半導体スイッチのみに並列に抵抗を接続したことを特
徴とする電力変換装置。2. A power supply means having three potentials between positive, negative and intermediate, and a series connection of four sets of semiconductor switches connected in series from a first to a fourth. The second semiconductor switch is in the ON state and the third and fourth switches are in the ON state.
The positive potential of the power supply means is in the off state of the semiconductor switch, the negative potential of the power supply means is in the opposite switching state, and the second or third semiconductor switch is in the on state and the first and the second semiconductor switches are in the on state. In a power converter configured to output an intermediate potential of the power supply unit to an AC terminal that is a series connection point of the second and third semiconductor switches when the semiconductor switch of No. 4 is in an off state, So that the impedance between both ends of the second and third semiconductor switches when all of the semiconductor switches are in the off state is smaller than the impedance between both ends of the first and fourth semiconductor switches, respectively. 2nd and 3rd
A power converter characterized in that a resistor is connected in parallel only to the semiconductor switch of (1).
された２つのコンデンサの直列体の両端に、第１から第
４まで順に直列接続された４組の半導体スイッチの直列
接続体の両端が接続され、前記第１と第２の半導体スイ
ッチの直列接続点と前記第３と第４の半導体スイッチの
直列接続点との間に２つのダイードの直列体が前記第
２、第３の半導体スイッチの極性とは逆極性で並列とな
るように接続され、前記コンデンサの直列接続点と前記
ダイオードの直列接続点とが電気的に接続されてなり、
前記第１と第２の半導体スイッチがオン状態でかつ前記
第３と第４の半導体スイッチがオフ状態で前記直流電源
の正電位が、又その逆のスイッチング状態で前記直流電
源の負電位が、さらに前記第２又は第３の半導体スイッ
チがオン状態でかつ前記第１と第４の半導体スイッチが
オフ状態で前記コンデンサの直列接続点の電位がそれぞ
れ前記第２と第３の半導体スイッチの直列接続点である
交流端子に出力される電力変換装置において、 前記第１と第４の各半導体スイッチに抵抗を並列接続
し、前記第２つの各ダイオードに抵抗を並列接続し、該
ダイオードそれぞれに並列接続される抵抗の抵抗値が前
記第１及び第４の半導体スイッチに並列接続される抵抗
の抵抗値より小さいことを特徴とする電力変換装置。3. Both ends of a series connection of four sets of semiconductor switches serially connected in series from first to fourth are connected to both ends of a series connection of two capacitors connected in series so as to divide a DC power supply voltage. A second diode connected in series between the series connection point of the first and second semiconductor switches and the series connection point of the third and fourth semiconductor switches. Are connected in parallel with the polarity opposite to that of the capacitor, and the series connection point of the capacitor and the series connection point of the diode are electrically connected,
When the first and second semiconductor switches are on and the third and fourth semiconductor switches are off, the positive potential of the DC power supply is changed, and when the switching state is reversed, the negative potential of the DC power supply is changed. Further, when the second or third semiconductor switch is turned on and the first and fourth semiconductor switches are turned off, the potential of the series connection point of the capacitor is connected in series with the second and third semiconductor switches, respectively. In a power converter output to an AC terminal as a point, a resistor is connected in parallel to each of the first and fourth semiconductor switches, a resistor is connected in parallel to each of the second diodes, and a parallel connection is made to each of the diodes. The power converter according to claim 1, wherein a resistance value of the resistor is smaller than a resistance value of a resistor connected in parallel to the first and fourth semiconductor switches.
された２つのコンデンサの直列体の両端に、第１から第
４まで順に直列接続された４組の半導体スイッチの直列
接続体の両端が接続され、前記第１と第２の半導体スイ
ッチの直列接続点と前記第３と第４の半導体スイッチの
直列接続点との間に２つのダイードの直列体が前記第
２、第３の半導体スイッチの極性とは逆極性で並列とな
るように接続され、前記コンデンサの直列接続点と前記
ダイオードの直列接続点とが電気的に接続されてなり、
前記第１と第２の半導体スイッチがオン状態でかつ前記
第３と第４の半導体スイッチがオフ状態で前記直流電源
の正電位が、又その逆のスイッチング状態で前記直流電
源の負電位が、さらに前記第２又は第３の半導体スイッ
チがオン状態でかつ前記第１と第４の半導体スイッチが
オフ状態で前記コンデンサの直列接続点の電位がそれぞ
れ前記第２と第３の半導体スイッチの直列接続点である
交流端子に出力される電力変換装置において、 前記４組の半導体スイッチが全てオフ状態のときの前記
第２と第３の半導体スイッチ両端間のインピーダンスが
前記第１と第４の各半導体スイッチ両端間のインピーダ
ンスよりも小さくなるように、前記直列体の各ダイオー
ドに抵抗を並列接続したことを特徴とする電力変換装
置。4. Both ends of a series connection of four sets of semiconductor switches connected in series from first to fourth are connected to both ends of a series connection of two capacitors connected in series so as to divide a DC power supply voltage. A second diode connected in series between the series connection point of the first and second semiconductor switches and the series connection point of the third and fourth semiconductor switches. Are connected in parallel with the polarity opposite to that of the capacitor, and the series connection point of the capacitor and the series connection point of the diode are electrically connected,
When the first and second semiconductor switches are on and the third and fourth semiconductor switches are off, the positive potential of the DC power supply is changed, and when the switching state is reversed, the negative potential of the DC power supply is changed. Further, when the second or third semiconductor switch is turned on and the first and fourth semiconductor switches are turned off, the potential of the series connection point of the capacitor is connected in series with the second and third semiconductor switches, respectively. In the power conversion device output to the AC terminal, which is a point, the impedance between both ends of the second and third semiconductor switches when all of the four semiconductor switches are in the OFF state is equal to the impedance of the first and fourth semiconductor switches. A power converter, wherein a resistor is connected in parallel to each diode of the series body so as to be smaller than an impedance between both ends of the switch.
電源手段と、第１から第４まで順に直列接続された４組
の半導体スイッチの直列接続体とからなり、前記第１と
第２の半導体スイッチがオン状態でかつ前記第３と第４
の半導体スイッチがオフ状態で前記電源手段の正電位
が、又その逆のスイッチング状態で前記電源手段の負電
位が、さらに前記第２又は第３の半導体スイッチがオン
状態でかつ前記第１と第４の半導体スイッチがオフ状態
で前記電源手段の中間電位がそれぞれ前記第２と第３の
半導体スイッチの直列接続点である交流端子に出力され
るように構成された電力変換装置において、 前記４組の半導体スイッチが全てオフ状態のときの前記
第２と第３の各半導体スイッチの両端間のインピーダン
スが前記第１と第４の各半導体スイッチの両端間のイン
ピーダンスよりも小さくなるように、前記第１と第２の
半導体スイッチの直列接続点と前記第３と第４の半導体
スイッチの直列接続点とを抵抗を介して接続したことを
特徴とする電力変換装置。5. A power supply means having three potentials between positive, negative and intermediate, and a series connection of four sets of semiconductor switches connected in series from a first to a fourth, wherein the first and the fourth are connected. The second semiconductor switch is in the ON state and the third and fourth switches are in the ON state.
The positive potential of the power supply means is in the off state of the semiconductor switch, the negative potential of the power supply means is in the opposite switching state, and the second or third semiconductor switch is in the on state and the first and the second semiconductor switches are in the on state. In a power converter configured to output an intermediate potential of the power supply unit to an AC terminal that is a series connection point of the second and third semiconductor switches when the semiconductor switch of No. 4 is in an off state, So that the impedance between both ends of the second and third semiconductor switches when all of the semiconductor switches are off is smaller than the impedance between both ends of the first and fourth semiconductor switches. A power converter, wherein a series connection point of the first and second semiconductor switches and a series connection point of the third and fourth semiconductor switches are connected via a resistor.
電源手段と、第１から第４まで順に直列接続された４組
の半導体スイッチの直列接続体とからなり、前記第１と
第２の半導体スイッチがオン状態でかつ前記第３と第４
の半導体スイッチがオフ状態で前記電源手段の正電位
が、又その逆のスイッチング状態で前記電源手段の負電
位が、さらに前記第２又は第３の半導体スイッチがオン
状態でかつ前記第１と第４の半導体スイッチがオフ状態
で前記電源手段の中間電位がそれぞれ前記第２と第３の
半導体スイッチの直列接続点である交流端子に出力され
るように構成された電力変換装置において、 前記４組の半導体スイッチが全てオフ状態のときの前記
第２と第３の各半導体スイッチの両端間のインピーダン
スが前記第１と第４の各半導体スイッチの両端間のイン
ピーダンスよりも小さくなるように、前記第１乃至４の
半導体スイッチの少なくとも何れかにインピーダンス素
子を結合させたことを特徴とする電力変換装置。6. A power supply means having three potentials, positive, negative, and intermediate between them, and a series connection of four sets of semiconductor switches connected in series from a first to a fourth. The second semiconductor switch is in the ON state and the third and fourth switches are in the ON state.
The positive potential of the power supply means is in the off state of the semiconductor switch, the negative potential of the power supply means is in the opposite switching state, and the second or third semiconductor switch is in the on state and the first and the second semiconductor switches are in the on state. In a power converter configured to output an intermediate potential of the power supply unit to an AC terminal that is a series connection point of the second and third semiconductor switches when the semiconductor switch of No. 4 is in an off state, So that the impedance between both ends of the second and third semiconductor switches when all of the semiconductor switches are off is smaller than the impedance between both ends of the first and fourth semiconductor switches. A power converter, wherein an impedance element is coupled to at least one of the semiconductor switches of 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27607593A JP3160792B2 (en) | 1993-10-07 | 1993-10-07 | Power converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27607593A JP3160792B2 (en) | 1993-10-07 | 1993-10-07 | Power converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07111784A JPH07111784A (en) | 1995-04-25 |
| JP3160792B2 true JP3160792B2 (en) | 2001-04-25 |
Family
ID=17564457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27607593A Expired - Lifetime JP3160792B2 (en) | 1993-10-07 | 1993-10-07 | Power converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3160792B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170033438A (en) | 2015-03-16 | 2017-03-24 | 후지 덴키 가부시키가이샤 | Exhaust gas treatment apparatus |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6080714B2 (en) * | 2013-07-16 | 2017-02-15 | 東芝三菱電機産業システム株式会社 | Power converter |
| US9774241B2 (en) | 2013-09-10 | 2017-09-26 | National Institute Of Advanced Industrial Science And Technology | Power conversion circuit and device |
| CN103715927A (en) * | 2013-12-31 | 2014-04-09 | 山东新风光电子科技发展有限公司 | Regenerative brake absorption device based on inverter |
| KR101627307B1 (en) * | 2014-05-13 | 2016-06-07 | 아주대학교산학협력단 | Three-level neutral point clamped inverter for prevention of switch fault accident because of leakage current |
| CN105429499B (en) * | 2015-11-25 | 2018-01-23 | 燕山大学 | A kind of modulator approach of non-isolation type three-phase tri-level photovoltaic DC-to-AC converter |
| US11323044B2 (en) | 2017-04-20 | 2022-05-03 | Danfoss Power Electronics A/S | Three-level inverter and a three-level brake chopper |
| JP2020072495A (en) * | 2018-10-29 | 2020-05-07 | 株式会社日立製作所 | Power conversion device |
| CN110212812B (en) * | 2019-06-11 | 2021-07-16 | 国家能源投资集团有限责任公司 | Starting control circuit of direct-current oil pump motor and control method thereof |
-
1993
- 1993-10-07 JP JP27607593A patent/JP3160792B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170033438A (en) | 2015-03-16 | 2017-03-24 | 후지 덴키 가부시키가이샤 | Exhaust gas treatment apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07111784A (en) | 1995-04-25 |
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