JP3147162B2 - Bump arrangement method for flip chip integrated circuit and flip chip integrated circuit - Google Patents

Bump arrangement method for flip chip integrated circuit and flip chip integrated circuit

Info

Publication number
JP3147162B2
JP3147162B2 JP19754798A JP19754798A JP3147162B2 JP 3147162 B2 JP3147162 B2 JP 3147162B2 JP 19754798 A JP19754798 A JP 19754798A JP 19754798 A JP19754798 A JP 19754798A JP 3147162 B2 JP3147162 B2 JP 3147162B2
Authority
JP
Japan
Prior art keywords
integrated circuit
chip integrated
bump
flip
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP19754798A
Other languages
Japanese (ja)
Other versions
JP2000031188A (en
Inventor
正 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19754798A priority Critical patent/JP3147162B2/en
Publication of JP2000031188A publication Critical patent/JP2000031188A/en
Application granted granted Critical
Publication of JP3147162B2 publication Critical patent/JP3147162B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、フリップチップ集
積回路における電源用バンプの配置方法に関する。
The present invention relates to a method for arranging power supply bumps in a flip-chip integrated circuit.

【0002】[0002]

【従来の技術】従来のフリップチップ集積回路は、基板
との実装面の所定の位置に、バンプを接続するための電
極を必要な数だけ配設した構造である。
2. Description of the Related Art A conventional flip-chip integrated circuit has a structure in which a necessary number of electrodes for connecting bumps are arranged at predetermined positions on a mounting surface with a substrate.

【0003】[0003]

【発明が解決しようとする課題】このようなフリップチ
ップ集積回路では、バンプに使用された半田などのバン
プ材料の組成が製造後に変化してバンプに含まれている
α線などの放射線量が増えることがある。この場合、フ
リップチップ集積回路の内部回路領域にバンプと重なる
ようにメモリセルが配置されていると、製造後のフリッ
プチップ集積回路のメモリセルがソフトエラーを引き起
こしてしまう。
In such a flip-chip integrated circuit, the composition of the bump material such as solder used for the bump changes after manufacturing, and the amount of radiation such as α rays contained in the bump increases. Sometimes. In this case, if the memory cells are arranged in the internal circuit area of the flip-chip integrated circuit so as to overlap the bumps, the memory cells of the manufactured flip-chip integrated circuit cause a soft error.

【0004】従来の構成では製造後にバンプの設置場所
だけを自由に変えることができないので、α線などによ
ってメモリセルのソフトエラーが起こった場合にはこれ
を回避するために集積回路の配線レイアウトやバンプ接
続用電極の配置レイアウトを修正して集積回路を初めか
ら製造し直さなければならなかった。
In the conventional configuration, only the location of the bump cannot be freely changed after the manufacturing. Therefore, if a soft error occurs in the memory cell due to α-rays or the like, the wiring layout of the integrated circuit and the The layout of the bump connection electrodes had to be modified, and the integrated circuit had to be remanufactured from the beginning.

【0005】本発明は上記従来技術の問題点に鑑み、製
造後にメモリセルの配置位置から自由にバンプの位置を
離すことができるフリップチップ集積回路を提供するこ
とを目的とする。
The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a flip-chip integrated circuit capable of freely separating a bump position from a memory cell arrangement position after manufacturing.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に本発明は、メモリセルを含む内部回路領域を有するフ
リップチップ集積回路において、バンプ搭載側面の前記
内部回路領域に対応する部分に、バンプを配置するため
の電極を本来必要なバンプの数より多く配設しておく事
を特徴とする。
According to the present invention, there is provided a flip-chip integrated circuit having an internal circuit area including a memory cell, wherein a bump is provided on a portion corresponding to the internal circuit area on a bump mounting side surface. It is characterized in that more electrodes for arranging are arranged than the originally required number of bumps.

【0007】この構成によれば、配線レイアウトやバン
プ接続用電極の配置レイアウトを変えることなく、バン
プの設置場所だけを自由に変えることができる。これに
より、フリップチップ集積回路製造後に、バンプ材料の
組成が変化してバンプに含まれているα線などの放射線
量が増えてメモリセルのソフトエラーが起こっても、バ
ンプの位置をソフトエラーが起きない位置の電極に変え
てα線等の放射線によるメモリセルのソフトエラーを回
避することができる。
[0007] According to this configuration, it is possible to freely change only the installation location of the bump without changing the wiring layout and the layout of the bump connection electrodes. As a result, even after a flip-chip integrated circuit is manufactured, even if the composition of the bump material changes and the amount of radiation such as α-rays contained in the bump increases, and the soft error of the memory cell occurs, the soft error of the bump position occurs. It is possible to avoid a soft error of the memory cell due to radiation such as α-rays instead of an electrode at a position where no occurrence occurs.

【0008】また、上記のフリップチップ集積回路は、
バンプ搭載側面の前記内部回路領域に対応する部分にお
いて前記電極を配設するための最上層配線層の幅を均一
幅にしていることが好ましい。
[0008] Further, the above-mentioned flip-chip integrated circuit includes:
It is preferable that the width of the uppermost wiring layer for arranging the electrodes at a portion corresponding to the internal circuit region on the side surface on which the bump is mounted is made uniform.

【0009】この構成によれば、最上層配線層のレイア
ウトを電極の配置箇所に応じて変える必要がなく、バン
プの設置位置を、電極の位置変更のみにより細かく変え
ることができるようになる。
According to this structure, it is not necessary to change the layout of the uppermost wiring layer in accordance with the location of the electrodes, and it is possible to finely change the installation positions of the bumps only by changing the positions of the electrodes.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0011】図1は本発明の実施の一形態としてのフリ
ップチップ集積回路のバンプ搭載側面を示す図である。
FIG. 1 is a view showing a bump mounting side surface of a flip chip integrated circuit according to an embodiment of the present invention.

【0012】この図に示される形態のフリップチップ集
積回路1のバンプ搭載側面の最上層配線層2には、電源
用バンプ4や信号用バンプ5を接続するための電極3が
接続されている。さらに、フリップチップ集積回路1の
内部回路領域10にはメモリセル11などが存在してい
る。バンプ搭載側面の、メモリセル11を含む内部回路
領域10に対応する部分には電源を供給する最上層配線
層6が設けられており、この最上層配線層6には電源用
バンプ4を接続するための電極7が敷き詰められてい
る。そして、電極7および、最上層配線層6の電極7の
配置箇所は本来必要な電源用バンプ4の数以上に設けら
れている。
An electrode 3 for connecting a power supply bump 4 and a signal bump 5 is connected to the uppermost wiring layer 2 on the bump mounting side surface of the flip-chip integrated circuit 1 of the embodiment shown in FIG. Further, a memory cell 11 and the like exist in the internal circuit area 10 of the flip-chip integrated circuit 1. A portion corresponding to the internal circuit region 10 including the memory cell 11 on the side surface on which the bump is mounted is provided with an uppermost wiring layer 6 for supplying power, and the power supply bump 4 is connected to the uppermost wiring layer 6. Electrodes 7 are laid. The number of the electrodes 7 and the arrangement positions of the electrodes 7 on the uppermost wiring layer 6 are equal to or greater than the originally required number of power supply bumps 4.

【0013】このように最上層配線層6に電極7が本来
必要な電源用バンプ4の数以上に敷き詰められているこ
とで、最上層配線層6に接続する電源用バンプ4は任意
の位置の電極7に設置可能である。したがって、フリッ
プチップ集積回路製造後に、電源用バンプ4に使用され
る半田等から放射されるα線によってメモリセル11の
ソフトエラーが起こっても、製造後にメモリセル11か
ら離れた位置の電極7に電源用バンプ4を自由に変える
ことができ、α線によるメモリセル11のソフトエラー
をフリップチップ集積回路製造後でも回避することがで
きる。
As described above, since the electrodes 7 are spread over the uppermost wiring layer 6 more than the originally required number of power supply bumps 4, the power supply bumps 4 connected to the uppermost wiring layer 6 can be located at arbitrary positions. It can be installed on the electrode 7. Therefore, even if a soft error occurs in the memory cell 11 due to α rays emitted from the solder or the like used for the power supply bump 4 after manufacturing the flip-chip integrated circuit, the electrode 7 at a position distant from the memory cell 11 after manufacturing. The power supply bump 4 can be freely changed, and a soft error of the memory cell 11 due to α rays can be avoided even after manufacturing the flip-chip integrated circuit.

【0014】図2は本発明のその他の実施の形態として
のフリップチップ集積回路のバンプ搭載側面を示す図で
ある。
FIG. 2 is a view showing a bump mounting side surface of a flip chip integrated circuit according to another embodiment of the present invention.

【0015】本発明の他の実施の形態では、上記の実施
形態に比べ、図2に示すように、内部回路領域10に対
応する、バンプ搭載側面の最上層配線層8は、電極7が
どこでも配置できるように配線幅が均一になっている。
その他の構成は上記の同じである。
In another embodiment of the present invention, as shown in FIG. 2, the uppermost wiring layer 8 on the side surface on which the bump is mounted, corresponding to the internal circuit region 10, is different from the above-described embodiment in that the electrode 7 is provided anywhere. The wiring width is uniform so that it can be arranged.
Other configurations are the same as above.

【0016】このような形態にすれば、最上層配線層6
のレイアウトを電極7の配置箇所に応じて変える必要が
なくなるとともに、電極7の位置を細かく変えることが
できる。これにより、電源用バンプ4の設置位置も電極
7の位置変更のみにより細かく変えることができるよう
になる。よって、本形態では電極のレイアウト変更だけ
で、さらに細かく電源用バンプの位置を自由に変えるこ
とができるという効果が得られる。
With such a configuration, the uppermost wiring layer 6
It is not necessary to change the layout according to the location of the electrode 7, and the position of the electrode 7 can be finely changed. Thereby, the installation position of the power supply bump 4 can be finely changed only by changing the position of the electrode 7. Therefore, in this embodiment, the effect is obtained that the position of the power supply bump can be freely changed more finely simply by changing the layout of the electrodes.

【0017】以上の各実施形態では、バンプ搭載側面
の、メモリセルを含む内部回路領域に対応する部分に電
源用バンプのみを配置している構成を示したが、本発明
はこれに限られず、バンプ搭載側面の、メモリセルを含
む内部回路領域に対応する部分に信号用バンプと電源用
バンプのいずれか一方または両方を配置する構成にも適
用することができる。
In each of the above embodiments, the configuration is shown in which only the power supply bumps are arranged in the portions corresponding to the internal circuit regions including the memory cells on the side surfaces on which the bumps are mounted. However, the present invention is not limited to this. The present invention can also be applied to a configuration in which one or both of the signal bump and the power supply bump are arranged in a portion corresponding to the internal circuit region including the memory cell on the side surface on which the bump is mounted.

【0018】[0018]

【効果の説明】以上説明したように本発明は、フリップ
チップ集積回路におけるバンプ搭載側面の前記内部回路
領域に対応する部分に、バンプを配置するための電極を
本来必要なバンプの数より多く配設したことにより、フ
リップチップ集積回路製造後に、バンプ材料の組成が変
化してバンプに含まれているα線などの放射線量が増え
てメモリセルのソフトエラーが起こっても、製造後にバ
ンプの位置をメモリセルから離れた位置の電極に自由に
変えることができる。
As described above, according to the present invention, the number of electrodes for arranging bumps is greater than the originally required number of bumps at the portion corresponding to the internal circuit area on the side surface of the flip-chip integrated circuit where bumps are mounted. With this configuration, even after the flip-chip integrated circuit is manufactured, even if the composition of the bump material changes and the amount of radiation such as α-rays contained in the bump increases, and a soft error occurs in the memory cell, the position of the bump after manufacturing is reduced. Can be freely changed to an electrode at a position away from the memory cell.

【0019】その結果、集積回路の配線レイアウトやバ
ンプ接続用電極の配置レイアウトを修正しないで、α線
等の放射線によるメモリセルのソフトエラーをフリップ
チップ集積回路製造後でも回避することができる。
As a result, a soft error of a memory cell due to radiation such as α-rays can be avoided even after manufacturing a flip-chip integrated circuit without modifying the wiring layout of the integrated circuit or the layout of the bump connection electrodes.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の一形態としてのフリップチップ
集積回路のバンプ搭載側面を示す図である。
FIG. 1 is a diagram showing a bump mounting side surface of a flip chip integrated circuit as one embodiment of the present invention.

【図2】本発明のその他の実施の形態としてのフリップ
チップ集積回路のバンプ搭載側面を示す図である。
FIG. 2 is a diagram showing a bump mounting side surface of a flip chip integrated circuit as another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 フリップチップ集積回路 2、6、8 最上層配線層 3、7 電極 4 電源用バンプ 5 信号用バンプ DESCRIPTION OF SYMBOLS 1 Flip chip integrated circuit 2, 6, 8 Top wiring layer 3, 7 Electrode 4 Power supply bump 5 Signal bump

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 メモリセルを含む内部回路領域を有する
フリップチップ集積回路のバンプ配置方法であって、 バンプ搭載側面の前記内部回路領域に対応する部分に、
バンプを配置するための電極を本来必要なバンプの数よ
り多く配設しておく事を特徴とするバンプ配置方法。
1. A method of arranging a bump in a flip-chip integrated circuit having an internal circuit area including a memory cell, the method comprising:
A method for arranging bumps, comprising arranging more electrodes for arranging bumps than the originally required number of bumps.
【請求項2】 バンプ搭載側面の前記内部回路領域に対
応する部分において前記電極を配設するための最上層配
線層の幅を均一幅にする事を特徴とする請求項1に記載
のバンプ配置方法。
2. The bump arrangement according to claim 1, wherein the width of the uppermost wiring layer for arranging the electrodes is made uniform in a portion corresponding to the internal circuit region on the side surface on which the bump is mounted. Method.
【請求項3】 メモリセルを含む内部回路領域を有する
フリップチップ集積回路であって、 バンプ搭載側面の前記内部回路領域に対応する部分に、
バンプを配置するための電極が本来必要なバンプの数よ
り多く設けられていることを特徴とするフリップチップ
集積回路。
3. A flip-chip integrated circuit having an internal circuit area including a memory cell, wherein a portion corresponding to the internal circuit area on a side surface on which bumps are mounted is provided.
A flip-chip integrated circuit, wherein the number of electrodes for arranging bumps is greater than the originally required number of bumps.
【請求項4】 バンプ搭載側面の前記内部回路領域に対
応する部分に、前記電極を配設するための最上層配線層
が設けられていることを特徴とする請求項3に記載のフ
リップチップ集積回路。
4. The flip-chip integrated circuit according to claim 3, wherein an uppermost wiring layer for arranging the electrodes is provided in a portion corresponding to the internal circuit region on a side surface on which bumps are mounted. circuit.
【請求項5】 前記最上層配線層の幅が均一である事を
特徴とする請求項4に記載のフリップチップ集積回路。
5. The flip-chip integrated circuit according to claim 4, wherein the width of the uppermost wiring layer is uniform.
JP19754798A 1998-07-13 1998-07-13 Bump arrangement method for flip chip integrated circuit and flip chip integrated circuit Expired - Fee Related JP3147162B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19754798A JP3147162B2 (en) 1998-07-13 1998-07-13 Bump arrangement method for flip chip integrated circuit and flip chip integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19754798A JP3147162B2 (en) 1998-07-13 1998-07-13 Bump arrangement method for flip chip integrated circuit and flip chip integrated circuit

Publications (2)

Publication Number Publication Date
JP2000031188A JP2000031188A (en) 2000-01-28
JP3147162B2 true JP3147162B2 (en) 2001-03-19

Family

ID=16376307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19754798A Expired - Fee Related JP3147162B2 (en) 1998-07-13 1998-07-13 Bump arrangement method for flip chip integrated circuit and flip chip integrated circuit

Country Status (1)

Country Link
JP (1) JP3147162B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090032941A1 (en) * 2007-08-01 2009-02-05 Mclellan Neil Under Bump Routing Layer Method and Apparatus
US7906424B2 (en) 2007-08-01 2011-03-15 Advanced Micro Devices, Inc. Conductor bump method and apparatus
US8314474B2 (en) 2008-07-25 2012-11-20 Ati Technologies Ulc Under bump metallization for on-die capacitor
JP6251828B2 (en) * 2017-01-30 2017-12-20 ルネサスエレクトロニクス株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2000031188A (en) 2000-01-28

Similar Documents

Publication Publication Date Title
US20200235131A1 (en) Semiconductor device and a method of manufacturing the same
US7375433B2 (en) Semiconductor device packaging substrate and semiconductor device packaging structure
JP3353508B2 (en) Printed wiring board and electronic device using the same
US20100038117A1 (en) Tape wiring substrates and packages including the same
US20090101395A1 (en) Printed wiring board and electronic apparatus
US9460938B2 (en) Semiconductor device including a plurality of semiconductor chips, and a cover member with first and second brims
US20080128883A1 (en) High i/o semiconductor chip package and method of manufacturing the same
US6046495A (en) Semiconductor device having a tab tape and a ground layer
US20060220246A1 (en) Bump land structure of circuit substrate for semiconductor package
JPH1056093A (en) Semiconductor device and electronic device where the semiconductor device is incorporated
CN101615605B (en) Semiconductor integrated circuit
JP3147162B2 (en) Bump arrangement method for flip chip integrated circuit and flip chip integrated circuit
US20060284310A1 (en) Offset via on pad
JPH11177225A (en) Printed board
TW202105665A (en) Semiconductor package
JPS58157147A (en) Hybrid integrated circuit substrate
US6940166B2 (en) Semiconductor device and method for designing the same
US20230395482A1 (en) Semiconductor package
US8089164B2 (en) Substrate having optional circuits and structure of flip chip bonding
US20050077081A1 (en) Robust high density substrate design for thermal cycling reliability
JP2004172604A (en) Semiconductor integrated circuit device
JP2004319692A (en) Electronic circuit board
JPH09283703A (en) Composite semiconductor device
JPH10126021A (en) Hybrid integrated circuit device
JPH06163693A (en) Method for wiring and designing semiconductor integrated circuit device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees