JP3132459B2 - Direct conversion receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct conversion receiver, and more particularly to a direct conversion receiver used in a portable telephone or other wireless terminal device and known as a zero intermediate frequency (IF) receiver.

[0002]

2. Description of the Related Art In recent years, with the spread of portable telephones and other wireless portable terminals, demands for downsizing, lower power consumption, and lower prices of wireless devices have been increasing. As one of the wireless reception systems that fulfills such demands, a direct conversion system has been receiving attention.

FIG. 9 shows a block diagram of a typical direct conversion receiver of this kind. Referring to FIG. 9, a high-frequency signal is input to quadrature mixers 73a and 73b via an antenna 71 and a high-frequency amplifier 72, respectively.
Then, the signal is multiplied by the local oscillation frequency of the local oscillator 74 in the mixer 73a, and is multiplied by the quadrature component of the local oscillation frequency in the mixer 73b, and is output as an I component and a Q component. The quadrature component of the local oscillation frequency of the local oscillator 74 is generated by the 90-degree phase shifter 75. In this case, each output signal of the mixers 73a and 73b is composed of a sum component of the input carrier frequency and the local oscillation frequency, and a difference component centered on the zero frequency (in the case of ± representation of spectrum). Then, only the difference component around the zero frequency (hereinafter, the zero frequency component) is extracted by the LPFs 76a and 76b. The extracted zero frequency component is further subjected to signal processing by baseband (baseband) amplifiers 77a and 77b and demodulated.

[0004] In the above-mentioned direct conversion method, an input frequency is directly converted to a baseband frequency. This corresponds to the case where the intermediate frequency in the superheterodyne method is zero. As a result, since there is no image frequency response, a high-frequency filter is not required in principle. Also, since the baseband signal is folded at zero frequency, the channel filter may be an LPF type. Therefore, the BP using the superheterodyne method is used.
IC integration is easier than an F-type channel filter.
That is, the direct conversion method is considered to be a circuit suitable for a one-chip receiver because it has few external components and is easy to be integrated into an LSI as compared with the superheterodyne method. .

[0005]

However, in order to use a direct conversion receiver in a wireless system such as a cellular phone, generally, a mixer requires several mV to several tens mV.
It is necessary to remove the DC offset voltage existing in the order of 1), which has conventionally been the biggest problem in practical use. That is, PDC (Domestic Digital Mobile Phone) and PHS
(Simplified mobile phone) In order to obtain the required reception sensitivity in the system, the amplification of the baseband amplifiers 77a and 77b needs to be very high, for example, several tens of dB. The baseband amplifier was saturated by the presence of the DC offset voltage generated in the mixer, and the function as a receiver could not be obtained.

As a method for removing the DC offset voltage, as shown in FIG. 10, it is conceivable to use DC cut capacitors 78a and 78b immediately after the mixers 73a and 73b. However, in this method, the zero frequency component of the signal information is also cut off at the same time, so that it can be used only for the FSK modulation method used in, for example, a pager system. In addition, a portable wireless device such as a pager needs to have an intermittent reception function in order to prolong the battery life, but in order to provide this function, an additional circuit for shortening the charge / discharge time of the capacitor is generally required. However, there is a drawback that the circuit scale is increased because of the necessity.

As another conventional technique for removing a DC offset voltage, Japanese Patent Laid-Open Publication No.
There is a technique disclosed in Japanese Patent No. 220823 “direct conversion receiver”. This publication describes a method of removing a DC offset voltage by a negative feedback loop using AD and DA converters as shown in FIG. In the block diagram of FIG. 11, the same components as those in the block diagram of FIG. 9 are denoted by the same reference numerals.

The direct conversion receiver shown in FIG. 11 is a closed-loop control unit that extracts a DC offset voltage from output signals of baseband amplifiers 77a and 77b using AD converters 81a and 81b, and based on the extraction result. The DC voltage offset is suppressed using the data processing circuit 82 and the DA converters 83a and 83b.

According to this method, since the zero frequency component of the signal information is not cut, it can be applied to π / 4 QPSK modulation used in PDC and PHS systems. However, since the related art uses a closed loop, it has little effect on a temporally fast offset voltage fluctuation due to restrictions such as a loop convergence time. That is, when control is performed so that the average value of the offset voltage becomes zero for a long time of, for example, about 1 second, an effect can be expected to some extent, but the speed of the slot time in the digital mobile phone system (for example, 0.6 for PHS
There was not much effect on the offset voltage fluctuation which changes in about 25 msec). Further, an AD converter and D
Since the A converter is used, there is a disadvantage that the circuit scale is increased.

An object of the present invention is to provide a direct conversion receiver with an offset voltage canceling circuit capable of solving the above-mentioned conventional disadvantages and capable of erasing a small offset voltage at high speed.

Another object of the present invention is to provide, in addition to the above objects,
An object of the present invention is to provide a direct conversion receiver suitable for mobile phones and other portable wireless terminal devices while avoiding an increase in circuit scale.

[0012]

A direct conversion receiver according to the present invention, which achieves the above object, comprises a frequency mixing means for mixing a received high-frequency signal and a local oscillation signal, and an output signal from the frequency mixing means. A signal conversion unit that converts the signal into a baseband signal, an offset voltage detection unit that detects an offset voltage from an output signal of the signal conversion unit, and an offset voltage that is detected by the offset voltage detection unit. An offset canceling means for outputting an offset canceling voltage for canceling the offset voltage in the output signal; and a specific period based on a predetermined rule, supplying an output signal of the frequency mixing means to the offset voltage detecting means, and During the period other than the above, the offset output from the offset erasing means is output. The door cancel voltage and a switch means for supplying the output of said frequency mixing means.

According to a second aspect of the present invention, when the direct conversion receiver of the present invention is applied to a time-division communication system, the switch means operates the frequency converter during a period other than the time slot allocated to the own receiver. The output signal of the mixing means is supplied to the offset voltage detecting means, and the offset cancel voltage output from the offset erasing means is supplied to the output of the frequency mixing means during a time slot allocated to the own receiver. The connection is switched as described above.

According to a third aspect of the present invention, in the direct conversion receiver according to the present invention, when applied to a frequency division communication system, the switch means operates during a period corresponding to a pilot signal portion of a received frame. Supplying the output signal of the frequency mixing means to the offset voltage detection means, and switching the connection so as to supply the offset cancellation voltage output from the offset elimination means to the output of the frequency mixing means during the other period. Features.

According to a fourth aspect of the present invention, there is provided a direct conversion receiver according to the present invention, wherein the offset voltage detecting means inputs the output of the frequency mixing means and performs delta sigma modulation, and the delta sigma modulation means uses the delta sigma modulation means. Averaging means for averaging the sigma modulated output signal.

According to a fifth aspect of the present invention, there is provided a direct conversion receiver, wherein the delta-sigma modulation means is a first-order or second-order or higher-order delta-sigma modulator. The delta-sigma modulator is a MASH-type delta-sigma modulator.

According to a seventh aspect of the present invention, in the direct conversion receiver of the present invention, the offset canceling means inverts the offset voltage detected by the offset voltage detecting means to obtain an offset canceling voltage, and obtains the obtained offset canceling voltage. It is characterized by holding.

In a direct conversion receiver according to the present invention, one or two or more baseband amplifiers are interposed between the frequency mixing means and the signal conversion means, and the rearmost baseband amplifier is provided. For an output of an arbitrary baseband amplifier located before the amplifier, a connection to the switch means for extracting an output signal to be supplied to the offset voltage detecting means and supplying the offset cancel voltage is provided. It is characterized by being done.

According to a ninth aspect of the present invention, there is provided a direct conversion receiver according to the present invention, comprising: frequency mixing means for frequency-mixing a received high-frequency signal and a local oscillation signal; and converting an output signal of the frequency mixing means into a baseband signal. Signal converting means, offset voltage detecting means for detecting an offset voltage from an output signal of the signal converting means, and the offset voltage in the output signal of the frequency mixing means in accordance with the offset voltage detected by the offset voltage detecting means. And an offset canceling unit that outputs an offset canceling voltage for canceling the offset, and superimposes the offset canceling voltage on the output signal of the frequency mixing unit, and supplies the output signal of the offset voltage detecting unit to the offset canceling unit during a specific period based on a predetermined rule. Is shut off, and during a period other than the specified period, the offset The output signal of the detecting means, characterized in that it comprises a switching means for supplying to said offset canceling means.

When the direct conversion receiver of the present invention is applied to a communication system of a time division system, the switch means sets the offset voltage during a period other than the time slot allocated to the own receiver. The supply of the output signal of the detection means to the offset elimination means is interrupted, and the output signal of the offset voltage detection means is supplied to the offset elimination means during a time slot assigned to the own receiver. I do.

According to the eleventh aspect of the present invention, when the direct conversion receiver of the present invention is applied to a communication system of a frequency division system, the switch means operates during a period corresponding to a pilot signal portion of a received frame. The supply of the output signal of the offset voltage detecting means to the offset erasing means is interrupted, and the output signal of the offset voltage detecting means is supplied to the offset erasing means during other periods.

Further, a direct conversion receiver according to the present invention is characterized in that a frequency conversion means for mixing the frequency of a received high-frequency signal and a local oscillation signal to convert the mixed signal into a baseband signal, and a specification based on a predetermined rule. In the period, the offset voltage detecting means for detecting an offset voltage from the output signal of the frequency converting means, and a period other than the specific period, according to the offset voltage detected by the offset voltage detecting means, the frequency converting means And an offset erasing means for canceling the offset voltage in the output signal.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the direct conversion receiver according to the first embodiment of the present invention. In the following description, P
The time division multiplexing method (Ti
me Division Multiplex Acc
(ESS: TDMA system) will be described as an example.

Referring to FIG. 1, in the direct conversion receiver of this embodiment, an RF (high frequency) signal received by an antenna 11 is orthogonally transformed by mixers 13a and 13b via a high frequency amplifier 12.
For this purpose, a local oscillator 14 and a 90-degree phase shifter 15 are provided, and the local oscillation frequency and its orthogonal component are supplied to the mixers 13a and 13b, respectively. The output signals of the mixers 13a and 13b are input to and processed by the offset voltage canceling circuits 100a and 100b, respectively. FIG. 1 shows a specific example only of the offset voltage canceling circuit 100a for the I component output from the mixer 13a.
Since the functions are the same as those of the offset voltage canceling circuit 100a, they are not shown and the description is omitted. In FIG. 1, only the characteristic configuration of the present embodiment is described, and the description of other general configurations is omitted.

The output signal of the mixer 13a is split into two, one of which is input to the signal processing unit 18 via the LPF 16 and the baseband amplifier 17, and is subjected to baseband signal processing. The other is input to the offset cancel voltage generating circuit 200 via the contact “n” of the switch 20. The offset cancel voltage generation circuit 200 includes a delta-sigma modulator 210 for detecting an offset voltage, an inverter 230 for inverting a modulation output signal from the delta-sigma modulator 210, and an averaging circuit for averaging the output signal of the inverter 230. 240, and a hold circuit 220 for holding the output signal of the averaging circuit 240. The output signal of the hold circuit 220 is supplied to the output of the mixer 13a via the contact "m" of the switch 20.
The switching of the switch 20 is controlled by the switching controller 19.

The branch output of the mixer 13a input to the delta-sigma modulator 210 is applied to the in-phase input of a subtractor 211, and the subtracted output of the subtracter 211 is passed through an integrator 212 to a 1-bit quantizer 213. Supplied to The output signal of the one-bit quantizer 213 is applied to the negative-phase input of the subtracter 211 via the one-sample delay 214.

The switching control of the switch 20 by the switching controller 19 is performed as follows. As described above, since the present embodiment is a TDMA system, refer to one example of a TDMA slot configuration (an example of a PHS system) shown in FIG.
For example, the terminal No. Considering the case of 2 (indicated by R2), during the period of the receiving slot 21, the high-frequency amplifier 12 is activated and in the data receiving state, and the switch 20 is connected to the contact "m". During a period 23 from the end of the reception slot 21 to the start of the reception slot 22 of the next frame, the high-frequency amplifier 12 is in the inactive sleep state, and the switch 20 is connected to the contact “n”. .

In FIG. 2, periods 21 and 22 are offset voltage cancel periods, and period 23 is an offset voltage detection period. The delta-sigma modulator 210 is used for detecting the offset voltage during the offset voltage detection period. The principle of operation is, for example,
Document "Journal of the Institute of Electronics, Information and Communication Engineers" No. 72, published in February
Vol. 12 pp. 1422-1429. According to the document, the delta-sigma modulator 210
Modulates an input signal into a 1-bit oversampling frequency signal sequence having a value of “+ a” or “−a” (“a” is a constant). Therefore, after passing through the delta-sigma modulator 210, the offset voltage appearing at the mixer output in the period 23 has a positive or negative value “±
This is converted into a 1-bit digital signal of a ″.
The digital signal is further sign-inverted by the inverter 230 and averaged by the averaging circuit 240. Thus, a value obtained by inverting the sign of the DC offset voltage of the mixer 13a in the period 23 can be obtained. This value is held in the hold circuit 220 including the buffer 221 and the capacitor 222. Next, in the period 22, the DC offset voltage of the mixer 13a is canceled by the inverted value of the hold circuit 220 via the switch 20. Therefore, the offset voltage is removed during data reception.

As is clear from the above description, in the offset voltage canceling circuit 100 of the present embodiment, since the offset canceling voltage generating circuit 200 and the switch 20 form a single open loop, the canceling operation is performed in comparison with the closed loop. And fast. Therefore, for example, the offset canceling operation can be performed in the immediate vicinity of the reception slot as at the point "A" shown in FIG. As a result, even when the offset voltage fluctuates on the order of the slot time, the cancel operation can be performed finely, so that deterioration of the reception characteristics can be suppressed to a minimum.

In the above description, the case where the offset voltage value is constant is considered. However, when the offset voltage fluctuates with time, an inverted output signal of the average value of the fluctuating voltage is output from the contact "m" of the switch 20. ".

Although the case of the TDMA system has been described with reference to FIG. 2, the FD receiving signals continuously in time is used.
MA (Frequency Division Mul
In the case of a direct conversion receiver of the "Tip Access" type, the same effect as in the case of the TDMA system can be realized by setting the minimum non-reception state necessary for offset voltage detection for offset cancellation. . This non-reception state is obtained, for example, by turning off the high-frequency amplifier 12. FIG.
An example of a radio frame of the FDMA scheme is shown. 3, the timing for turning off the high-frequency amplifier 12 is shown in FIG.
Of the received frame shown in "B" of FIG.
It is sufficient to select a certain period of time ot). That is, the switch 20 is controlled to the contact “n” side only during the selected period, and the switch 20 is set to the contact “m” side during other periods to cancel the offset voltage. Further, the timing for turning off the high-frequency amplifier 12 does not necessarily need to be performed for all pilot signals, and the timing for turning off the high-frequency amplifier 12 may be selected intermittently.

Generally, to detect a voltage of about several mV corresponding to the offset voltage of a mixer, for example, assuming that the full scale of the AD converter is 1 V, 10 bits (60 bits)
An AD converter having a resolution of dB or more is required. However, in the example of FIG. 1, if the value of “a” in the modulation processing by the delta-sigma modulator 210 is set to, for example, 100 mV, an AD converter having a resolution of 40 dB, that is, about 7 bits is sufficient. . Here, the S / N ratio (signal to noise) of the first-order delta-sigma modulator
eratio) is represented by S / N = (9π / 2) · {fs / (2π · fb)} 3. Note that fs is a sampling frequency and fb is a signal band. Therefore, a resolution of S / N = 40 dB can be easily obtained by using the first-order delta-sigma modulator 210 shown in FIG.

The offset cancel voltage generating circuit 200 shown in FIG.
0, but a second-order or higher delta-sigma modulator or M
ASH (Multi Stage Noise Sha
If a ping-type delta-sigma modulator is used, although the circuit becomes complicated, it is possible to remove a smaller offset voltage and to operate at a higher speed.

FIG. 4 shows an example of the configuration of a second-order delta-sigma modulator. The circuit configuration of the illustrated delta-sigma modulator is disclosed in the above-mentioned document “Journal of the Institute of Electronics, Information and Communication Engineers”. FIG.
, The second-order delta-sigma modulator includes subtractors 41 and 43, integrators 42 and 44, a one-bit quantizer 45, and a one-sample delay unit 46. The input signal is applied to the positive-phase input of the subtractor 41, the output signal of the subtractor 41 is applied to the positive-phase input of the subtractor 43 via the integrator 42, and the output signal of the subtracter 43 is supplied to the integrator 44. It is input to a 1-bit quantizer 45. The output signal of the one-bit quantizer 45 is applied to the negative phase inputs of the subtracters 41 and 43 after being delayed by the one-sample delay unit 46.

FIG. 5 shows a configuration example of a three-stage MASH type delta-sigma modulator. The circuit configuration of the illustrated delta-sigma modulator is disclosed in the above-mentioned document “Journal of the Institute of Electronics, Information and Communication Engineers”. Referring to FIG. 5, the MASH type AD converter includes subtractors 51, 54, 55, 59, 60, integrators, 52, 56, 61, and 1-bit quantizers 53, 57, 6,.
2, a differentiator 58, 63, 64, and an adder 65. The input signal is applied to the in-phase input of the subtractor 51, and is input to the 1-bit quantizer 53 via the integrator 52. The output signal of the integrator 52 is applied to the in-phase input of the subtractor 54. The output signal of the 1-bit quantizer 53 is output to a subtracter 51,
The signal is supplied to an adder 65 while being applied to the negative-phase input of 54. The output signal of the subtractor 54 is applied to the in-phase input of a subtractor 55, and is input to a 1-bit quantizer 57 via an integrator 56. The output signal of the integrator 56 is applied to the in-phase input of the subtractor 59. The output signal of the 1-bit quantizer 57 is applied to the negative-phase inputs of the subtracters 55 and 59, and is also supplied to the adder 65 via the differentiator 58. The output signal of the subtractor 59 is applied to the in-phase input of the subtractor 60, and is input to the 1-bit quantizer 62 via the integrator 61. The output signal of the 1-bit quantizer 62 is applied to the negative-phase input of the subtractor 60 and is supplied to an adder 65 via differentiators 63 and 64 provided in series.

FIG. 6 is a block diagram showing a configuration of a direct conversion receiver according to a second embodiment of the present invention. Referring to FIG. 6, the direct conversion receiver of the present embodiment is shown in FIG. 1 except that the output signals of the mixers 13a and 13b are provided over two stages for inputting and processing the output signals and outputting the processed signals to the signal processing unit 18. The configuration is the same as that of the first embodiment. 6, the same components as those shown in FIG. 1 are denoted by the same reference numerals. In FIG. 6, only the characteristic configuration of the present embodiment is described, and the description of other general configurations is omitted.

In the present embodiment, as shown in FIG.
The offset detection is not performed directly from the output signals a and 13b, but is once performed by the LPF 21 and the baseband amplifier 22 to detect the offset from the output signal of the baseband amplifier 22. For this purpose, a second-stage LPF 23 and a baseband amplifier 24 for processing the output signal of the baseband amplifier 21 are provided, and the output signal of the baseband amplifier 21 is connected to the switch 20. The combination of the LPF and the baseband amplifier may be provided in three or more stages, and the detection and erasure of the offset voltage may be performed in any stage.

FIG. 7 is a block diagram showing a configuration of a direct conversion receiver according to a third embodiment of the present invention. Referring to FIG. 7, in the direct conversion receiver of the present embodiment, the output signal of the mixer 3a is
It is split into two, and one is supplied to the adder 400 as it is. The other output signal is input to offset cancel voltage generation circuit 200.

Offset cancel voltage generating circuit 200
Is a delta-sigma modulator 21 for detecting an offset voltage.
0, an inverter 230 for inverting the output signal modulated by the delta-sigma modulator 210, an averaging circuit 240 for averaging the output signal of the inverter 230, and a hold circuit 220 for holding the output signal of the averaging circuit 240.
And an output signal of the inverter 230 to the averaging circuit 240
Switch 250 for controlling whether or not to transmit to
And

The transmission switch 250 is connected to the transmission controller 300
To transmit or disconnect the output signal of the inverter 230. The transmission controller 300 controls the transmission switch 250 as follows. That is, during the reception slot 21 shown in FIG. 2, the high-frequency amplifier 12 is activated and is in the data receiving state, and the transmission control switch 250 is connected to the inverter 230 and the averaging circuit 2.
The connection to the connection 40 is cut (OFF). In a period 23 from the end of the reception slot 21 to the start of the reception slot 22 of the next frame, the transmission control switch 250 switches the inverter 230 and the averaging circuit 24
0 is connected (ON). FIG. 8 shows the above relationship.

In FIG. 8, periods 21 and 22 are offset voltage cancel periods, and period 23 is an offset voltage detection period. The detection of the offset voltage in the offset voltage detection period is performed in the same manner as in the first embodiment shown in FIG. Therefore, the relevant periods 21 and 22
In the hold circuit 220, the mixers 3a, 3b
, An offset cancel voltage having a polarity opposite to that of the offset voltage is output. In addition, in the reception slots in the periods 21 and 22, the transmission switch 250 is turned off as described above.
Since the FF is set, the offset cancel voltage detected immediately before the reception slot is applied to the adder 400. Therefore, in the output signal of the adder 400, the offset voltage is canceled and only the baseband signal is obtained.

As can be seen from the above description, it is clear that the offset voltage canceling circuit 100a shown in FIG. 7 also forms an open loop.

In the above description, the case of the TDMA system has been described. However, as in the other embodiments described above, the present invention can be applied to the FDMA system. Further, the configuration of the delta-sigma modulator 210 shown in FIG.
If necessary, a multi-order delta-sigma modulator as shown in FIG. 4 or a MASH-type delta-sigma modulator as shown in FIG. 5 can be used.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0045]

As described above, according to the direct conversion receiver of the present invention, since a single loop for offset cancellation of a mixer forms an open loop, the single loop is closed as in the prior art. This has an effect that the speed of the cancel operation can be further increased as compared with the case of

According to the present invention, a small offset voltage can be detected with a simple configuration, so that the size and cost of a direct conversion receiver can be reduced, and a portable telephone and other portable radios can be achieved. It is suitable for a terminal device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a direct conversion receiver according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a frame configuration example of a TDMA system.

FIG. 3 is a diagram illustrating a frame configuration example of the FDMA scheme.

FIG. 4 is a block diagram illustrating a configuration example of a second-order delta-sigma modulator.

FIG. 5 is a block diagram illustrating a configuration example of a three-stage MASH-type delta-sigma modulator.

FIG. 6 is a block diagram illustrating a configuration of a direct conversion receiver according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a direct conversion receiver according to a third embodiment of the present invention.

FIG. 8 is a TD for explaining the operation in the embodiment of FIG.
FIG. 3 is a diagram illustrating an example of a frame configuration of an MA system.

FIG. 9 is a block diagram showing a configuration of a conventional direct conversion receiver.

FIG. 10 is a block diagram showing another configuration of a conventional direct conversion receiver.

FIG. 11 is a block diagram showing still another example of the configuration of a conventional direct conversion receiver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Antenna 12 High frequency amplifier 13a, 13b Mixer 14 Local oscillator 15 90 degree phase shifter 16 LPF (channel filter) 17 Base band amplifier 18 Signal processing part 19 Switching controller 20 Switch 100a, 100b Offset voltage cancel circuit 200 Offset cancel voltage generation circuit 210 Delta-sigma modulator 211 Subtractor 212 Integrator 213 1-bit quantizer 214 1-sample delay 220 Hold circuit 221 Buffer 222 Capacitor 230 Inverter 240 Averaging circuit

Claims (17)

(57) [Claims] 1. A frequency mixing means for frequency-mixing a received high-frequency signal and a local oscillation signal, a signal conversion means for converting an output signal from the frequency mixing means into a baseband signal, and an output signal of the signal conversion means An offset voltage detecting means for detecting an offset voltage from, and an offset erasing means for outputting an offset cancel voltage for canceling the offset voltage in an output signal of the frequency mixing means in accordance with the offset voltage detected by the offset voltage detecting means. In a specific period based on a predetermined rule, an output signal of the frequency mixing unit is supplied to the offset voltage detecting unit, and in a period other than the specific period, the offset cancel voltage output from the offset erasing unit is output. Switch means for supplying the output of the frequency mixing means. Direct conversion receiver, characterized in that to obtain. 2. When applied to a time-division communication system, the switch means transmits an output signal of the frequency mixing means to the offset voltage detection means during a period other than a time slot assigned to the own receiver. The connection is switched so as to supply the offset cancel voltage output from the offset canceling means to the output of the frequency mixing means during a time slot supplied and assigned to the own receiver. 2. The direct conversion receiver according to 1. 3. When applied to a frequency division communication system, the switching means detects the offset signal from the frequency mixing means during the period corresponding to the pilot signal portion of the received frame. 2. The direct connection according to claim 1, wherein the connection is switched so as to supply the offset cancel voltage output from the offset canceling means to the output of the frequency mixing means during other periods. Conversion receiver. 4. The delta-sigma modulation means for inputting the output of the frequency mixing means and performing delta-sigma modulation, and the averaging means for averaging the delta-sigma modulation output signal by the delta-sigma modulation means. The direct conversion receiver according to any one of claims 1 to 3, further comprising: 5. The direct conversion receiver according to claim 4, wherein said delta-sigma modulation means is a first-order or second-order or higher-order delta-sigma modulator. 6. The delta-sigma modulation means includes a MASH
5. A direct conversion receiver according to claim 4, wherein the receiver is a delta-sigma modulator of the type. 7. The offset erasing means, wherein the offset voltage detected by the offset voltage detecting means is inverted to obtain an offset cancel voltage, and the obtained offset cancel voltage is held. A direct conversion receiver according to claim 6. 8. An arbitrary baseband located at a stage preceding the most recent baseband amplifier by interposing one or more stages of a baseband amplifier between the frequency mixing unit and the signal conversion unit. 2. An output of an amplifier is connected to the switch means for extracting an output signal to be supplied to the offset voltage detecting means and supplying the offset cancel voltage. A direct conversion receiver according to claim 7. 9. A frequency mixing means for frequency-mixing a received high-frequency signal and a local oscillation signal, a signal conversion means for converting an output signal from the frequency mixing means into a baseband signal, and an output signal of the signal conversion means. An offset voltage detecting means for detecting an offset voltage from the output signal, and an offset cancel voltage for canceling the offset voltage in an output signal of the frequency mixing means in accordance with the offset voltage detected by the offset voltage detecting means. Offset elimination means to be superimposed on the output signal of the means, and for a specific period based on a predetermined rule, supply of the output signal of the offset voltage detection means to the offset elimination means is cut off, and during a period other than the specific period Supplying the output signal of the offset voltage detecting means to the offset erasing means. Direct conversion receiver comprising: a switch means that. 10. When applied to a time-division communication system, the switch means transmits the output signal of the offset voltage detection means to the offset cancellation means during a period other than the time slot allocated to the own receiver. And supplying the output signal of the offset voltage detecting means to the offset erasing means during a time slot allocated to the own receiver. Machine. 11. When applied to a communication system of a frequency division system, the switch means controls the offset canceling means of the output signal of the offset voltage detecting means during a period corresponding to a pilot signal portion of a received frame. 10. The direct conversion receiver according to claim 9, wherein supply to the offset conversion unit is interrupted, and an output signal of the offset voltage detection unit is supplied to the offset elimination unit during other periods. 12. The delta-sigma modulation means for inputting the output of the frequency mixing means and performing delta-sigma modulation, and the averaging means for averaging the delta-sigma modulation output signal by the delta-sigma modulation means. The direct conversion receiver according to any one of claims 9 to 11, wherein the delta-sigma modulation means is a first-order or second-order or higher-order delta-sigma modulator. 13. The delta-sigma modulation means for inputting the output of the frequency mixing means and performing delta-sigma modulation, and the averaging means for averaging the delta-sigma modulation output signal by the delta-sigma modulation means. The direct conversion receiver according to claim 9, wherein the delta-sigma modulation means is a MASH-type delta-sigma modulator. 14. A frequency conversion means for mixing a received high-frequency signal and a local oscillation signal into a baseband signal by frequency mixing, and for a specific period based on a predetermined rule, an offset voltage from an output signal of said frequency conversion means. An offset voltage detecting means for detecting, and an offset erasing means for canceling the offset voltage in the output signal of the frequency converting means according to the offset voltage detected by the offset voltage detecting means during a period other than the specific period. A direct conversion receiver characterized in that: 15. When applied to a time-division communication system, during a time period other than the time slot allocated to the own receiver,
The offset voltage detecting means detects an offset voltage, and the offset canceling means supplies the offset canceling voltage to an output of the frequency converting means during a time slot allocated to the own receiver. Item 15. A direct conversion receiver according to item 14. 16. When applied to a frequency division communication system, the offset voltage detecting means detects an offset voltage in a period corresponding to a pilot signal portion of a received frame, and in other periods, 15. The direct conversion receiver according to claim 14, wherein the offset cancel voltage output from the offset canceling unit is supplied to an output of the frequency converting unit. 17. The offset voltage detecting means extracts an output signal of the frequency converting means via one or more baseband amplifiers and detects an offset voltage of the obtained output signal. 17. The direct conversion receiver according to claim 14, wherein: