JP3130357B2 - Inverting type switching regulator control IC - Google Patents
Inverting type switching regulator control ICInfo
- Publication number
- JP3130357B2 JP3130357B2 JP04003180A JP318092A JP3130357B2 JP 3130357 B2 JP3130357 B2 JP 3130357B2 JP 04003180 A JP04003180 A JP 04003180A JP 318092 A JP318092 A JP 318092A JP 3130357 B2 JP3130357 B2 JP 3130357B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- power supply
- output
- switching regulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、反転型スイッチングレ
ギュレータの改良に関するものであり、特にスイッチン
グレギュレータの制御用ＩＣに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an inverting type switching regulator, and more particularly to an IC for controlling a switching regulator.
【０００２】[0002]
【従来の技術】従来の反転型スイッチングレギュレータ
の回路図を図２に示す。これはチョッパ型スイッチング
レギュレータとして広く知られているものである。正電
源入力端子１と接地間に入力された電圧は、スイッチン
グトランジスタ２とインダクタ３とダイオード４によ
り、極性が反転された負電圧として、出力電圧端子５に
出力される。この出力電圧端子５に出力される電圧値を
一定に制御する回路が、誤差増幅器６と基準電圧回路７
と発振回路８とＮＡＮＤ回路９とブリーダ抵抗１０と１
１である。出力電圧端子５に出力される電圧ＶOUT は式
（１）で表わされる。2. Description of the Related Art FIG. 2 shows a circuit diagram of a conventional inverting type switching regulator. This is widely known as a chopper type switching regulator. The voltage input between the positive power supply input terminal 1 and the ground is output to the output voltage terminal 5 as a negative voltage whose polarity is inverted by the switching transistor 2, the inductor 3 and the diode 4. A circuit for controlling the voltage value output to the output voltage terminal 5 to be constant includes an error amplifier 6 and a reference voltage circuit 7.
Oscillating circuit 8, NAND circuit 9, bleeder resistors 10 and 1
It is one. The voltage V OUT output to the output voltage terminal 5 is expressed by equation (1).
【０００３】 ＶOUT ＝−（Ｒ1 ＋Ｒ2 ）／Ｒ1 ×Ｖref （１） ここで、Ｒ1 は抵抗１０の抵抗値、Ｒ2 は抵抗１１の抵
抗値、Ｖref は基準電圧回路の出力電圧である。誤差増
幅器６と基準電圧回路７と発振回路８とＮＡＮＤ回路９
とブリーダ抵抗１０と１１は、モノリシックＩＣ化さ
れ、一般にスイッチングレギュレータの制御用ＩＣとし
て提供されている。V OUT = − (R 1 + R 2 ) / R 1 × V ref (1) where R 1 is the resistance value of the resistor 10, R 2 is the resistance value of the resistor 11, and V ref is the resistance value of the reference voltage circuit. Output voltage. Error amplifier 6, reference voltage circuit 7, oscillation circuit 8, and NAND circuit 9
The bleeder resistors 10 and 11 are made into a monolithic IC, and are generally provided as an IC for controlling a switching regulator.
【０００４】[0004]
【発明が解決しようとする課題】スイッチングレギュレ
ータの制御用ＩＣ内の誤差増幅６と基準電圧回路７と発
振回路８とＮＡＮＤ回路９は、正電源を正電源入力端子
１に印加される電圧とし、負電源を出力電圧端子５に出
力される電圧として駆動される。この駆動法はブートス
トラップ駆動と呼ばれ、スイッチングレギュレータの効
率を上げるための一手法である。しかし、ここで問題と
なるのは、制御用ＩＣの消費電流であり、これは無効電
流としてスイッチングレギュレータの効率を下げる要因
となっている。The error amplifier 6, the reference voltage circuit 7, the oscillation circuit 8 and the NAND circuit 9 in the control IC of the switching regulator use the positive power supply as the voltage applied to the positive power supply input terminal 1, The negative power supply is driven as a voltage output to the output voltage terminal 5. This driving method is called bootstrap driving and is one method for increasing the efficiency of the switching regulator. However, a problem here is the current consumption of the control IC, which is a reactive current and reduces the efficiency of the switching regulator.
【０００５】前述したように、各回路は正電源入力端子
１と出力電圧端子５の間の電圧によって駆動されるた
め、非常に大きな電圧が各回路に印加され、消費電流の
増大を引き起こしている。とりわけ発振回路の消費電流
は、印加電圧と発振周波数に比例するため、制御用ＩＣ
の消費電流の９０％以上を占めている。As described above, since each circuit is driven by the voltage between the positive power supply input terminal 1 and the output voltage terminal 5, a very large voltage is applied to each circuit, causing an increase in current consumption. . In particular, since the current consumption of the oscillation circuit is proportional to the applied voltage and the oscillation frequency, the control IC
Account for 90% or more of the current consumption.
【０００６】[0006]
【課題を解決するための手段】本発明は従来の技術の課
題を解決することを目的とし、低消費電流な反転型スイ
ッチングレギュレータの制御用ＩＣを実現した。具体的
には、発振回路を正電源入力端子１と接地間に印加され
る電圧で駆動するものである。SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and has realized a low current consumption control IC for an inverting switching regulator. Specifically, the oscillation circuit is driven by a voltage applied between the positive power supply input terminal 1 and the ground.
【０００７】[0007]
【作用】本発明の反転型スイッチングレギュレータは、
図１に示すように発振回路８の電源電圧を正電源入力端
子１と接地間に印加される電圧にすることにより、発振
回路に印加される電圧を下げることができ、印加電圧に
比例する消費電流を低減することができる。The function of the inverting switching regulator of the present invention is as follows.
By setting the power supply voltage of the oscillation circuit 8 to a voltage applied between the positive power supply input terminal 1 and the ground as shown in FIG. 1, the voltage applied to the oscillation circuit can be reduced, and the consumption proportional to the applied voltage can be reduced. The current can be reduced.
【０００８】[0008]
【実施例】本発明の反転型スイッチングレギュレータの
回路図を図１に示す。正電源１１は正電源入力端子１と
接地間に接続され、正電源入力端子１とスイッチングト
ランジスタ２のソースが接続され、そのドレインは、ダ
イオード４のカソードとインダクタ３の一端に接続され
ている。ダイオード４のアノードは出力電圧端子５と接
続され、出力電圧端子５には、接地間にブリーダ抵抗１
０と１１及びコンデンサ１２が接続されている。誤差増
幅器６の正入力端子には、ブリーダ抵抗１０と１１の接
続点が接続され、負入力端子には基準電圧回路７が接続
されている。誤差増幅器の出力端子はＮＡＮＤ回路９の
一方の入力端子に接続され、他方の入力端子は発振回路
８に接続されている。またＮＡＮＤ回路９の出力端子
は、スイッチングトランジスタ２のゲートに接続されて
いる。さらに、誤差増幅器６と基準電圧回路７とＮＡＮ
Ｄ回路９の正電源は、正電源入力端子１に接続され、負
電源は出力電圧端子５に接続され、電力の供給を受け
る。1 is a circuit diagram of an inverting switching regulator according to the present invention. The positive power supply 11 is connected between the positive power supply input terminal 1 and the ground, the positive power supply input terminal 1 is connected to the source of the switching transistor 2, and the drain is connected to the cathode of the diode 4 and one end of the inductor 3. The anode of the diode 4 is connected to the output voltage terminal 5, and the output voltage terminal 5 has a bleeder resistor 1 between the ground.
0 and 11 and a capacitor 12 are connected. The connection point between the bleeder resistors 10 and 11 is connected to the positive input terminal of the error amplifier 6, and the reference voltage circuit 7 is connected to the negative input terminal. The output terminal of the error amplifier is connected to one input terminal of the NAND circuit 9 and the other input terminal is connected to the oscillation circuit 8. The output terminal of the NAND circuit 9 is connected to the gate of the switching transistor 2. Further, the error amplifier 6, the reference voltage circuit 7, and the NAN
The positive power supply of the D circuit 9 is connected to the positive power supply input terminal 1 and the negative power supply is connected to the output voltage terminal 5 to receive power supply.
【０００９】一方、発振回路８については、正電源はラ
イン１３によりやはり正電源入力端子１に接続される
が、負電源はライン１４により接地電位に接続される。
正電源１１が印加された直後は、出力電圧端子５の電圧
は接地電位にある。したがって、誤差増幅器６と基準電
圧回路７とＮＡＮＤ回路９は、正電源１１の電圧で駆動
される。電圧印加により反転動作を開始すると、出力電
圧端子５には式（１）で示される負電圧が発生する。し
たがって、誤差増幅器６と基準電圧回路７とＮＡＮＤ回
路９には、正電源１１の電圧をＶINとすると｜ＶIN＋Ｖ
OUT ｜の電圧が印加されることになる。しかし、発振回
路８は正電源１１の電圧ＶINで常に駆動するため、誤差
増幅器６や基準電圧回路７やＮＡＮＤ回路９に印加され
る電圧｜ＶIN＋ＶOUT ｜よりも小さいため、その消費電
流を低減することができる。On the other hand, with respect to the oscillation circuit 8, the positive power supply is also connected to the positive power supply input terminal 1 by the line 13, while the negative power supply is connected to the ground potential by the line 14.
Immediately after the positive power supply 11 is applied, the voltage of the output voltage terminal 5 is at the ground potential. Therefore, the error amplifier 6, the reference voltage circuit 7, and the NAND circuit 9 are driven by the voltage of the positive power supply 11. When the inversion operation is started by applying a voltage, a negative voltage represented by the equation (1) is generated at the output voltage terminal 5. Therefore, when the voltage of the positive power supply 11 is V IN , | V IN + V is applied to the error amplifier 6, the reference voltage circuit 7, and the NAND circuit 9.
OUT | voltage will be applied. However, since the oscillation circuit 8 is always driven by the voltage V IN of the positive power supply 11, it is smaller than the voltage | V IN + V OUT | applied to the error amplifier 6, the reference voltage circuit 7, and the NAND circuit 9, so that the current consumption is small. Can be reduced.
【００１０】[0010]
【発明の効果】以上述べたように本発明によれば、発振
回路の電源電圧を正電源１１からとることによって、反
転型スイッチングレギュレータの制御用ＩＣにおける消
費電流のうち、９０％以上を占める発振回路の消費電流
を、３０〜４０％以下にすることが可能であり、低消費
電流は反転型スイッチングレギュレータの制御用ＩＣを
供給できるという効果がある。As described above, according to the present invention, by taking the power supply voltage of the oscillation circuit from the positive power supply 11, the oscillation occupying 90% or more of the current consumption in the control IC of the inverting switching regulator is obtained. The current consumption of the circuit can be reduced to 30 to 40% or less, and the low current consumption has the effect of supplying a control IC for an inverting switching regulator.
【図１】本発明の反転型スイッチングレギュレータの回
路図である。FIG. 1 is a circuit diagram of an inverting switching regulator of the present invention.
【図２】従来の反転型スイッチングレギュレータの回路
図である。FIG. 2 is a circuit diagram of a conventional inverting switching regulator.
２ スイッチングトランジスタ ３ インダクタ ４ ダイオード ８ 発振回路 2 switching transistor 3 inductor 4 diode 8 oscillation circuit
Claims (1)
子と、 出力電圧端子と、 前記出力電圧端子と接地電圧間に接続されるブリーダ抵
抗と、 基準電圧回路と、 前記ブリーダ抵抗の接続点の電圧と前記 基準電圧回路の
出力を入力とする誤差増幅器と、発振回路と、 前記誤差増幅器の出力と前記発振回路の出力を入力とす
るゲート回路と、 前記ゲート回路の出力をゲートに入力し、ソースを前記
正電源入力端子に接続するスイッチングトランジスタ
と、 前記スイッチングトランジスタのドレインと接地電圧間
に接続されるインダクタと、 前記スイッチングトランジスタのドレインに接続される
ダイオードと、 前記ダイオードに接続される出力電圧端子を有する 反転
型スイッチングレギュレータ制御用ＩＣにおいて、前記基準電圧回路と前記誤差増幅器と前記ゲート回路の
電源を前記出力電圧端子に接続すると共に、 前記発振回路の正電源を前記正電源入力端子の電圧と
し、前記負電源を接地電圧とする反転型スイッチングレ
ギュレータ制御用ＩＣ。1. A positive power supply input terminal to which a positive voltage of a power supply is input.
And children, and an output voltage terminal, a bleeder resistance connected between said output voltage terminal and a ground voltage
To the anti, and a reference voltage circuit, an error amplifier which receives the output voltage and the reference voltage circuit of the bleeder resistor connecting point between the input and the oscillation circuit, the output of the output and the oscillation circuit of said error amplifier A gate circuit, and a switching transistor for inputting an output of the gate circuit to a gate and connecting a source to the positive power input terminal
If, between the drain and the ground voltage of the switching transistor
Connected to the drain of the switching transistor
Diode and, in the reverse switching regulator control IC having an output voltage terminal connected to said diode, and said reference voltage circuit and the error amplifier of said gate circuit
An inverting switching regulator control IC wherein a power supply is connected to the output voltage terminal, a positive power supply of the oscillation circuit is a voltage of the positive power supply input terminal, and the negative power supply is a ground voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04003180A JP3130357B2 (en) | 1992-01-10 | 1992-01-10 | Inverting type switching regulator control IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04003180A JP3130357B2 (en) | 1992-01-10 | 1992-01-10 | Inverting type switching regulator control IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05191968A JPH05191968A (en) | 1993-07-30 |
| JP3130357B2 true JP3130357B2 (en) | 2001-01-31 |
Family
ID=11550194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04003180A Expired - Fee Related JP3130357B2 (en) | 1992-01-10 | 1992-01-10 | Inverting type switching regulator control IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3130357B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010154655A (en) * | 2008-12-25 | 2010-07-08 | Renesas Technology Corp | Power system |
-
1992
- 1992-01-10 JP JP04003180A patent/JP3130357B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05191968A (en) | 1993-07-30 |
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