JP3129903B2 - Encoding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication coding method used for a medium-to-short distance transmission path such as a transmission path in a semiconductor manufacturing apparatus.

[0002]

2. Description of the Related Art Generally, in a semiconductor manufacturing apparatus for performing various processes, for example, a film forming process and an etching process on a semiconductor wafer, a motor, a vacuum gauge, a gas flow meter, Sensors, actuators, and the like must be controlled with high accuracy, and detection values must be quickly fed back from each sensor.

The number of control objects described above has increased to several hundred units in today's semiconductor manufacturing equipment, which has become highly complex. Therefore, a main control unit (master side) that manages the operation of the entire equipment. It is necessary to quickly transmit information between the input / output terminal (I / O) of the device terminal (slave side). In particular, recently, a plurality of manufacturing apparatuses that perform the same type or different types of processing are aggregated, that is, a cluster tool is used to improve the processing efficiency. In this case, control of the entire cluster tool is performed. It must be performed in a uniform manner in the main control unit, and there is a demand for faster transmission.

[0004] In normal data transmission, basically, one line for data transmission and one line for data return, respectively.
In addition, one clock line is required, and about 2 to 4 serial lines are required. In this case, the encoding method in the various communication methods transmits information in response to a temporal change of a state in one transmission line, that is, a change to High or Low. Such a method is the same when the control units are connected to each other by a serial line having a low transmission speed, or when several hundred so-called bus lines are connected.

[0005]

Here, a conventional communication method in a semiconductor manufacturing apparatus will be specifically described. FIG.
FIG. 1 shows a configuration diagram of a distributed controller system. For example, an I / O group of a semiconductor manufacturing apparatus is divided into a plurality of modules, and a slave operation unit 2 for control is controlled by each of the modules.
Set up close to O. Then, each slave side operation unit 2
To the main arithmetic unit 8 of the main control unit 6 that manages the entire operation on a medium-to-low speed communication path 4, for example, a communication path based on the RS232C standard. As a result, I / Os at each end are managed collectively for each module.

However, this method has a problem that quick control cannot be performed because the transmission speed of the communication path 4 connecting the main processing unit 8 and the slave processing unit 2 is low. is there.

FIG. 20 shows a block diagram of a centralized controller system, in which a long transmission line 10 is extracted from control elements such as I / Os, for example, digital input DI, digital output DO, analog input AI, analog output AO, and motor. This is connected to a plurality of I / O units 12 arranged on the main control unit 6 side,
Each I / O unit 12 and the main operation unit 8 are connected by a system bus 14.

However, in this method, since the main control section 6 and each control element are directly connected by a relatively long transmission line 10, the total amount of wiring in units of several hundreds becomes enormous. There is a problem that it is. In addition, since the wiring is relatively long as described above, especially when the device scale is large, noise is apt to be mixed in transmission of high-speed transmission signals and analog signals, which is a major problem in terms of noise resistance. turn into.

Therefore, a method has been developed in which some I / Os are aggregated at the device terminal, digitized, and then transmitted to a control controller of the entire device using a highly reliable transmission medium. This method is classified into two types according to the difference of the transmission medium.

One of them is an I / O intensive controller system in which a CPU bus is extended, and FIG. 21 shows a configuration diagram thereof. This scheme uses I / O near the control element.
Section 12 and each I / O section 12 is connected to the CPU bus 1
The bus 16 is connected to the main processing unit 8 of the main control unit 6 through a relatively long, for example, about 100, balanced transmission line 18 composed of about 100 wires. Then, the balanced transmission line 18, the main arithmetic unit 8, and the CPU bus 1
6, a board-like interface 20 is provided for separation.

According to this, since the CPU bus is expanded, the I / O within one bus cycle of the main control unit 16 is performed.
It has the advantage of not only being able to read or write information to and from the unit 12 to achieve high speed, but also having good noise resistance, but has the advantage of a thick and long balanced transmission of about 100 wires. There is a problem that the path 18 must be routed inside the semiconductor manufacturing apparatus.

The other transmission system is an I / O intensive controller system using a dedicated communication interface,
FIG. 22 shows the configuration diagram. This method is based on each I / O
A communication interface 22 composed of an intelligent LSI is disposed in each of the unit 12 and the main processing unit 8, and the communication interface 22 on each slave side and the communication interface 23 on the main control unit 6 are, for example, about 8 to 10 lines. The connection is made by a serial bus line 24 composed of the above-mentioned wiring.

Here, the communication method shown in FIG. 22 will be specifically described with reference to FIGS. FIG. 23 is a diagram showing a communication procedure when the main operation unit reads (reads) data of the selected I / O unit. FIG. 24 shows that the main operation unit transmits data to the selected I / O unit. The communication procedure when writing (writing) is shown. First, in the case of the read shown in FIG. 23, the read operation is performed in the following procedure.
In the following procedure, the head number indicates the communication order.

1) First, the main arithmetic unit 8 assigns the address A to the address A of the communication interface 23 on the master side.
m, an address S1 of the communication interface 22 on the slave side to be selected as the data D, and a WR (write) signal. 2) Communication interface 2 on master side receiving these
Reference numeral 3 stores the address S1 in its internal memory and sends an ACK signal indicating normal reception to the main operation unit 8.

3) Upon receiving this signal, the main operation unit 8
Outputs the address A = Am and the data D to the address a of the I / O unit 12 and the WR signal to the communication interface 23 on the master side. 4) Communication interface 2 on master side receiving these
Reference numeral 3 stores a in the internal memory and sends an ACK signal to the main operation unit 8.

5) Upon receiving this signal, the master communication interface 23 sets the address A = Am and the data D to R.
It outputs a D (read) instruction and a WR signal to the communication interface 23 on the master side. 6) Upon receiving this signal, the communication interface 23 on the master side outputs an ACK signal to the main processing unit 8 and also stores the internally stored S1, a, and RD in the serial line 2.
4 to the transmission line.

7) The communication interface 22 on the slave side selected in S1 outputs an address a and an RD signal to the I / O unit 12. 8) Upon receiving this signal, the I / O unit 12 sets the address a and the RD
And outputs the data D and the ACK signal of the response selected to the slave-side communication interface 22.

9) Receiving this signal, the communication interface 22 on the slave side outputs the received data D and an OK signal indicating that the access has been normally performed to the transmission line. A) Upon receiving this signal, the master-side communication interface 23 outputs, for example, an INT signal indicating an interrupt to the main arithmetic unit 8 to notify that data has been received. B) Upon receiving this signal, the main arithmetic unit 8 sets the address A =
Communication between the Am and RD signals on the master side communication interface 2
Output to 3 C) Upon receiving this signal, the communication interface 23 on the master side outputs the previously received data D and the ACK signal to the main arithmetic unit 8. Thus, the reading of the data D is completed.

Next, a procedure for writing data will be described with reference to FIG. 1) First, the main arithmetic unit 8 sends the address Am of the master communication interface 23 to the address A and the slave communication interface 22 to be selected to the data D.
And outputs a WR (write) signal. 2) Receiving this signal, the communication interface 23 on the master side stores S1 in the internal memory and outputs an ACK signal to the main arithmetic unit 8.

3) The address A = Am from the main operation unit 8 receiving this signal, and the data D to the address a of the I / O unit.
And the WR signal to the communication interface 23 on the master side. 4) Upon receiving this signal, the communication interface 23 on the master side saves a in the internal memory and outputs an ACK signal indicating normal reception to the main arithmetic unit 8.

5) Upon receiving this signal, the main processing unit 8
The address A = Am, the WR instruction for the data D, and the WR signal are output to the communication interface 23 on the master side. 6) Upon receiving this signal, the communication interface 23 on the master side stores the WR instruction in the internal storage and outputs an ACK signal to the main arithmetic unit 8.

7) The address A = Am from the main operation unit 8 receiving this signal and the data D to be written to the I / O unit
And the WR signal are output to the communication side interface 23 on the master side. 8) Receiving this signal, the communication interface 23 on the master side outputs an ACK signal to the main processing unit 8 and outputs S1, a, WR, and D stored internally in the transmission line including the serial line 24. .

9) The communication interface 22 on the slave side selected by the address S1 outputs the address a, the data D, and the WR signal to the I / O unit 12, respectively. A) The I / O unit 12 receiving these signals sets the address a
The received data D is written to the
The CK signal is output to the communication interface 22 on the slave side. B) Upon receiving this signal, the communication interface 22 on the slave side outputs an OK signal indicating that the access to the I / O unit has been normally performed to the transmission line. C) The master communication interface 23 that has received this signal outputs, for example, an INT signal indicating an interrupt to the main arithmetic unit 8 to notify that the data has been written to the I / O unit.

Thus, the reading of the data D is completed. As described above, in the communication method using the configuration as shown in FIG. A number of connection commands are output over the external reference cycle to activate the partner interface and perform communication.

This has the advantage that the number of wires in the serial line 24, which is relatively long, is smaller than in the system shown in FIG. 21, but as described above, one transmission line is used as the encoding method. Since the information is transmitted in accordance with the temporal change of the state in the middle, for example, in the case of start-stop synchronization, not only redundant bits such as a start bit and a stop bit must be provided, but also for sampling. In addition, the clock of the chip must be set to 8 to 16 times the transmission rate, and there is a problem that the transmission rate cannot be increased due to the limit of the operation speed of the chip.
In addition, in the case of normal synchronization, not only the time required for the preamble becomes long, but also the complicated P
There is also a problem that an LL circuit or the like must be provided.

The present invention focuses on the above problems,
It was created to solve this effectively. An object of the present invention is to provide an encoding method capable of high-speed transmission with a small number of lines.

[0027]

The present invention SUMMARY OF], in order to solve the above problems, when the digital information is encoded and transmitted through a transmission line comprising a plurality of lines, the transmission of
The parallel data to be processed is n bits (n is an integer of 2 or more).
Number), serializing in units of:
Transmitting the original data through 2 ⁿ transmission lines;
One of the 2 ⁿ transmission lines is one transmission line.
It changes every time serial transmission of the data is performed.

[0028]

Since the present invention is constructed as described above, only one of a plurality of lines, for example, two or four lines, changes simultaneously, and the change always occurs at a predetermined interval. Therefore, the meaning is determined according to the line that changes, for example, “0” or “1” for two lines, “0, 1” or “1,” for four lines. A meaning such as "0" is given, and the information is transmitted.
As a result, not only high-speed transfer can be performed in communication within a device at a relatively short distance (several tens of meters), but also extraction of a clock (CLK) can be facilitated.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An encoding method according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a communication system for implementing the method of the present invention, FIG. 2 is an external view showing a semiconductor manufacturing apparatus to which the communication system shown in FIG. 1 is applied, and FIG.
FIG. 3 is a block diagram showing a high-speed communication interface unit used in the communication system shown in FIG.

As shown in FIG. 2, this semiconductor manufacturing apparatus
A plurality, for example, three, of the same or different processing devices 26A, 2
This is a so-called cluster tool in which 6B and 26C are assembled and combined. Each processing apparatus has a transfer arm (not shown) inside and a central transfer chamber 28 disposed in the center by a gate valve or the like. The common transfer chamber 28 is connected to two cassette chambers 30A, 30A and 3A.
0B is also communicably connected. A cassette 32 for accommodating unprocessed or processed wafers is disposed in front of each of the cassette chambers 30A and 30B. A central processing unit (CPU) is provided on the front panel of the apparatus for each device in the apparatus. An input device 34 and a display 36 for inputting via the PC are provided.

In such an apparatus, the transfer of wafers to each processing apparatus is all performed via the common transfer chamber 28, thereby improving the processing efficiency. Then, control of a vacuum gauge, a gas flow meter (MFC), various sensors, various actuators, various motors and the like in each processing apparatus, and a supply and exhaust system of the common transfer chamber 28 and the cassette chambers 30A and 30B,
Since it is necessary to centrally control movable parts and gate valves that partition the space,
A single master-side control unit 38 composed of a PU module is provided, and a plurality of slave-side control units 40 are formed by modularizing I / O in each processing device, common transfer chamber, cassette chamber, and the like. The slave-side control unit 40 and the master-side control unit 38 are connected by a serial line 42 and are centrally managed. FIG. 2 shows, as an example, a master-side controller (CPU module) 38 and first and second slave-side controllers (chamber I / O control modules) 38A and 38B. Although the number of units depends on the scale of the entire apparatus, for example, up to about 31 modules can be connected. The overall size of this device is less than several meters in length, width and height, and the serial line 42 connecting the modules is not too long. Done.

As shown in FIG.
. 0A, 40B, 40C... Have high-speed communication interface units 44M,
4S, known bus interfaces 46M and 46S and a port interface are provided. The master bus interface 46M is connected to the CPU by the CPU bus 48, and each of the slave bus interfaces 46S or the port interface is connected to the motor control I / O. O, AD (analog digital) or DA
(Digital-Analog) It is connected to the I / O to be converted, a memory, a digital I / O of a sensor, an actuator, and the like.
Each slave-side control unit is sequentially line-connected to form a network, that is, multi-drop, and finally the bus terminator 50 is connected.

Here, the high-speed communication interface unit 4
The configuration of the 4M, 44S will be described with reference to FIG. The high-speed communication interfaces 44M and 44S have the same structure, and are integrated on one chip. The high-speed communication interface section is roughly divided into a master / slave block (MS block) and a communication block.

The master / slave block (MS block) is an I / F (in master mode) with the CPU on the master side.
And I / F with slave I / O bus (in slave mode)
This block mainly generates an I / F (interface) with the outside of the chip, a communication request signal, transmission message / data, and interprets and executes a received message.
Each constituent block of the S block will be described. In the figure, [M] indicates an element that operates only in the master mode.
[S] indicates a device that operates only in the slave mode,
[R] indicates the one that operates only in the repeater mode.

The master sequencer 52 performs address reception and data transmission and reception.
This block has a function of controlling all operations of the MS block and returning a response to an access from the U.
The slave sequencer 54 is a block having a function of controlling all operations of the MS block and returning a response to a request from the communication block in the slave mode.

The address decoder / data selector 56 connected to the master sequencer 52 and the slave sequencer 54 determines whether the request from the master sequencer 52 or the slave sequencer 54 is a register / counter 58, a communication, or a slave I / O bus access. This is a block for selecting a kana and issuing an access request to each functional block.

The address decoder / data selector 5
6 are connected to a control / error / status register, a timer, a DM, and the like.
This block includes all registers / counters necessary for this chip, such as an A (Direct Memory Access) transfer circuit counter. There is also a DI / DO port that operates in the slave port mode. An access request to a communication block has the following four requesters, and the requester block operates only in the master mode.

The slave bus requester 60 is a block for directly issuing a slave communication access request in response to a request from the CPU. There are slave registers or slave I / O buses and slave port access. The interrupt polling requester 62 is a block that issues a communication access request at a set interval in order to confirm the interrupt occurrence status on the slave side. This request is made automatically irrespective of the access from the CPU.

DMA Ch. 0 requester 64 is DM
This is a block for realizing the A transfer. The presence or absence of a DMA request from a slave is automatically confirmed at a set interval, and necessary data transfer is performed. It also has a DMA I / F function with the outside of the chip. DMA Ch. 1 requester 66 is the DMA Ch. It is a block having the same function as 0.

Each of the requesters 60, 62, 64, 66
A communication bus arbiter 68 connected to the arbiter is a block for arbitrating a communication access request from each requester. By the arbitration function of the block 68, two or more accesses to the communication block do not occur at the same time.

The message / data formatter 70 connected to the slave sequencer 54 and the communication bus arbiter 68 converts the address and data to be transmitted into a body according to a prescribed communication format, It has a function to decompose the body part into addresses and data. The communication message includes a header section, a body section, a CRC section, and a recovery section.
The body part therein is composed of an address and data configuration, but the configuration must be adjusted because the body length is changed by a communication command.

An access request to the slave I / O bus has the following two requesters, ie, repliers. These reply blocks operate only in the slave mode. One I / O bus reply 72 is
This block issues a bus access request to the I / O bus arbiter 76 in response to a slave I / O bus access request from the high-speed communication interface chip on the master side. The other DMA reply 74 is a block for realizing DMA transfer with the master. DMA with outside chip
And a function for responding to the confirmation of the presence or absence of a DMA request from the master side and performing necessary DMA data transfer.

The I / O bus arbiter 76 connected to the I / O bus replier 72, the DMA replier 74 and the slave bus I / F 78 described below waits for the request of each of the replier 72, 74 for a specified time or more. Sometimes has the function of generating a bus hold timeout error. The access request to the slave bus I / F 78 includes the two replies and the secondary bus master (2nd CPU) outside the chip. The slave bus also has a function of arbitrating the slave bus in response to these requests.

The slave bus I / F 78 transmits an address, transmits and receives data, and transmits and receives digital data.
In addition to the basic function of the I / F for accessing the slave I / O bus, a funneling function that matches the data width of the I / O bus and the replyer, a bus timeout when an acknowledgment does not return from the I / O bus for a specified time Has the function of generating an error.

In contrast to the above-described MS block, the communication block is a block that controls network communication in the high-speed communication interface unit, and exchanges messages and data in parallel with the MS block. Input / output signals with the outside of the chip are: 4 transmission lines, 4 reception lines,
One transmission enable signal. The communication block includes a flow controller 80, a transmitter 82, a line state detector 84, a receiver 86, a repeater 88, a break /
It is configured by an emergency generation section 90. less than,
The function of each component block of the communication block will be described.

First, the flow controller 80 is a block for controlling the flow of transmission / reception of communication.
Here, a process of generating a header part for the communication message data and passing it to the transmission block (transmitter) together with the body part from the MS block is performed. Also, it interprets the body part of the communication message data from the receiving block (receiver) and judges the message addressed to itself, the retransmission message, the retransmission request, the error message, etc.
Do the processing.

The transmitter 82 connected to the flow controller 80 and the break / emergency generation circuit 90 transmits the transmission request and the transmission message data from the flow controller 80 to the GCC 4 /
GCC2 (Gray Coded Coding 4 /
2) The transmission is performed by changing the transmission line in accordance with the setting of each mode of MMC (Modified Manchester coding). These GCC / MMC codes are designed to be used for communication inside the device. In particular, the GCC code which is a feature of the present invention is, for example, a relatively short distance extension of an I / O bus in the device. It is an object of the present invention to perform high-speed data transfer by using a plurality of transmission lines to minimize the circuit load of each node. Also, M
The purpose of the MC code is to provide an efficient and simple bit-oriented synchronous communication means based on the Manchester code under a use condition free from collision such as opposition or multi-drop. These encoding methods are implemented in this transmitter. Note that these encoding methods will be described later.

The line state detector 84 is connected to the flow controller 80 and is a block for constantly monitoring the line state such as break, emergency, no line bit change, and line / space state. The receiver 86 is a block that is connected to the flow controller 80 and receives message / data of the transmission line together with the line state detection block 84.
Although normal reception confirmation at the bit level is performed, whether the received message is significant is determined by the flow controller 8.
Leave it to 0. The encoding method described in the transmitter 82 is also implemented in the receiver 86.

The repeater 88 is connected to the flow controller 80, the line state detector 84, and the receiver 86, and operates in the repeater mode in the network form of the high-speed communication interface unit. Generate a communication direction control signal. In this mode, the chip also functions as a monitor of the transmission line, outputting message data on the line and a signal for monitoring the line state. In the repeater mode, the flow controller 80 and the transmitter 82 do not operate.

The break / emergency generating section 90
The break / emergency signal is input, and a break / emergency signal is output to the transmitter 82.
Requests for transmission of these abnormal signals are made in this block separately from the regular route to prevent accidents.

Next, the GCC code of the communication block, M
A block for realizing the MC code will be described.
The transmitting unit and the receiving unit described below are mainly included in the transmitter 82 and the receiver 86 described above. FIG.
FIG. 3 is a block diagram illustrating a GCC code transmission unit. This transmission unit is provided with a serial / parallel conversion circuit 9 as shown in the figure.
2. It is composed of a data encoding circuit 94, a line return code generation circuit 96, and the break / emergency generation circuit section 90 described above.

First, the serial / parallel conversion circuit 92
Is a block that receives parallel data and converts the formatted parallel transmission message data into serial data, and outputs the generated serial data to the data coding circuit 94. In this conversion circuit,
In the communication codec mode (GCC4 / GCC2), serial bits to be converted are changed to 2 bits or 1 bit, respectively.

The data coding circuit 94 receives the input from the other three circuits and codes the serialized transmission message data and the line return code after the completion of the message transmission in accordance with GCC4 / GCC2. Also, in response to a break request from the break / emergency generation circuit 98, the line signal is changed to the break state with priority even during message transmission.

The GCC4 / GCC2 encoding method will be described later. The line return code generation circuit 96
After the transmission of the transmission message data, the state of the line signal is detected, a line return code is generated from the state of the line signal, and this is supplied to the data encoding circuit 94. In addition, the break / emergency generation circuit (part) 90 responds to the break / emergency request by the data encoding circuit 94 for a specified time as described above.
Is a circuit that issues a break request to On the transmission line,
Breaks and emergencies are distinguished by their issuance times.

FIG. 5 is a block diagram showing a receiving section of the GCC code. As shown, the receiving unit includes a sampling circuit 98, a line change detection circuit 100, a data / CLK
Extraction circuit 102, serial / parallel conversion circuit 104,
It is composed of a line error circuit 106 and the line state detection circuit 84 described above.

The sampling circuit 98 is a circuit which receives a line signal, samples it with a system clock, and synchronizes it.
0 is output to the line error detection circuit 106 and the line state detection circuit. The line change detection circuit 100
This circuit detects changes (rising / falling) of the four line signals, and outputs the data / C
It is output to the LK extraction circuit 102 and the line error detection circuit 106.

The data / CLK extracting circuit 102 is a circuit for extracting serial data (GCC4 = 2 bits, GCC2 = 1 bit) and a bit change timing clock from the line change. The serial / parallel conversion circuit 104 is a circuit that converts the extracted n-bit serial data (GCC4: n = 2, GCC2: n = 1) into parallel according to the received timing clock, and outputs parallel data.

The line error detection circuit 106 receives the output of the line change detection circuit 100 and determines that the line change is GCC4.
/ GCC2 is a circuit that generates an error signal when the signal does not conform to the encoding. There are two types of error contents detected here: multi-bit change (MBC) when a plurality of lines change at the same time, and no-bit change (NBC) when no line changes within a specified time.

The above-mentioned line state detection circuit 84
This is a circuit for detecting a line state other than the line error. The contents to be detected are a line space in which all the line signals are at a High level for a specified time or more, and a break / emergency in which the line signals are at a Low level for a specified time or more. The break has a low level for a sufficiently long time (for example, eight times the transmission clock) compared to the normal communication state, and the emergency has a sufficiently long time (for example, several times as many times as the break detection) as compared to the break detection time.
A distinction is made based on the difference in the detection time, such as at w level.

FIG. 6 is a block diagram showing an MMC code transmitting section. As shown, the transmission unit includes a serial / parallel conversion circuit 108, a data coding circuit 110, and the break / emergency generation circuit (part) described above.
90.

First, the serial / parallel conversion circuit 108
Is a circuit for converting the transmission message data of the formatted parallel data into 1-bit serial data. The data encoding circuit 110 encodes the serialized transmission message data and the line return after the completion of the message transmission according to the MMC regulations. Further, in response to a break request from the break / emergency generation circuit 90, the line signal is changed to the break state with priority even during message transmission. The MMC encoding method will be described later. The break / emergency generation circuit 90 is the same as described above.

FIG. 7 is a block diagram showing an MMC code receiving section. The receiving unit includes a sampling circuit 112, a line change detection circuit 114, a data / CL
K bit detection circuit 116, start bit detection circuit 11
8, bit synchronization circuit 120, data / CLK extraction circuit 1
22, a serial / parallel conversion circuit 124 and the line state detection circuit 84 described above.

First, the sampling circuit 112 is a circuit that samples and synchronizes a line signal with a system clock. The line change detection circuit 114 is a circuit that detects a change (rise / fall) of the line signal. The data / CLK bit detection circuit 116 is a circuit that extracts a data bit and a CLK bit from a line change in accordance with the MMC coding rule based on the count value from the bit synchronization circuit 120, and a line change that violates the rule. At times, an error signal is issued.

The start bit detecting circuit 118 receives the input from the line change detecting circuit 114 and detects a start bit indicating the start of a communication message from among the detected line changes, and receives message data from this. To the necessary blocks, for example, the bit synchronization circuit 120. The bit synchronization circuit 120 is a circuit that counts the time until the next line change every time a start is detected or a normal CLK bit is detected. This count value is used by the data / CLK bit detection circuit 116 as a criterion for determining whether the line change is normal or abnormal.

The data / CLK extraction circuit 122 is a circuit for extracting 1-bit serial data and a timing clock of a bit change from a line change. The serial / parallel conversion circuit 124 is a circuit that converts the extracted 1-bit serial data into parallel data according to the received timing clock. Line state detection circuit 84
Is the same as described above.

Next, the coding method of the present invention performed by the communication system configured as described above will be described together with the communication method. First, a case of a read cycle for reading data from a selected module (slave-side control unit) will be described.

FIG. 8 is a diagram showing a communication procedure in the case of a read cycle. In this read cycle, the control unit 38 on the master side selects a desired one from a plurality of slave side control units and reads out data of a specific I / O from the selected one. However, in the conventional method, a plurality of bus cycles, that is, external reference cycles are required, but in the present invention, it is performed in one bus cycle. In the following procedure, the head number indicates the communication order.

1) First, the main processing unit 8 of the master-side control unit 38 transmits the address A and RD (read) signal via the CPU bus 48 to the high-speed communication interface unit 4 on the master side.
Output to 4M. The address A has a form including the address of the master-side high-speed communication interface unit, the address S1 of the slave-side high-speed communication interface unit 44S to be selected, and the slave-side I / O address a. I have.

2) The master-side high-speed communication interface unit 44M receiving the above signal operates the respective high-speed communication interface units 44S on the slave side to be selected from the address A by the operation of each block shown in FIG. An address S1 and its I / O address a are generated and transmitted to a serial line (transmission line) 42 together with an RD (read) signal as serial data. In this case, while the data transfer rate in the conventional transmission line is relatively low, for example, 64 KBPS, in the present embodiment, for example, the data transfer rate is 40 MBPS.
PS and high-speed transfer are performed. The above address S1
, One module, that is, a slave-side control unit is selected from the plurality of chamber I / O control modules # 1, # 2, # 3,... Shown in FIG.

3) The high-speed communication interface 44S on the slave side selected by the address S1 is connected to the I / O side (motor control, AD / DA,
DI / DO, etc.) and outputs an address a and an RD (read) signal. In this case, the serially input received data is restored in parallel. 4) Here, the I / O specified by the address a is the address a, the data D selected by the RD signal, and the response ACK signal indicating that the I / O has been read normally, and the slave high-speed communication interface. The signal is output in parallel to the unit 44S.

5) The high-speed communication interface unit 44S on the slave side of the address S1 receiving the above signal is connected to the I / O
The data D received from the side and an OK signal indicating that I / O access has been normally performed are serially output to a serial line 42 which is a transmission line. 6) Upon receiving the above signal, the master side high-speed communication interface unit 44M outputs the input data D and a response ACK signal indicating that the access has been normally performed to the main arithmetic unit 8. Become. As a result, the data D at the predetermined address a of the I / O is read, and the C
It will be taken in PU.

In this case, a series of reading procedures 1) to 6) described above are performed during one bus cycle (external reference cycle) of the main processing unit (CPU) 8.
In order to read data during one bus cycle, high-speed transfer of, for example, 40 MBPS is performed.

That is, one of the main operation units 8 on the master side
During the three external reference cycles, various instructions output from the arithmetic unit 8 are serially assembled and transferred at high speed by the high-speed communication interface unit 44M on the master side. The interface unit 44S reconfigures the received data in parallel to access the I / O, and sends the data to the master side in the reverse procedure.

Therefore, the master side main arithmetic unit 8 can directly access the slave side I / O at the same level as that of the master side memory, for example, and the conventional method (see FIG. 23). ) Can significantly reduce the access time at the time of reading.

Next, the case of a write cycle will be described. FIG. 9 is a diagram showing a communication procedure in the case of a write cycle. In this write cycle, the control unit 3 on the master side
8 selects a desired one from a plurality of slave-side control units, and writes data to a specific I / O among them. This series of write operations is performed in the same manner as in the read cycle described above. In one bus cycle. In the following procedure, the head number indicates the communication order.

1) First, the main processing unit 8 of the master-side control unit 38 sends an address A via the CPU bus 48 and an I / O
And outputs a data D to be written and a WR (write) signal to the high-speed communication interface unit 44 on the master side. The address A includes the address of the master-side high-speed communication interface unit, the address S1 of the slave-side high-speed communication interface unit 44S to be selected, and the address a of the slave-side I / O. .

2) The master-side high-speed communication interface unit 44M receiving the above signal operates the slave-side high-speed communication interface unit 44S to be selected from the address A by operating the respective blocks shown in FIG. An address S1 and an address a of its I / O are generated, and data D and WR (write) are written to a serial line (transmission line) 42.
It is sent out as serial data with the signal. Also in this case, for example, 40 times faster than the transfer rate in the case of the conventional transmission.
MBPS high-speed transfer is performed. The above address S1
, One module, that is, a slave-side control unit is selected from the plurality of chamber I / O control modules # 1, # 2, # 3,... Shown in FIG.

3) The high-speed communication interface unit 44S on the slave side selected by the address S1 is connected to the I / O side (motor control, AD / DA,
DI / DO, etc.) to output an address a, data D, and a WR (write) signal. In this case, the serially input received data is restored in parallel. 4) Here, the I / O specified by the address a writes the data D to the location selected by the address a and the WR signal, and sends a response ACK signal indicating this to the slave high-speed communication interface unit. Output in parallel to 44S.

5) The high-speed communication interface unit 44S on the slave side of the address S1 receiving the signal receives the I / O signal.
An OK signal indicating that the access has been normally performed is serially output to a serial line 42 as a transmission line. 6) The master-side high-speed communication interface unit 44M having received the signal outputs a response ACK signal indicating that the access has been normally performed to the main arithmetic unit 8. As a result, the data D of the main operation unit 8 on the master side is written to a predetermined address a of the I / O.

Also in this case, similarly to the above-described reading procedure, the series of writing procedures 1) to 6) described above are performed during one bus cycle (external reference cycle) of the main processing unit (CPU) 8. Therefore, the master-side main arithmetic unit 8 can directly access the slave-side I / O at the same level as the master-side memory, for example. That is, when the main operation unit 8 acts on the final address of the I / O with a plurality of commands, the high-speed communication interface unit on the master side fetches the parallel data, converts it into serial data, and transmits it. The high-speed communication interface unit on the side converts the data into parallel data, accesses the I / O, and performs writing. This series of operations is performed during one bus cycle.

As a result of performing the read / write cycle as described above, according to the conventional method, for example, the time required for one data read is several tens of
Although the order was from 0 μsec to several msec, according to the present embodiment, the access was completed within 10 μsec, and the processing time was greatly shortened to enable high-speed processing.

Next, the case of an interrupt cycle will be described. FIG. 10 is a diagram showing a communication procedure in the case of an interrupt cycle. This interrupt cycle can be performed by any I / O
This is a communication procedure for detecting an interrupt request from the server.
In the following procedure, the head number indicates the communication order.

1) First, the main arithmetic unit 8 of the master-side control unit 38 specifies the address Am of the high-speed communication interface unit 44M on the master side as the address A and the slave S1 to poll the data D, and writes the WR (write). ) Generate a signal. 2) The master-side high-speed communication interface unit 44M that has received this signal stores S1 in the internal storage and outputs an ACK signal for confirmation to the main arithmetic unit 8.

3) Main arithmetic unit 8 receiving ACK signal
Specifies the address Am of the high-speed communication interface unit 44M on the master side and the interval time Ti for polling the data D as the address A, and generates a WR (write) signal. 4) The master-side high-speed communication interface unit 44M that has received this signal stores Ti in the internal storage and outputs an ACK signal for confirmation to the main operation unit 8.

5) Upon receiving this signal, the master-side high-speed communication interface unit 44M inquires the slave-side high-speed communication interface unit 44S at intervals specified by the interval time Ti whether an interrupt has occurred. For this purpose, an address S1 and an IRQ_POL command are output on a transmission line composed of the serial line 42. 6) When the high-speed communication interface unit 44S on the slave side that has input this command does not generate an interrupt for the I / O under its control, the NO_IR
Q is output on the transmission line, and responds to the main arithmetic unit 8 on the master side.

7) Here, it is assumed that an arbitrary I / O generates an INT indicating an interrupt at a certain point in time toward the high-speed communication interface unit 44S on the slave side. 8) Here, the main arithmetic unit 8 on the master side sends the address S1 on the transmission line to inquire whether the interrupt has occurred to the interface unit 44S for high speed communication on the slave side at intervals specified by the interval time Ti. And I
Output the RQ_POL command.

9) The slave high-speed communication interface unit 44S (S1) receiving this signal outputs the IRQ signal indicating the interrupt request to the master side because the I / O interrupt has occurred as described above. To the high-speed communication interface unit 44M. A) The master-side high-speed communication interface unit 44M receiving the IRQ signal outputs an INT signal indicating an interrupt to the main operation unit 8. B) Upon receiving the INT signal, the main operation unit 8 controls the I / O by using the above-described read cycle and write cycle. As described above, the interrupt cycle is completed.

Next, the case of a DMA (direct memory access) cycle will be described. FIG. 11 shows the DMA
It is a figure showing the communication procedure in the case of a cycle. in this case,
In order to perform the DMA cycle, the main operation unit 8 is used or a special controller (DMAC) is provided.

In the DMA cycle, when data of I / O is transferred to the main memory on the master side, this is directly performed by hardware.
This is performed by connecting the I / O and the memory via a bus without using the memory. Main CPU controls DM
When temporarily transferred to AC, the DMAC is
It operates to transfer the data of / O to the memory. That is, this DMA can be considered to be data obtained by adding data to the above-described interrupt operation. In the following procedure, the head number indicates the communication order.

1) to 4) First, steps 1) to 4) are repeated as many times as the number of slave registers that need to be set in the DMA in the same manner as described in the write cycle described above. 5) -6) Master-side high-speed communication interface unit 44
5) to 6) are repeated as many times as the number of master registers that need to be set in the DMA in order to access the register to M.

7) Next, it is checked whether or not the high-speed communication interface unit 44M on the master side outputs polling to the slave side on the transmission line to output a DMA request (DRQ). 8) When the high-speed communication interface unit 44S on the slave side does not output the DRQ, NO_
The DRQ signal is output to the transmission line to reply. 9) Here, a DRQ (DMA) is sent to the high-speed communication interface 44S on the slave side corresponding to an arbitrary I / O.
Is issued, and when the internal preparation of the high-speed communication interface unit 44S on the slave side is completed, the data D accompanying the data is fetched from the slave bus.

10) Next, it is checked whether or not the high-speed communication interface unit 44M on the master side outputs a DMA request (DRQ) to the slave side in the same manner as in the above-mentioned procedure 7). 11) Receiving this signal, the high-speed communication interface unit 44S on the slave side outputs a DRQ signal to the transmission line in response to receiving the DRQ signal from the I / O, and determines the presence of the DMA request on the high-speed communication on the master side. Interface section 44
Notify M.

12) Upon receiving this signal, the master-side high-speed communication interface unit 44M reads the DMA data that the slave-side high-speed communication interface unit 44S has previously fetched from the slave side. 13) Upon receiving this signal, the slave-side high-speed communication interface unit 44S sends out the data D, and the master-side high-speed communication interface unit 44M stores this data D in an internal register.

14) The master-side high-speed communication interface 44M informs the DM that the DMA data D has been fetched.
Report to AC. 15) Upon receiving this signal, the DMAC fetches the received DMA from the master-side high-speed communication interface 44M.
You will read the data. Thereafter, the steps 7) to 15) are repeated by the number of times of the DMA transfer to complete the DMA operation.

Next, the case of an EMG (emergency) cycle will be described. FIG. 12 is a diagram showing a communication procedure in the case of an EMG cycle, and FIG. 12A is a diagram showing a case of outputting an EMG signal to the slave side.
2 (B) shows a case where an EMG signal is output to the master side.

This EMG cycle is performed using a break signal in the communication circuit. For example, when a break signal is output when a fire or the like occurs in any of the processing units, the master high-speed communication interface unit is connected. The signal is forcibly pulled. This break signal is represented as a continuous low-level signal long enough to be sufficiently distinguished from inadvertently introduced noise.

1) An EMG signal is input to the high-speed communication interface unit 44M on the master side. 2) Upon receiving this signal, the master-side high-speed communication interface unit 44M drives the transmission line to the EMG state. 3) Then, all the high-speed communication interface units on the slave side output an EMG signal to the I / O, and notify all the I / Os of that.

4) On the other hand, when an emergency occurs in a certain I / O, an EMG signal is input to a high-speed communication interface on one slave side which controls the emergency. 5) The interface section for high-speed communication on the slave side to which the EMG signal is input drives the transmission line to the EMG state. 6) Then, the other high-speed communication interface units on the slave side output an EMG signal to the controlling I / O, and at the same time, the high-speed communication interface unit 44M on the master side outputs an EMG signal to the main CPU side. Will be notified. Thus, the EMG cycle is completed.

Next, a specific description will be given of an encoding method which is a feature of the present invention and is used between a master and a slave in the above-described communication method. In this embodiment, MMC (Modified Manchester coding) performed by the circuits shown in FIGS. 6 and 7 and GCC (Gray coded coding) performed by the circuits shown in FIGS.
Is used. The GCC code includes GCC4 and GC
There are two types of C2. This MMC / GCC code has been devised for use in communication inside the device as described above.

The main purpose of the MMC code is to provide a simple and efficient bit-oriented synchronous communication means based on Manchester codes under use conditions free from collisions such as opposition and multidrop. The GCC code is
For example, the purpose is to extend an I / O bus in a device at a relatively short distance, and to minimize the circuit load of each node by using a plurality of (two or four) transmission lines (lines). It aims at high-speed data transfer.

There are various existing transmission methods for communicating between nodes, but all of them focus on minimizing the number of communication lines (two to four). As described above, there are the following restrictions. The controller becomes complicated. Transmission speed is slow.

Regarding start-stop synchronization and synchronization, in start-stop synchronization, since there is no clock component, synchronization has to be reestablished for each byte. About 3 bits are required. In addition, the clock of the chip is required to be 8 to 16 times the transmission rate for sampling, and the transmission rate cannot be increased due to the operating speed limit of the chip.

In the ordinary synchronization, not only the time required for the preamble is long, but also clock extraction using a PLL circuit or the like is troublesome. By using the MMC / GCC code, the above problem can be solved to some extent. The number of transmission lines is one for MMC1 and one for transmission and reception.
2 is two transmission / reception lines, and GCC4 is four transmission / reception lines.

Now, the rules of each encoding method will be described.
MMC1 becomes "1" at the rise of the transmission path and "0" at the fall. In GCC2, the change of each transmission path is “0” and “1”. In GCC4, the change of each transmission path is “00”, “01”, “10”, and “11”.

In the GCC code, a plurality of transmission paths do not change at the same time, and a change in any one of the transmission paths always occurs at predetermined intervals. The feature of the MMC code is that the sampling rate is six times the bit rate. The features of the GCC code are that the clock can be extracted with a simple circuit, that only one bit changes at the same time on the line, it is strong in phase variation, and that the sampling rate is more than three times the bit rate. The point is that it can be slow because it is good, and a high transfer speed can be obtained.

First, the encoding method of MMC1 will be described.
FIG. 13 is a waveform diagram showing the waveform of each part in the transmission section shown in FIG. First, when the parallel data α to be transmitted is input to the serial / parallel conversion circuit 108, the data is converted into 1-bit serial data β. The serial data β is generated by the data encoding circuit 110 and sent out as a line signal γ.

In this case, encoding is performed for serial data "1".
In this case, the line signal changes from low to high, and when the serial data is "0", the line changes from high to low. When data is not being transmitted, the transmission line is maintained in a high state. Therefore, by setting the line to low at the start of transmission,
Add a start bit. Data bits are extracted from the transmitted line signal at predetermined intervals determined by a CLK bit determined on the receiving side, as described later. When the transmission of the message data is completed, if the transmission line is not High, the transmission line is set to the High state, and the line is always restored.

When a break / emergency issuance request is issued, a break line signal is output from any line state. In the data coding circuit 110, there is no distinction between break / emergency, and all the line signals γ are kept in a low state only during the time when the break request is input, and the time management at this time is performed by the break / emergency generation circuit 90.

Next, the operation of the receiving section of the MMC 1 will be described. FIG. 14 is a waveform diagram showing the waveform of each part in the receiving section of the MMC code shown in FIG. First, the line signal I is sampled and synchronized by the sampling circuit 112 at, for example, a sampling CLK six times the transfer rate, and a line state change signal II (SRx0) is created. Then, based on the SRx0 signal, the data / CLK
Bit detection circuit 116, start bit detection circuit 11
8, from the bit synchronization circuit 120 and the data / CLK extraction circuit 122, the start bit III, the CLK bit IV,
1-bit serial data V and an RxCLK signal VI are generated. Then, the serial / parallel conversion circuit 124 generates parallel data VII based on the serial data V and the RxCLK signal VI, and restores the original data.

Next, the operation of the transmitting section of GCC4 will be described. FIG. 15 is a waveform diagram showing the waveform of each part in the transmitting section of the GCC code shown in FIG. First, the parallel data to be transmitted is converted by the serial / parallel conversion circuit 92 into 2-bit serial data. Then, the serial data is converted into a 4-bit parallel data line signal by the data coding circuit 94 and transmitted.

In this case, as described above, when the serial data is "1, 0", the T
The line of x2 is changed, the line of Tx1 is changed at "0,1", the line of Tx3 is changed at "1,1", and the line of Tx0 is changed at "0,0". Note that a plurality of lines do not change at the same time. Further, a change in any one of the lines always occurs at predetermined intervals. As described above, only one of the plurality of lines is changed at any one time, and the meaning is given to that.

In the line restoration process after the transmission of the message is completed, the line restoration code generation circuit 96 encodes and outputs the line restoration code. At this time, the return code is sequentially changed from the line of Tx0 to the state of Low → High. If the state of the line is already High, the next line is processed in order, and all the lines are returned to the state of High. . In this case, at the time of data transmission, data can be transmitted immediately without first providing a start bit such as a preamble.

When a break / emergency issuance request is issued, a break line signal is output from any line state. In the data coding circuit 94, there is no distinction between break / emergency, and all the line signals are kept in a low state only during the time when the break request is input. The time management at this time is performed by the break / emergency generation circuit 90.

In transmitting actual data,
At the end of the data transmission, 8 is used to check whether the data transmitted so far is correct (whether there are no missing bits or the like).
CRC of up to 16 bits (Cyclic Redundancy Check: Cyclic
A Redundancy Checks check is performed, but depending on how this CRC check is performed, it is not necessary to perform a return operation for finally setting all the lines to a High state. For example, as an example, the number of bytes of message data to be transmitted in the case of the GCC4 code may be set to a multiple of four. Therefore, for example, when it is desired to transmit message data having a byte number of 18 bits, 2 bits are added to 20 bits which is a multiple of 4 so that all lines can be transmitted without performing a return operation at the end of the CRC check. High state can be set.

Next, the operation of the receiving unit of GCC4 will be described. FIG. 17 is a waveform chart showing the waveform of each part in the receiving unit of the GCC code shown in FIG. The input line signals A (four) are sampled and synchronized by the sampling circuit 98 at, for example, a sampling CLK four times the transfer rate, and the state change signal B (SRx0
To SRx3). Then, in the data / CLK extraction circuit 102, these four signals (SRx0 to SRx
From 3), according to the GCC encoding, n bits, 2 bits in this embodiment, serial data D and reception CLK
(RxCLK) Generate a signal C. The received CLK signal C can be easily created by passing the above four signals (SRx0 to SRx3) through an exclusive OR circuit (EX-OR). And a serial / parallel conversion circuit 1
In step 04, the parallel data E is generated from the serial data D and the RxCLK signal C, and the original data is restored.

Next, the operation of the transmitting section of GCC2 will be described. FIG. 16 is a waveform chart showing the waveform of each part in the transmitting section of the GCC code shown in FIG. The GCC2 code is different from the GCC4 code in that meaning is given to a change in two lines, and the GCC2 code is used for other points.
Same as CC4 code.

That is, first, the parallel data to be transmitted is converted by the serial / parallel conversion circuit 92 into 1-bit serial data. Then, the serial data is converted into a 2-bit line signal by the data encoding circuit 94 and transmitted. In this case, the encoding changes the Tx1 line of the two lines when the serial data is "1" as described above, and changes the Tx1 when the serial data is "0".
Change the 0 line. The two lines do not change at the same time. Further, similarly to the above-mentioned GCC4 code, a change in any line always occurs at predetermined intervals. As described above, one of the two lines always changes and has a meaning.

In the line restoration process after the transmission of the message is completed, the line restoration code generation circuit 96 encodes and outputs the line restoration code. At this time, the return code is sequentially changed from the line of Tx0 to the state of Low → High. If the state of the line is already High, the next line is processed and all the two lines are returned to the state of High. . In this case, if a CRC check of an even parity is performed, a line return operation can be made unnecessary. In this case, when data is transmitted, the point that data can be transmitted immediately without adding a start bit or the like is the same as in the case of GCC4.

When a break / emergency issuance request is issued, a break line signal is output from any line state. In the data coding circuit 94, there is no distinction between break / emergency, and all the line signals are kept in a low state only during the time when the break request is input, and the time management at this time is performed by the break / emergency generation circuit 96.

Next, the operation of the receiving section of GCC2 will be described. FIG. 18 is a waveform chart showing waveforms of respective parts in the receiving unit of the GCC code shown in FIG. The input line signals A (two lines) are sampled by the sampling circuit 98 at, for example, a sampling CLK twice as high as the transfer rate and synchronized, and the state change signal B (SRx
0, SRx1). Then, the two signals (SRx0, SRx
x1), GCC2 is coded to n bits, in this embodiment, 1-bit serial data D and reception CL
A K (RxCLK) signal C is generated. The received CLK signal C can be easily created by passing the two signals (SRx0, SRx1) through an exclusive OR circuit (EX-OR). Then, the serial conversion circuit 104 generates parallel data E from the serial data and the RxCLK signal C, and restores the original data.

As described above, according to the GCC4 / GCC2 encoding method, a plurality of lines are used, and only one of these lines is necessarily changed to have a meaning. High-speed transfer can be performed. For example, a practical line speed is limited to, for example, about 10 MHz (system clock is 40 MHz), but a transfer rate of 40 MBPS is possible in GCC code. Further, since redundant bits such as a start bit and a stop bit can be reduced, a circuit load can be reduced correspondingly, and higher-speed data transfer can be performed.

As described above, the sampling speed is about 4 to 6 times the transfer rate, and circuit design is easy. Further, in order to form an internal clock (CLK) signal, it is only necessary to pass the received data through an exclusive OR element, so that a conventionally required PLL (Phase (Phase)
A Locked Loop (Clocked Loop) circuit, a clock line, and the like can be eliminated, and the configuration is simple.

Also, since only one line changes at the same time, it is more resistant to noise.
It is very suitable for a semiconductor manufacturing apparatus using many noise sources such as magnets. Furthermore, in order to reduce the transmission error, the phase margin on the communication path is important, but by performing the GCC encoding method as described above,
Although it depends on the sampling speed, the phase margin is up to ±
It was possible to enlarge to 25%, to be strong against delay, and to obtain good transmission results. In the above embodiments, the semiconductor manufacturing apparatus has been described as an example of the intra-device communication, but it is needless to say that the present invention is not limited to this.

[0124]

As described above, according to the encoding method of the present invention, the following excellent effects can be obtained. Parallel at predetermined intervals, for example, in units of 2 bits
Each time the data is transmitted serially, the state of one of the plurality of lines is changed, and a predetermined meaning is assigned in accordance with the changed line. It is possible to reduce the number, and to perform high-speed data transmission. In addition, since a clock signal can be easily extracted from changes in a plurality of lines, it is not necessary to provide a dedicated clock line or a complicated circuit for extracting a clock. Furthermore, since only one line state changes at the same time, noise resistance can be improved. Since high-speed transmission is possible without greatly increasing the number of transmission lines, it is possible to provide an encoding method that is optimal for medium-to-short distance communication such as intra-device communication.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a communication system for implementing a method of the present invention.

FIG. 2 is an external view showing a semiconductor manufacturing apparatus to which the communication system shown in FIG. 1 is applied.

FIG. 3 is a block diagram showing a high-speed communication interface unit used in the communication system shown in FIG. 1;

FIG. 4 is a block diagram illustrating a GCC code transmission unit according to the method of the present invention.

FIG. 5 is a block diagram illustrating a receiving unit of a GCC code according to the method of the present invention.

FIG. 6 is a block diagram illustrating a transmitting unit of an MMC code.

FIG. 7 is a block diagram illustrating an MMC code receiving unit.

FIG. 8 is a diagram showing a communication procedure in the case of a read cycle.

FIG. 9 is a diagram showing a communication procedure in the case of a write cycle.

FIG. 10 is a diagram showing a communication procedure in the case of an interrupt cycle.

FIG. 11 is a diagram showing a communication procedure in the case of a DMA cycle.

FIG. 12 is a diagram showing a communication procedure in the case of an EMG cycle.

13 is a waveform chart showing waveforms of respective parts in the transmission unit shown in FIG.

14 is a waveform chart showing waveforms of respective parts in the receiving unit of the MMC code shown in FIG.

FIG. 15 is a waveform chart showing waveforms of respective parts in a GCC 4 code transmitting section of the method of the present invention shown in FIG. 4;

16 is a waveform diagram showing the waveform of each portion in the transmit portion of GCC 2 code of the present invention the method shown in FIG.

17 is a waveform diagram showing a waveform of each part in the receiving part of the GCC 4 codes of the present invention the method shown in FIG.

FIG. 18 is a waveform chart showing waveforms of respective parts in a GCC 2 code receiving unit of the method of the present invention shown in FIG. 5;

FIG. 19 is a configuration diagram of a distributed controller system.

FIG. 20 is a configuration diagram of a centralized controller system.

FIG. 21 is a configuration diagram of an I / O intensive controller system in which a CPU bus is extended.

FIG. 22 is a configuration diagram of an I / O intensive controller system using a communication-only interface.

FIG. 23 is a diagram illustrating a communication procedure when the main operation unit reads data of a selected I / O unit.

FIG. 24 is a diagram showing a communication procedure when the main arithmetic unit writes data to a selected I / O unit.

[Explanation of symbols]

 26A, 26B, 26C Processing unit 28 Common transfer chamber 30A, 30B Cassette room 32 Cassette 34 Input device 36 Display 38 Master side control unit 40A, 40B, 40C Slave side control unit 42 Serial line (transmission line) 44M, 44S High speed communication Interface unit 46M, 46S Bus interface 48 CPU bus 50 Bus terminator

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-296434 (JP, A) JP-A-6-261092 (JP, A) JP-A-2-143642 (JP, A) JP-A-59-296 123344 (JP, A) JP-A-57-136843 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 25/02

Claims (4)

(57) [Claims] When encoding digital information and transmitting it through a transmission line composed of a plurality of lines, parallel data to be transmitted is made of n bits (n is 2 or more).
And serializing the n-bit serial data into 2 ⁿ transmission lines.
And one of the 2 ⁿ transmission lines is one transmission line.
A coding method that changes each time a packet is transmitted serially . 2. The method of claim 2, wherein ⁿ  1 bit of the transmission line
One transmission line that changes each time serial transmission is performed
Is uniquely determined according to the value of n-bit data.
The encoding method according to claim 1, wherein the encoding method comprises: 3. When the transmission is completed, ⁿ  Book transmission line
2. The method according to claim 1, wherein the signals are sequentially turned high one by one.
Is the encoding method described in 2. 4. The method according to claim 1, wherein n is 2.
Item 4. The encoding method according to any one of Items 1 to 3.