JP3025870U - Peripheral device connector - Google Patents

Abstract

(57) Abstract: A peripheral device is always provided with a plug having a pin array that can efficiently and quickly provide the processing device with information necessary for determining the communication system of the peripheral device by the processing device. There is provided a peripheral device connector capable of smoothly communicating between a processing device and a peripheral device by a communication system unique to the above. A connector used to connect a peripheral device to a processing device. This connector has a plug connector that is detachably connected to a socket connector of the processing apparatus. This plug connector has 9 connector pins arranged in a row that are in contact with the 9 pins of the socket respectively, and pin 1 is the power supply potential and pin 9 is the ground potential from the processor. Supplied, pin 4 and 5
A control signal is supplied to the No. pin from the processing device, and a data signal corresponding to the communication system of the peripheral device is supplied to the processing device through at least one of the second pin, the third pin, the seventh pin and the eighth pin. .

Description

[Detailed description of the device]

[0001]

[Technical field to which the device belongs]

 The present invention relates to a connector for connecting a peripheral device to a processing device such as an image processing device.

[0002]

[Prior art]

 Generally, an image processing apparatus is known as an apparatus for displaying an image that changes with the passage of time on a display such as a television receiver (hereinafter, referred to as “monitor”), and a typical one of them is shown. As one, a game machine is known.

This game machine has, as basic components, a game machine main body (game device) that mainly executes image processing and the like, and also executes various processing such as control of peripheral devices, and a game machine. It is composed of an operation panel as a peripheral device electrically connected to the main body of the machine. Peripheral devices are also called peripherals.

When the game machine main body to which a monitor is connected is operated, an image of the game development is displayed on the screen of the monitor, and a sound suitable for the game development is reproduced from the speaker of the monitor to play the desired game. be able to.

In this type of game machine, since it is necessary to realize a wide variety of game contents, various peripheral devices are connected to the game machine body. Peripheral devices are devices that perform functions such as inputting desired data to the main body of the game machine or receiving and displaying data from the main body of the game machine.

Various interfaces are provided between the peripheral device and the main body of the game machine, but the communication method between the main body of the game machine and the peripheral device is different depending on the type and model of the peripheral device. Therefore, it is necessary for the main body of the game machine to obtain information (peripheral equipment identification data) regarding the type and model of peripheral equipment.

As a conventional method in which the main body of the game machine recognizes the type and model of the peripheral device connected to the main body of the game machine, when a device select signal of logic “1” is given to the peripheral device from the main body of the game machine. The logic value obtained from the data signal line of the peripheral device and the logic value obtained from the data signal line of the peripheral device when the device select signal of logic "0" is given from the game machine body to the peripheral device. A method has been proposed in which the type and model of the peripheral device is determined based on the value (see, for example, Japanese Patent Laid-Open No. 2-62618).

[0008]

[Problems to be solved by the device]

 However, in the above-mentioned conventional determination method, only the type and model of the peripheral device is determined according to the logical value obtained from the data signal line, and the communication method itself of the peripheral device is determined. However, there is a problem in that it may not be possible to perform data transmission with the peripheral device or control of the peripheral device by a communication method optimal for the peripheral device.

Therefore, in order to solve such a problem, the present invention provides a pin capable of efficiently and promptly providing the processing device with information necessary for the processing device to determine the communication method of the peripheral device. It is an object of the present invention to provide a peripheral device connector that includes a plug having an array and is capable of performing smooth communication between a processing device and a peripheral device by a communication method unique to the peripheral device.

[0010]

[Means for Solving the Problems]

 In order to achieve such an object, a device according to claim 1 is a connector for connecting a peripheral device to a processing device, the connector being detachably connected to a socket connector of the processing device. There is a plug connector, and this plug connector has nine connector pins arranged in a row that respectively come into contact with the nine pins of the socket. Of these connector pins, the first pin has a power supply potential. The ground potential is supplied to the 9th and 9th pins from the processor, the control signal is supplied to the 4th and 5th pins from the processor, and the 2nd pin, 3rd pin, 7th pin and 8th pin are supplied. The data signal according to the communication system of the peripheral device is supplied to the processing device through at least one of the pins.

According to a second aspect of the present invention, in the peripheral device connector, the control signal is transmitted through the 6th pin, and the data signal of the 3-wire handshake communication system is transmitted through the 2nd pin, the 3rd pin, the 7th pin and the 8th pin. It is characterized in that it is used by connecting to a peripheral device that generates.

According to a third aspect of the present invention, in the peripheral device connector, the pin 6 is connected to the pin 5 at the same potential as the pin 5, and the clock is passed through the pin 2, the pin 3, the pin 7 and the pin 8. It is characterized in that it is used by connecting to a peripheral device that generates data in the deparallel communication system.

According to a fourth aspect of the present invention, in the peripheral device connector, the second pin is connected to the same potential as the first pin, and the sixth pin to the eighth pin are connected to the same potential as the ninth pin. It is used by connecting to a peripheral device which generates data of the clocked serial communication system through the pin No. 2, and is used by being connected to the peripheral device according to claim 1.

Further, the peripheral device connector according to claim 5 is used by connecting to a peripheral device which requires a 2-bit data select signal through pins 4 and 5. To do.

Further, the peripheral device connector according to claim 6 has a plug connector which is detachably connected to a socket connector of the processing device, and the plug connector contacts the nine pins of the socket, respectively. It has 9 connector pins arranged in rows. Of these connector pins, the power supply potential is supplied to pin 1 and the ground potential is supplied to pin 9 from the processor, respectively, and pin 2 is supplied. Is connected to pin 1 at the same potential, pins 6 to 8 are connected to pin 9 at the same potential, and one cable for either pin 1 or pin 6 One cable is connected to any of Pins 9 to 9, and a cable is connected to Pins 3 to 5, respectively, and control signals are transmitted through Pins 4 and 5 and Pin 3 is used. Clocked through pins It is characterized by having a connector plug having a pin array configured so that data of a serial communication system is supplied from a peripheral device to a processing device.

Communication methods adopted in various peripheral devices include a three-wire handshake communication method, a clocked parallel communication method, and a clocked serial communication method. Further, as will be described later, there is a TH / TR selection communication system that requires a 2-bit data select signal through pins 4 and 5.

In the peripheral device adopting the 3-wire handshake communication system, a device select signal line for selecting a peripheral device, a data request signal line for requesting data, and a peripheral device response signal line for indicating a response from the peripheral device. Since multiple data signal lines for parallel data transmission are required, it is necessary to use all the pins of the peripheral device plug connector independently. Peripheral devices that use the TH and TR selection communication methods require two data selection signal lines and have the same pin arrangement structure of the plug connector as the three-wire handshake communication method.

In the peripheral device adopting the clocked parallel communication system, the data request signal line and the peripheral device response signal line of the plurality of signal lines described above can be used by being short-circuited. Further, in the peripheral equipment adopting the clocked serial communication system, only the peripheral equipment select signal line, the data request signal (for example, clock signal) line, and one data signal line for serial data transmission are required.

That is, the present invention is directed to this because the number and position of the pins used in the plug of the connector for connecting the processing device and the peripheral device depend on the communication system.

The present invention determines the communication method by determining the relationship between the number of pins and the position in the plug of the peripheral device connector required for communication between the processing device and its peripheral device and its logical value. The connector pins of the peripheral device connector plugs are arranged so that the required logic values can be efficiently transmitted to the processor. That is, the connector pins of the plug of the peripheral device connector are arranged as described in claim 1.

[0021] The peripheral device connector is used as a peripheral device that generates data for each of the three-wire handshake communication system, the clocked parallel communication system, the clocked serial communication system, and the TH / TR selection communication system. By being connected, the processing device itself can quickly determine the communication method of the peripheral device, and smooth communication with the peripheral device is performed based on the communication method unique to the peripheral device. I did it.

[0022]

[Embodiment of device]

 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an external view of a game machine 1 to which the present invention is applied. The game machine 1 includes a processing device body 2 and two operation panels 3a and 3b as peripheral devices. The processing device 2 has connector ports 4a and 4b for connecting peripheral devices. Socket connectors 4as and 4bs are provided at the connector ports of the processing apparatus. Plug connectors 4ap and 4bp provided at the other ends of the cables 5a and 5b, one ends of which are connected to peripheral devices, can be attached to and detached from the socket connectors 4as and 4bs, respectively.

Operation panels 3a and 3b are connected to the plug connectors 4ap and 4bp via cables 5a and 5b, respectively. When the plug connectors 4ap and 4bp are inserted into the socket connectors 4as and 4bs, respectively, the operation panels 3a and 3b are connected to the internal circuit of the processing apparatus main body 2 via the cables 5a and 5b.

Although not shown, the processing device main body 2 is provided with a video output terminal and an audio output terminal. The video output terminal and the video input terminal 7a of the television receiver (monitor) 6 are connected to each other by a cable 8a. The sound output terminal and the sound input terminal 7b of the monitor 6 are connected to each other by a cable 8b.

A CD-ROM drive 9 is provided in the processing device body 2. A cartridge connecting portion 10 into which a ROM cassette or the like (not shown) is inserted is provided behind the CD-ROM drive 9 in the drawing.

The processing device main body 2 executes various processes such as control of peripheral devices in addition to image processing and sound processing. The operation panels 3a and 3b provide operation signals to the processing device body 2. Furthermore, the video signal and the audio signal formed by the processing device main body 2 are given to the monitor 6 via the cable 8a and the cable 8b, respectively.

FIG. 2 is a block diagram showing a configuration example of the processing device main body 2 of the game machine 1. In the figure, the processing apparatus main body 2 is roughly divided into a processing block 11, a video block 12, an audio block 13, and an auxiliary block 14. A cartridge interface (cartridge I / F) 15 is provided in the cartridge connecting section 10, and a compact disc interface (CD I / F) 16 is provided in the auxiliary block 14.

The processing block 11 includes a main processing unit (CPU) 21, a RAM 22, a ROM 23, a system control unit 24, and a sub CPU 25. A RAM 22, a ROM 23, a system control unit 24, and a sub CPU 25 are connected to the main CPU 21 via a bus line 26.

The main CPU 21 is also connected to the video block 12, the sound block 13, the cartridge I / F 15, and the CD I / F 16 via a bus line 26, a system control unit 24, and a bus line 17. A CD-ROM drive 9 is connected to the CD I / F 16 of the auxiliary block 14.

The main CPU 21 is responsible for the control of the entire system, is equipped with an arithmetic unit equivalent to a digital signal processor (DSP), and improves the arithmetic capacity.

The RAM 22 has a 32 Mbit area as a whole, and a 16 Mbit area is allocated to the main CPU 21, for example. The other area of the RAM 22 is allocated for the video block 12 and the sound block 13. The ROM 23 stores an initial program for hardware, a ROM cassette, and an initial program for a CD-ROM.

The system control unit 24 plays a role of a co-processor of the main CPU 21, and smoothly executes an interface function between the main CPU 21 and the video block 12, the audio block 13, and the auxiliary block 14.

The sub CPU 25 resets the entire system when the power is turned on or the reset button is pressed, and the peripheral devices (here, the operation panel 3a (3b), the cable 5a (5b), and the plug connector 4ap (4bp)) are reset. Data collection) and control of peripheral devices. Further, the sub CPU 25 can change the clock frequency of the entire system.

Further, the sub CPU 25 is provided with a connection switching means 40. This connection switching means 40 connects peripheral equipment such as operation panels 3a and 3b connected to the socket connectors 4as and 4bs of the connector ports 4a and 4b to the CPU core 31 or the main CPU 21 of the sub CPU 25 side. Switch to connect.

The video block 12 forms a video signal based on a video control signal supplied from the main CPU 21 via the system control unit 24, and supplies the video signal to the monitor 6 via the cable 8a. As a result, the image is displayed on the display of the monitor 6.

The sound block 13 forms a digital sound signal based on a sound control signal given from the main CPU 21 via the system control unit 24, and converts the digital sound signal into an analog sound signal by a digital analog (DA) converter. Then, it is given to the monitor 6 via the cable 8b. As a result, the sound is reproduced from the sound reproducing section of the monitor 6.

Next, the configuration of the sub CPU 25 will be described with reference to FIG. FIG. 3 shows the overall configuration of the sub CPU 25 for peripheral device management control. In the figure, the sub CPU 25 is connected to the main CPU 21 via a bus line 26. The sub CPU 25 includes a CPU core 31, a ROM 32, a RAM 33, a register table 34, a register group 35, a multiplexer 36, and an I / O interface 37.

Note that, specifically, the register group 35, the multiplexer 36, and the I / O interface 37 are each composed of a circuit for two channels, but in FIG. 3, only one channel is displayed and described. To do.

The CPU core 31 can be composed of, for example, a 4-bit CPU. The CPU core 31 is connected to the ROM 32, and the programs required for the CPU core 31 are supplied from the ROM 32. A RAM 33, a register table 34, and a register group 35 are connected to the CPU core 31 via a bus line 38. The register group 35 is connected to the I / O interface 37 via the multiplexer 36. The register group 35 and the multiplexer 36 constitute the connection switching means 40 described above.

The register group 35 is roughly divided into a main CPU register group 351, a sub CPU register group 352, and an I / O selection register (I / O switch) 353.

One terminal of the main CPU register group 351 is connected to the main CPU 21 via the bus line 39 and the bus line 26, and the other terminal is connected to one terminal of the multiplexer 36. .

One terminal of the sub CPU register group 352 is connected to the CPU core 31 via the bus line 38, and the other terminal is connected to the other terminal of the multiplexer 36.

The common terminal of the multiplexer 36 is connected to the I / O interface. In the peripheral ports, that is, the connector ports 4a and 4b, the socket connectors 4as and 4bs for connecting peripheral devices are connected to the I / O interface 37 via nine lines, respectively. The multiplexer 36 connects peripheral devices such as the operation panels 3a and 3b to the CPU core 31 via the register group 352 and the bus line 38 in accordance with the setting of the I / O selection register 353 of the register group 35. Alternatively, it is connected to the main CPU 21 via the register group 351, the bus line 39, and the bus line 26.

When the CPU core 31 is connected to the peripheral device via the multiplexer 36, the CPU core 31 has “peripheral ID-1” + “peripheral ID-2” + “data size” + “data”. While communicating with peripheral devices in this order, the ID (identification data) is used to determine the communication method, and then data collection, transmission, and exchange can be performed. In this embodiment, the "peripheral ID-1" is composed of 4-bit data, and is data representing a communication method according to the type of peripheral device.

The “peripheral ID-2” also consists of 4-bit data, which is data representing a type of peripheral device, and is a model focused on the signal form (analog amount, digital amount, etc.). Is data representing. The "data size" represents the total number of bytes of peripheral device data, and is represented by (DSIZE _{0 to} DSIZE ₃ ) in the later-described figures. “Data” is the data from the peripheral device with the total number of bytes indicated by the data size value. Since the CPU core 31 is a 4-bit device in the present embodiment, it takes in data every 4 bits with respect to the total number of bytes of data.

FIG. 4 shows a block configuration of the connector ports 4a and 4b for connecting peripheral devices having the socket connectors 4as and 4bs, and FIGS. 5A to 5C show configurations of the plug connectors 4ap and 4bp of the peripheral devices. Each is shown.

FIG. 4 shows two-channel connector ports 4a and 4b. Nine pins (pin numbers 1 to 9) are provided on each socket connector 4as and 4bs of each connector port. Each pin is individually electrically connected to the I / O interface 37 by nine wires. However, as shown in FIG. 4, the first pin is connected to Vcc and the ninth pin is connected to the ground potential.

Pins 1 to 9 of each of the socket connectors 4as and 4bs are electrically independent. Each of the plug connectors 4ap and 4bp (see FIGS. 5 (1) to 5 (3)) also has nine pins of pin numbers 1 to 9, and when they are inserted into the socket connectors 4as (4bs), they face each other. The pins that make contact with each other are electrically connected. The plug connectors 4ap and 4bp are connected to the operation panels 3a and 3b via the cables 5a and 5b, respectively, as described above.

Table 1 summarizes the signal names assigned to pins 1 to 9 and their functions.

[0050]

[Table 1]

As shown in the table and FIGS. 4 and 5, in each of the connector ports 4a and 4b, the 4th to 6th pins are mainly assigned to transmission and reception of control signals. The 4th pin is the first control pin and is used for transmitting the device select signal TH from the processing device main body 2 to the peripheral devices (for example, the operation panels 3a and 3b). The fifth pin is a second control pin and is used for transmitting the data request signal TR from the processing device main body 2 to the peripheral device. Pin 6 is a third control pin and is used to transmit a peripheral device response signal TL from the peripheral device to the processing apparatus main body 2.

Pins 2, 3, 7 and 8 are mainly allocated for data signals. The second pin (first data pin) is the bit data D, the third pin (second data pin) is the bit data U, and the seventh pin (third data is the third data). The pin for data) is assigned to transmit the bit data R, and the pin 8 (pin for fourth data) is assigned to transmit the bit data L, respectively. The signal R represents the third bit of data, L represents the second bit, D represents the first bit, and U represents the zeroth bit. The signal lines of these data R, L, D, and U can freely set the input / output direction of data according to the type of peripheral device.

Pins 2 to 8 are connected to the power supply Vcc via the resistor 411, respectively, so that the signals TH, TR, TL, R, L, D, and U are pulled up to the level of the power supply Vcc. There is.

When the plug connectors 4ap and 4bp are not connected to the socket connectors 4as and 4bp, the voltage levels of the 2nd to 8th pins become equal to the voltage value (logic value “1”) of the power supply Vcc. As a result, when all the signal lines (for example, the lines of data R, L, D, U) are in the logical value "1", it is determined that the peripheral devices are not connected to the socket connectors 4as, 4bs. The CPU 25 can judge.

Pins 5 and 6 are mainly for transmitting control signals between the processing apparatus main body 2 and the peripheral devices as described above, but the peripheral devices are clocked (clock synchronous type) described later. When a parallel communication system or a clocked serial communication system is adopted, it can also be used for transmitting a data signal.

Pin 1 is assigned to the power supply voltage Vcc (voltage value: + 5V), and Pin 9 is assigned to the ground potential GND (voltage value = 0).

On the other hand, the plug connectors 4ap and 4bp on the peripheral device side have the pin configuration shown in either FIG. 5 (1) or FIG. 5 (3). These figures show the pin arrangements most suitable for the communication method adopted by the peripheral equipment. Figure 1 (1) shows the pin arrangements for the TH / TR selection communication method and the 3-wire handshake communication method. 2) shows the pin arrangement in the clocked parallel communication system, and FIG. 3C shows the pin arrangement in the clocked serial communication system.

The reason for adopting such various pin arrangements is that there are a wide variety of peripheral devices such as control PADs, mice, keyboards, modems, storage devices, etc. Different peripheral devices have different communication systems. Because there are many. Typical communication methods include TH / TR selection method, 3-wire handshake method, clocked parallel method, and clocked serial method.

Among these, in the peripheral device adopting the TH / TR selection method and the 3-wire handshake method, it is necessary to electrically use all the pins in the connector port 4a (4b) independently. Therefore, as shown in FIG. 5 (1), all the pins 1 to 9 of the plug connector 4ap (4bp) are not short-circuited with each other and are electrically independent.

On the other hand, in the peripheral device adopting the clocked parallel system, the pin 5 for the data request signal TR and the pin 6 for the peripheral device response signal TL are as shown in FIG. 5 (2). It is used by short-circuiting to. Due to this short circuit, the control signal (data request signal TR) of the logical value sent to the 5th pin always returns instantaneously as the control signal (peripheral device response signal TL) of the same logical value from the 6th pin. The processing device main body 2 recognizes the signal state of the data request signal TR = peripheral device response signal TL and can determine that the communication system is the clocked parallel system. When the device select signal line TH from the processing device main body 2 to the operation boards 3a, 3b is set to a predetermined logical value and a clock is given to the data request signal line TR, the peripheral device response signal TL (= TR) is instantly sent. Since the data can be obtained immediately in the processing device main body 2, the data R, L, D and U can be immediately received from the operation panels 3a and 3b in synchronization with the clock via the data signal line. Is output to the side.

With respect to this clocked parallel type peripheral device, the processing device main body 2 monitors the peripheral device response signal TL to determine whether the peripheral device is not connected or the like. When the data request signal TR is transmitted from the processing apparatus main body 2, the peripheral device response signal TL having the same logical value as the data request signal TR is instantly returned due to the short circuit of the pin 5 and the pin 6 described above. Therefore, if the peripheral device response signal TL having the same logical value does not return even after a lapse of a certain period from the transmission of the data request signal TR, the processing device main body 2 judges that the peripheral device is not connected. You can

Further, in the case of a peripheral device adopting the clocked serial system, as shown in FIG. 5C, basically only one signal line (U) is required to transmit data. Moreover, the control signal line may be two lines of the device select signal TH and the data request signal TR for transmitting the clock. Further, in order to judge this communication method, logical values of data R = L = “0”, D = “1”, U = “0” are required. Therefore, in each pin arrangement of the plug connectors 4ap and 4bp, there is one pin 3 for transmitting the data U, pin 4 for the device select signal TH, and pin 5 for the data request signal TR. The pins are independently secured and the remaining unused signal line pins and control line pins are short-circuited to the pin 1 of the power supply Vcc and the pin 9 of the ground potential GND. More specifically, as shown in FIG. 5C, the second pin is short-circuited to the first pin of the power supply Vcc, and the sixth to eighth pins are short-circuited to the ninth pin of the ground potential GND, and TL = R = L = always. The state is set to "0" and D = "1". As a result, logical values representing the clocked serial communication system are obtained at the pins of the connector ports 4a and 4b, and these are transmitted to the processing device main body 2.

As described above, certain conditions are satisfied for the number and position of pins (in other words, the number and type of signal lines) required for the connector ports 4a and 4b according to various communication systems, and this is satisfied. Therefore, the pin array of the plug connector for each communication method described above is formed. That is, the relationship between the number of pins and the pin positions of the plug connector required for the transmission of control signals and data and the logical value on the signal line is predetermined for each communication method, and the logical value necessary for determining the communication method is set in the processing device. The plug connector has a pin arrangement that enables effective transmission to the main body 2. As a result, the processing device main body 2 uses the logical value appearing on the pins of the connector ports 4a and 4b, that is, a predetermined signal line, and determines the communication method by determining what the logical value is. You can judge.

The above-described pin short circuit structure shown in FIGS. 5 (2) and 5 (3) is short-circuited by a short wire at the connection portion between the pin in the plug connector 4ap (or 4bp) and the cable 5a (or 5b). It suffices to short-circuit the printed circuit board provided in the plug connector 4ap (or 4bp). In this case, the number of wires of the cable 5a (or 5b) connecting the plug connector 4ap (or 4bp) and the peripheral device can be reduced. The advantage of the reduction in the number of lines becomes particularly remarkable when the communication system of the peripheral device is the clocked serial system, and the total of three control lines and data lines is sufficient.

Further, for the pin short circuit, the connection part of the cable 5a (or 5b) may be short-circuited by a short-circuit wire inside the peripheral device, or a printed board or the like having a predetermined short-circuit wiring may be used. In this case, the number of wires of the cable 5a (or 5b) cannot be reduced, but the shape of the plug can be made smaller than in the case where the short-circuit structure is provided in the plug.

Particularly, when the pin arrangement of the clocked serial type plug connector shown in FIG. 5C is realized inside the peripheral device, the number of wires of the cable 5a (or 5b) cannot be reduced. However, since the wire not involved in signal transmission is short-circuited to the power supply line and the ground electrode, it is possible to reduce the influence of noise and the like.

Next, the operation of the processing device body 2 including the function of determining the communication system of the peripheral device will be described with reference to FIGS. 3 to 13 and Tables 2 to 5.

As shown in FIG. 6, when the sub CPU 25 starts its operation, it outputs a device selection signal TH = "1" and a data request signal TR = "1" (step S101). Next, the CPU core 31 of the sub CPU 25 takes in the logical values of the data R, L, D, and U from the peripheral device and stores them in a predetermined area of the RAM 33 (S102). Next, the CPU core 31 outputs the device select signal TH = "0" and the data request signal TR = "1" again (S103). Again, the logical values of the data R, L, D, U are fetched into the CPU core 31 and stored in a predetermined area of the RAM 33 (S 104; see period T10 in FIG. 11 and period T20 in FIG. 12).

Next, the CPU 31 calculates the peripheral ID-1 (S105). This peripheral ID-1 can be calculated using the following formula 1.

[Equation 1] [ID-1] = {(R when TH = 1) or (L when TH = 1)} × 8h + {(D when TH = 1) or (TH = 1) U)} × 4h + {(R when TH = 0) or (L when TH = 0)} × 2h + {(D when TH = 0) or (TH = 0 U)} × 1h where h is a hexadecimal suffix.

The CPU core 31 determines the peripheral ID-1 based on the calculation result [ID-1] calculated in this way (S106 to S110). Table 2 shows the correspondence between peripheral device types and peripheral ID-1.

[0072]

[Table 2]

The procedure for determining the peripheral ID-1 will be described in detail. First, the CPU core 31 determines whether or not the calculation result [ID-1] is, for example, Bh. When it is determined that the calculation result [ID -1] is, for example, Bh (S106; YES), the peripheral device is determined to be the standard control PAD, as can be seen from Table 2, the CPU core 31 Moves to the processing of the standard control PAD access sub routine (S111).

However, when the CPU core 31 determines that the result of the operation result [ID-1] is not Bh (S106; NO), the CPU core 31 next determines whether the operation result [ID-1] is, for example, 5h. It is determined (S107).

Therefore, when the CPU core 31 determines that the calculation result [ID-1] is 5h (S107; YES, see Table 2), the processing is transferred to the peripheral # 1 access subroutine in FIG. (S112).

On the other hand, when it is determined that the calculation result [ID-1] is not 5h (S107; NO), the sub CPU 25 then determines whether the calculation result [ID-1] is, for example, 7h. . When it is determined that the calculation result [ID-1] is 7h (S108; YES, see Table 2), the sub CPU 25 shifts the processing to the adapter access routine (S113 in FIG. 6).

On the other hand, when it is determined that the calculation result [ID-1] is not 7h (S108; NO), the sub CPU 25 determines whether the calculation result [ID-1] is, for example, 3h ( S109). When it is determined that the calculation result [ID-1] is 3h (S109; YES, see Table 2), the sub CPU 25 shifts the processing to the mouse access subroutine (S114).

On the other hand, when the calculation result [ID-1] is not 3h (S109; NO), it is determined whether the calculation result [ID-1] is Dh (S110). When it is determined that the operation result [ID-1] is Dh (S110; YES, see Table 2), the process proceeds to the process of the 3/6 button access routine (S115). If the value of the operation result [ID-1] is, for example, Fh, it is not connected, and if it is a value other than the above, it is treated as unknown (S116, see Table 2).

Next, the peripheral # 1 access subroutine will be described with reference to FIG. 7 and Table 3. Table 3 shows a bit array used for determining the communication method for the peripheral device.

[0080]

[Table 3]

The CPU core 31 that has proceeded to the processing of this access subroutine first determines the communication method and the like based on the logical values of the data D and U that were acquired previously (S201 to S203). When the logical values of the data D and U are, for example, “D = 0” and “U = 1” (S201; YES), the CPU core 31 determines that the communication method of the peripheral device is the 3-wire handshake method ( (See Table 3) The procedure moves to the 3-line handshake type access subroutine (S204).

On the other hand, when the logical values of the data D and U are not “D = 0” and “U = 1” (S201; NO), the CPU core 31 now selects, for example, “D = 1” and “U”. It is determined whether or not = 0 ”(S202). Here, when it is determined that “D = 1” and “U = 0” (S202; YES, see Table 3), the CPU core 31 shifts the processing to the access subroutine of the clocked serial communication method (S205). ).

Furthermore, when “D = 1” and “U = 0” are not satisfied (S202; NO), the CPU core 31 determines that the logical values of the data D and U are “D = 1” and “U = 1”. It is determined whether there is any (S203). When the CPU core 31 determines that "D = 1" and "U = 1" (S203; YES, see Table 3), the CPU core 31 shifts the processing to the access subroutine of the clocked parallel communication method (S206).

If a positive determination result is not obtained even after performing the determinations in S201 to S203 (that is, NO in S201, NO in S202, NO in S203), the CPU core 31 determines that the peripheral device Is determined not to be connected (S207), and the processing of this subroutine ends.

Next, each process (S204, S205, S206) branched from the subroutine shown in FIG. 7 will be described in detail. First, the access subroutine of the 3-wire handshake communication system shown in FIG. 8 will be described with reference to the timing chart shown in FIG. In FIG. 11, the horizontal axis represents time t and the vertical axis represents the state of each signal.

In the period T11 of FIG. 11, the CPU core 31 takes in the peripheral ID-2 (S301). When the logical values (ID ₀ , ID ₁ , ID ₂ , ID ₃ ) of the data R, L, D, U are taken into the CPU core 31 at the timing in the period T11, the logical values (ID ₀ , ID ₁ , ID ₂ , ID ₃ ) is matched with “0h to Fh” (see “ID” column in Table 4).

[0087]

[Table 4]

In other words, the CPU core 31 determines each device by referring to Table 4 with the value of the peripheral ID-2 taken in. For example, the CPU core 31 determines that if the peripheral ID-2 is 0h, it is a digital device, 1h is an analog device, 2h is a pointing device, and 3h is a keyboard.

Upon completion of this determination, the CPU core 31 takes in the data size (displayed as DSIZE _{0 to} DSIZE ₃ in the figure) in the period T12 (S302).

When the data size is known, the CPU core 31 takes in the data after the period T13 in FIG. 11 (S303). Then, the CPU core 31 determines whether or not the data has reached the data size, and if the data has not reached the data size (S304; NO), the CPU core 31 fetches the data again (S303). When the data reaches the data size (S304; YES), the CPU core 31 ends the subroutine.

Next, the access subroutine of the clocked parallel communication system shown in FIG. 9 will be described with reference to the timing chart shown in FIG. In the figure, the horizontal axis represents time t, and the vertical axis represents the state of each signal. The clocked parallel communication system has almost the same contents as the timing chart of FIG. 11, as shown in the timing chart of FIG. The difference is that the data request signal TR and the peripheral device response signal TL operate at the same timing due to a pin short circuit.

In the peripheral # 1 access subroutine shown in FIG. 7 described above, when it is determined that the logical values of the data D and U are, for example, “D = 1” and “U = 0” (S202), the clock The access subroutine of the parallel method is started (S205).

First, the CPU core 31 takes in the peripheral ID-2 in the period T21 of FIG. 12 (FIG. 9, S401). That is, when the logical values (ID ₀ , ID ₁ , ID ₂ , ID ₃ ) of the data R, L, D, U are taken into the CPU core 31 at the timing in the period T21, the logical values (ID ₀ , ID ₁ , It is determined that ID ₂ and ID ₃ ) match any of “0h to Fh” (column “ID” in Table 4). Then, the CPU core 31 determines each device by referring to the value of the taken peripheral ID-2 in Table 4. For example, if the peripheral ID-2 is 0h, it is determined to be a digital device, 1h is an analog device, 2h is a pointing device, and 3h is a keyboard.

When this determination is completed, the CPU core 31 takes in the data size (displayed as DSIZE _{0 to} DSIZE ₃ in the figure) in the period T22 (S402).

When the data size is known, the CPU core 31 fetches the data after the period T23 in FIG. 12 (S403). Then, the CPU core 31 determines whether the data has reached the data size, and if it has not reached the data size (S404; NO), the CPU core 31 fetches the data again (S403). When the CPU core 31 determines that the data has reached the data size (S404; YES), it ends the subroutine.

Next, the “peripheral ID-2” determination process (S112 in FIG. 6) in the clocked serial communication system will be described with reference to FIGS. Note that FIG. 13 is a timing chart showing the state of signals in the clocked serial communication system, in which the ordinate represents the logical value of each signal TH, TR, U and the abscissa represents the time t 2.

In this communication system, as shown in FIG. 13, when the device select signal TH given to the peripheral device from the CPU core 31 is “0” and the data request signal TR is on / off, Data is obtained from the peripheral device on the line of the data U. The data thus obtained have the values shown in Table 5, for example.

[0098]

[Table 5]

In Table 5, when the device select signal TH is “0” and the data request signal TR 1 is on / off (indicated by arrows pointing up and down), the signals TL, R, L Are all "0" and the signal D is "1", various signals are obtained on the line of the signal U along the time t. In Table 5, when the "TR" column arrow (data requests signal TR is representative that the repeated logic "0""1".) , SMD 3 ... SMD 0, ID 3 ... ID 0 , DSIZE ₃ ... DSIZE ₀ , ... DATA A etc. are obtained (FIG. 10, S501). Among the data obtained from the line of the signal U, and determines the ID-2 based on the logical value of the data ID ₃ ... ID ₀ in light of Table 5.

Upon completion of this determination, the CPU core 31 determines the data size (in Table 5, DSI
(Displayed as ZE _{0 to} DSIZE ₃ ) (S502). When this data size is known, the CPU core 31 of the sub CPU 25 takes in the data after the predetermined period of FIG. 13 (S503). Then, the CPU core 31 determines whether or not the data has reached the fetched data size, and if not (S504; NO), the CPU core 31 fetches the data again (S503). When the CPU core 31 determines that the data has reached the data size (S404; YES), it ends the subroutine.

In this way, the CPU core 31 exchanges signals with peripheral devices, and fetches data (DATA) and the like that follow from the information of peripheral ID-1, ID-2, and data size (DSIZE). .

When data is taken into the CPU core 31 from the peripheral device, the CPU core 31 exchanges data with the main CPU 21 via the register table 34.

In this embodiment, since the pin arrangements of the plug connectors 4ap and 4bp as described above are implemented, the socket connectors 4as and 4bs of the processing apparatus main body 2 can be connected to the socket connectors 4as and 4bs of the processing apparatus main body 2 even when the types of peripheral devices and the communication systems are different. After inserting the plug connectors 4ap and 4bp, the sub CPU 25 of the processing apparatus main body 2 communicates in the order of "peripheral ID-1", "peripheral ID-2", "data size", and "data". The communication method can be automatically determined. Further, since the present embodiment has the pin arrangement as described above, it is possible to perform the transmission of the peripheral ID and the data transmission in the optimum state despite the difference in the peripheral device and the communication method.

In this embodiment, the peripheral CPU is controlled by the sub CPU 25 as an example. However, if the main CPU 21 is directly connected to the peripheral, the main CPU 21 executes all the above processes. May be.

Further, in the case of the clocked parallel communication system, the control signal TR = TL, and in the case of the clocked serial communication system, a specific pin (pin of signals D, TL, R, L) The communication method may be determined based on the signal value.

Further, in the three-wire handshake communication system, the communication system may be determined by utilizing the fact that the control signal TR ≠ TL.

[0107]

[Effect of device]

 As described above, according to the peripheral device connector of the present invention, the relationship between the number and position of the connector pins of the plug connector necessary for communication between the processing device and the peripheral device and its logical value is determined, Since the connector pins of the plug connector of the peripheral device are arranged so that the logical value required to judge the communication system of the device can be efficiently transmitted to the processing device side, the communication system with the peripheral device in the processing device Therefore, it is possible to quickly make a quick decision, and always be able to perform smooth communication with a peripheral device using a communication method unique to the peripheral device.

That is, signals and data can be optimally transferred between the processing device and the peripheral device, and the processing device can optimally control the peripheral device. In addition, depending on whether the communication mode of the peripheral device is the 3-wire handshake method, TH / TR selection method, clocked parallel method, or clocked serial method, the connector pin arrangement of the plug connector corresponding to that method Since the socket connector of the processor is always standard (the pins are electrically independent), it is necessary to replace the socket connector each time the peripheral device changes. It is possible to have versatility.

[Brief description of drawings]

FIG. 1 is a perspective view showing an appearance of a game machine according to an embodiment to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a processing apparatus main body of the same embodiment.

FIG. 3 is a block diagram showing a connection state between a main CPU and a sub CPU.

FIG. 4 is a peripheral circuit diagram of a socket connector at a connector port.

5 (1) to (3) are explanatory diagrams showing pin arrangements of plug connectors according to communication systems of peripheral devices.

FIG. 6 is a flowchart illustrating the operation of the embodiment.

FIG. 7 is a flowchart showing a peripheral access subroutine.

FIG. 8 is a flowchart showing an access subroutine of a three-line handshake communication system.

FIG. 9 is a flowchart showing an access subroutine of a clocked parallel communication system.

FIG. 10 is a flowchart showing an access subroutine of a clocked serial communication system.

FIG. 11 is a timing chart showing the operation of the three-wire handshake communication system.

FIG. 12 is a timing chart showing the operation of the clocked parallel communication system.

FIG. 13 is a timing chart showing the operation of the clocked serial communication system.

[Explanation of symbols]

 1 Game Machine 2 Processing Device Main Body 3a, 3b Operation Panel (Peripheral Equipment) 4a, 4b Connector Port 4as, 4bs Socket Connector 4ap, 4bp Plug Connector 5a, 5b Cable 21 Main CPU 25 Sub CPU 31 CPU Core 37 I / O Interface

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Creator Gen Ikebe 2-5-1 Suwa, Tama-shi, Tokyo Inside the CSK Research Institute, Inc.

Claims (6)

[Scope of utility model registration request] 1. A connector for connecting a peripheral device to a processing device, the connector having a plug connector detachably connected to a socket connector of the processing device,
This plug connector has nine connector pins arranged in a row that respectively come into contact with the nine pins of the socket, and the pin 1 of the connector pins has a power supply potential.
The ground potential is supplied from the processor to the 9th pin, the control signal is supplied from the processor to the 4th and 5th pins, and at least the 2nd pin, the 3rd pin, the 7th pin and the 8th pin. A peripheral device connector characterized in that a data signal according to a communication system of the peripheral device is supplied to the processing device through one. 2. A control signal is connected through a 6th pin to a peripheral device which generates a data signal of a 3-wire handshake communication system through a 2nd pin, a 3rd pin, a 7th pin and a 8th pin for use. The peripheral device connector according to claim 1, wherein the connector is a peripheral device connector. 3. A peripheral device for generating data in the clocked parallel communication system through pins 2, 3, 7, and 8 when pin 6 is connected to the same potential as pin 5. The connector for peripheral equipment according to claim 1, wherein the connector is used by connecting to the. 4. The data of the clocked serial communication system through the third pin in the state where the second pin is connected to the same potential as the first pin and the sixth pin to the eighth pin are connected to the same potential as the ninth pin. The peripheral device connector according to claim 1, wherein the peripheral device connector is used by connecting to a peripheral device that generates a noise. 5. A peripheral device connector, which is used by connecting to a peripheral device requiring a 2-bit data select signal through pins 4 and 5. 6. A connector for connecting peripheral equipment to a processing device, the connector having a plug connector detachably connected to a socket connector of the processing device,
This plug connector has nine connector pins arranged in a row that respectively come into contact with the nine pins of the socket, and the pin 1 of the connector pins has a power supply potential.
The ground potential is supplied to the 9th pin from the processing device, the 2nd pin is connected to the 1st pin at the same potential, and the 6th to 8th pins are connected to the 9th pin and the same potential.
One cable is connected to either pin # 2 or pin # 2, one cable is connected to any of pins # 6 to # 9, and a cable is connected to pins # 3 to # 5, respectively. A control signal is transmitted through pins 4 and 5, and clocked serial communication system data is supplied from a peripheral device to a processing device through a pin 3. Peripheral device connector.