JP2973744B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit for synchronizing the phases of a data signal and a clock signal input from an external circuit, and more particularly to a phase synchronization circuit of a data signal and a clock signal having the same frequency but different phases. .

[0002]

2. Description of the Related Art In a conventional phase locked loop circuit of this type, a phase difference between an input data signal and a clock signal is measured in advance, and based on the measured value, a phase difference is fixed to a signal side circuit whose phase is advanced. A delay element is inserted, and the signal phase on the delay element insertion side is delayed so that the phases of both signals match. Note that a transmission line may be used as the fixed delay element.

[0003]

In the above-mentioned phase locked loop circuit, the phase difference between the data signal and the clock signal is known, and if the difference is not always constant, the phases of the two signals can always be matched. Can not. For this reason, in the conventional phase locked loop circuit, if the phase difference between the data signal and the clock signal becomes different from the above-described measurement when the phase locked loop circuit is used, the phases of the two signals should be matched. There was a problem that can not be.

Accordingly, the present invention has been made to solve the above-mentioned drawbacks of the phase locked loop circuit using the prior art, and can cope with a temporal change of a phase difference between an input data signal and a clock signal. An object of the present invention is to provide a phase synchronization circuit that can make the phases of both signals coincide.

[0005]

A phase synchronization circuit according to the present invention comprises a data signal transmission line for transmitting a data signal input to a data signal input terminal to a data signal output terminal, and a data signal transmission line input to a clock signal input terminal. A clock signal transmission line for transmitting a clock signal having the same cycle as a data signal to a clock signal output terminal; and a clock signal transmission line inserted into one of the data signal transmission line and the clock signal transmission line in response to a control voltage signal. Delay means for delaying the signal passing through the transmission path, and a phase comparison means for comparing the phase of the undelayed signal of the data signal and the clock signal with the phase of the signal delayed by the delay means. The relative advance of the phase of the compared signals together with the phase shift amount of the compared signals from the comparison output of the phase comparing means. It has a phase shift detection means for producing a phase difference signal by detecting the record, and a control voltage generating means for producing said control voltage signal value to eliminate the phase shift amount from the phase difference signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase locked loop circuit according to one embodiment of the present invention. FIG. 4 is an operation explanatory diagram of this embodiment. Hereinafter, the configuration and operation of the phase locked loop circuit will be described with reference to FIGS.

A data signal S1 (see FIG. 4A) having a logical level of either L level or H level is input from an input terminal 7 according to the data content, and the data signal S1 is output without any processing. It is output to 10. On the other hand, a clock signal S2 having the same period as the data signal S1 and having a phase delay from the data signal S1 is input from the input terminal 8 in this embodiment. This signal S2
Is the delay control signal of this circuit, and the digital IC
The signal is delayed by a delay element 3, which is a voltage-controlled variable delay element formed of a circuit, and output to an output terminal 9 as a delayed clock signal S3 (see FIG. 4B). Note that the phase of the delayed clock signal S3 is finally synchronized with the phase of the data signal S1 by control using means described later.
Further, in this phase synchronization circuit, the clock signal S2 may be input to the input terminal 7, the data signal S1 may be input to the input terminal 8, and the data signal S1 may be used as the delayed control signal.

The phase comparator 2 compares the phase of the data signal S1 with the phase of the delayed clock signal S3, and outputs a comparison output S5 synchronized with the oscillation signal S4 from the oscillator 1 (when the signal S1 is at the H level, S5a: Referring to FIG. 4C, when the signal S1 is L
When the level is the level, S5b: see FIG.
Occurs. Here, when the data signal S1 and the delayed clock signal S3 are in phase synchronization, the width of the H level and the L level in the comparison output S5a or S5b are equal, but when the phase is not synchronized, FIG. As shown, the width between the H level and the L level in the comparison output S5a or S5b has a difference of W. This width W indicates the magnitude of the phase shift between the signals S1 and S3. Note that the oscillation signal S4
This frequency determines the phase difference detection sensitivity and phase difference accuracy of the comparison circuit 2, and is suitably about 10 times the frequency of the clock signal S1.

The phase difference detection circuit 5 responds to the data signal S1, the comparison output S5 from the phase comparison circuit 2 and the oscillation signal S4 used as a clock signal, and outputs the comparison output S5 to the clock signal S2 (or the data signal S1). The clock signal S3 is taken out for each cycle, and the phase shift amount detected by the phase comparison circuit 2 and the delay or advance of the phase of the clock signal S3 with respect to the data signal S1 are detected. This phase shift detection result is output to the output terminals 18 and 19 as the serial data phase difference signal S6 (the lower bit is output to the output terminal 18 as the signal S6a: see FIG. 4j, and the upper bit is output as the signal S6b. 19: see i of FIG. 4, where the signal S6 is represented by an NRZ signal). This phase difference detection circuit 5
In the case where the phase of the delayed clock signal S3 is behind the data signal S1 (in the case of this embodiment), the L level portion of the signal S5 appears in the lower bit (signal S6a) according to the magnitude of the phase shift. , The phase of the signal S3 is the data signal S
If it is more than 1, the L level portion of the signal S5 appears in the upper bit (signal S6b) according to the magnitude of the phase shift (in this embodiment, the signal S6b has no phase shift).

The phase difference signals S6a and S6b are ORed with the oscillation signal S4 by OR circuits 6a and 6b, respectively, and the H level of the data signal S1 and the delayed clock signal S3 from the OR circuits 6a and 6b, respectively. The phase difference clocks S7a (see l in FIG. 4) and S7b (see k in FIG. 4) are output for the time.

The phase difference clocks S7a and S7b are UP
/ DOWN input to a control voltage generating circuit 4 composed of a / DOWN counter.
A control voltage signal S8 composed of a base number signal is output to the delay element 3. That is, when the phase of the data signal S1 is advanced, the circuit 4 responds to the phase difference clock 7a by a time corresponding to the phase difference between the data signal S1 and the delayed clock signal S3 (1 in FIG. 4).
A control voltage signal S8 whose count is reduced by W is output. Conversely, if the phase of the data signal S1 is delayed, the circuit 4 responds to the phase difference clock 7b and outputs a control voltage signal S8 whose count is increased by a time corresponding to the phase difference between the signals S1 and S3.

The delay element 3 sets a delay amount according to the magnitude of the control voltage signal S8. As a result, the phases of the data signal S1 and the delayed clock signal S3 match, and the signals S1 and S
3 will be phase-synchronized.

Referring now to the block diagram of FIG.
The phase comparison circuit 2 used in the embodiment of the present invention takes an exclusive OR of the data signal S1 from the input terminal 8 and the delayed clock signal S3 from the output terminal 9 by an exclusive OR circuit (EX-OR) 12. , The phase difference between the two signals S1 and S3 is detected. The signal of this operation result is shaped by D-type flip-flops 13a and 13b using the oscillation signal S4 from the oscillator 1 as a clock signal, and is output from the output terminal 21 as the above-described comparison output S5.

Referring now to the block diagram of FIG. 3 and FIG. 4, the phase difference detection circuit 5 used in the embodiment of FIG. 1 is a serial / parallel converter (S
/ P) 14, the comparison output S5 is input to the data input terminal, the oscillation signal S4 is input to the clock input terminal, and the data signal S1,
That is, for each cycle of the clock signal S2, the comparison output S5 is set to the parallel bit string S51 of the number of bits of the oscillation signal S4.
(If the comparison output is S5a, the parallel bit string S51
a: see e in FIG. 4, and in the case of S5b, replace with a parallel bit string S51b: see f in FIG. The upper 6 bits of the bit string S51 are output from the terminals Q6 to Q11, and the lower 6 bits are output from the terminals Q0 to Q5. The exclusive OR circuit 15 performs an exclusive OR operation on the carry bit (CC) of the S / P 14 with the exclusive OR circuit 15 to provide a phase shift determination bit S52. This exclusive OR operation sets the phase shift determination bit S52 of the same bit string regardless of whether the data signal S1 is at H or L level.

Next, the phase difference detection circuit 5 converts the lower bits of the determination bit S52 to an inversion circuit 1 in order to represent the magnitude of the phase shift of the phase shift determination bit S52 in L level.
6 to produce a phase difference bit S53 (see h in FIG. 4). Here, when the phase of the delayed clock signal S3 is behind the data signal S1 (in the case of this embodiment), the L level portion of the signal S5 appears in the lower bits according to the magnitude of the phase shift, and the signal S3 Is higher than the data signal S1, the L level portion of the signal S5 appears in the upper bits according to the magnitude of the phase shift (in this embodiment, there is no phase shift in the upper bits). As for the phase difference bit S53, the lower bits are subjected to parallel / serial conversion by a parallel / serial converter (P / S) 17a and the above bits are converted to parallel / serial by a parallel / serial converter (P / S) 17b. become.

[0017]

As described above, according to the present invention, the phase difference between the input data signal and the clock signal is detected together with the phase shift amount to detect the phase lead and lag directions, and one of the signals is converted to the phase difference signal. Therefore, the phases of the two signals can be synchronized without knowing the phase difference between the input data signal and the clock signal, and the phase difference between the two signals has a temporal variation. However, there is an effect that it can follow this.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a phase locked loop according to the present invention.

FIG. 2 is a block diagram of a phase comparison circuit 2 used in this embodiment.

FIG. 3 is a block diagram of a phase difference detection circuit 5 used in this embodiment.

FIG. 4 is a signal waveform diagram of each part of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Oscillator 2 Phase comparison circuit 3 Delay element 4 Control voltage generation circuit 5 Phase difference detection circuit 6a, 6b OR circuit 7, 8 Input terminal 9, 10, 18, 19, 21 Output terminal 1215 Exclusive OR circuit (EX- OR) 13a, 13b D-type flip-flop 14 Serial / parallel converter (S / P) 16 Inverting circuit 17a, 17b Parallel / serial converter (P /
S)

Claims (2)

(57) [Claims] 1. A data signal transmission line for transmitting a data signal input to a data signal input terminal to a data signal output terminal, and a clock signal having the same cycle as the data signal input to a clock signal input terminal. A clock signal transmission line to be transmitted to a terminal, and delay means inserted into one of the data signal transmission line and the clock signal transmission line to delay the signal passing through the inserted transmission line in response to a control voltage signal Phase comparison means for comparing the phase of the undelayed signal of the data signal and the clock signal with the phase of the signal delayed by the delay means; and The phase shift that produces the phase difference signal by detecting the relative advance and delay of the phase of the compared signals together with the phase shift amount of the two signals. Detection means, have a control voltage generating means for the resulting control voltage signal value to eliminate the phase shift amount from the phase difference signal, the phase comparison means, the logic of the two signals the are phase compared
An OR circuit for taking a sum, and an integer of a period of the clock signal
A double clock is supplied and the output signal of the OR circuit is
Means for controlling phase sensitivity and accuracy . 2. Data input to a data signal input terminal
Data signal transmission line for transmitting signals to data signal output terminals
And the data signal input to the clock signal input terminal.
Clock signal with the same cycle as the clock signal to the clock signal output terminal.
A clock signal transmission line for transmission, and the data signal transmission line
And inserted into one of the clock signal transmission lines.
Through the inserted transmission line in response to the control voltage signal
Delay means for delaying the signal;
And the position of the non-delayed signal of the clock signal.
The phase is compared with the phase of the signal delayed by the delay means.
The phase comparison means to be compared and the comparison output of the phase comparison means.
And the amount of phase shift between the two compared signals.
Phase difference signal by detecting the relative advance / delay of the phase of the two signals
A phase shift detecting means for generating a signal;
Generating the control voltage signal having a value for eliminating the phase shift amount.
Control voltage generating means, wherein the phase shift detecting means controls the output of the phase comparing means.
Serial / parallel conversion means for converting to a real bit string
And the logic of the input data signal
Bit string format that is fixed to a bit string that does not depend on the logical level
A type means, and the standardized bit string is an upper bit string and a lower bit string.
Parallel to convert to bit string and convert to serial bit
A phase synchronization circuit having a serial conversion circuit;