JP2971817B2 - OFDM diversity receiver signal combining method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver for receiving a transmission signal by an OFDM (Orthogonal Frequency Division Multiplexing) method, and more particularly to a demodulation after combining two reception signals by two reception antennas having different directivities. To a signal synthesis method.

[0002]

2. Description of the Related Art As conventional general diversity receivers, pp. 161 to 161 of "Basics of Mobile Communication" by the authors: Yoshihisa Okumura and Masaaki Shinji (published on October 1, 1986).
165 (especially pages 161 and 162) discloses its outline.

FIG. 6 shows an example of the configuration of a conventional general diversity receiver. 6, the main receiving antenna 1 and the sub receiving antenna 3 have different directivities. The signals received by these antennas 1 and 3 are selected by the first and second receiving high-frequency units 2 and 4 at the next stage, respectively. The signal is demodulated and output by the circuit 6.

[0004] Here, the received wave that has passed through the transmission path undergoes fading, and the received signal level fluctuates. Diversity reception uses two or more received waves as a technique for reducing the effect of the fading. .

[0005] Among the diversity receptions, the spatial diversity is a method of synthesizing reception signals from two or more spatially independent reception antennas having different directivities, has high practicality, and has been used more frequently than before.

[0006] This spatial diversity is achieved by performing the above-mentioned synthesis so that even if the level of the received signal from one main receiving antenna 1 drops, the received signal from the other sub-receiving antenna 3 having different directivity is received. The reception quality is configured to compensate for the drop in signal level.

However, the main receiving antenna 1 and the sub receiving antenna 3
Since the signals have different directivities, each received signal is a signal having a time difference with each other through different transmission paths (hereinafter, referred to as multipath or ghost). For this reason, especially in the reception of a digital modulation signal, if the signals are simply synthesized, the signal quality deteriorates rather than the interference between signals having a time difference.

In such a case, it is a general method to combine the reception signal level by the main reception antenna 1 and the reception signal level by the sub reception antenna 3 with a difference in level, without making them identical. Deterioration is inevitable.

On the other hand, OFD is a future digital broadcast transmission system relatively resistant to multipath and ghost interference.
The M method is considered promising. In this OFDM system, a number of orthogonal carriers are used, and transmission signal symbols are allocated to each carrier and multiplexed. At this time, a waveform of an effective symbol period called a guard interval is cyclically added to each symbol. In order to reduce the effects of multipath and ghost interference, a signal margin period is provided.

FIG. 7 shows a frame configuration of an OFDM signal. When viewed from the time axis, the OFDM signal starts with a specific synchronization symbol for frame synchronization on the receiving side, and has a period of one frame until the next synchronization symbol. At this time, as shown in FIG. 7, if the number of symbols from the synchronization symbol to immediately before the next synchronization symbol is m + 1, one frame includes m +
One symbol.

[0011] The synchronization symbol is also called a null symbol. This period is a period during which the receiver completely stops all the carrier waves in order to obtain frame synchronization for signal demodulation. O
The FDM signal constitutes one frame by collecting a number of code units called symbols, and each symbol has an effective symbol period Ts called a guard interval period as shown in the enlarged view of the symbol n in FIG. Is provided in a signal margin period Gn in which the waveform of (1) is cyclically added.

The effect of the guard interval when the reflected wave delay is within the guard interval will be described with reference to FIG. 8A shows a direct wave, FIG. 8B shows a reflected wave, and FIG. 8C shows a combined wave.

Now, when the time delay of the reflected wave with respect to the direct wave shown in FIG. 8A is within the guard interval time as shown in FIG. 8B, the synthesized wave is shown in FIG. As described above, symbol components different from Sn-1 and Gn are mixed in the hatched portion.

In the OFDM system, a received signal is subjected to a discrete Fourier transform (hereinafter, referred to as FFT) for demodulation processing. However, if the FFT is performed in the hatched portion, orthogonality is not maintained and intersymbol interference occurs. As a result, the signal quality is degraded, and specifically, the number of bit errors increases.

Therefore, in the OFDM system, the target time range of the FFT for demodulating the symbol is set to the range indicated by Ts excluding the guard interval period Gn in FIG. That is, since the range of Ts does not include the intersymbol interference portion of the hatched portion, demodulation can be performed without intersymbol interference by limiting to the range of Ts. Therefore, by adding the guard interval period, the effects of multipath and ghost interference can be reduced.

Next, a case where the reflected wave delay is equal to or longer than the guard interval time ta will be described with reference to FIG. 9A shows a direct wave, FIG. 9B shows a reflected wave, and FIG. 9C shows a combined wave.

In this case, as shown in FIG. 9C, a hatched portion causing intersymbol interference of the composite wave overlaps Ts for a time td, resulting in signal deterioration. To avoid signal quality degradation due to this effect, the guard interval period must be further extended.

However, the guard interval period is a signal margin period, does not directly contribute to signal demodulation, and the transmission efficiency decreases due to the addition of the guard interval. From this viewpoint, it is desirable that the guard interval period be as short as possible.

[0019]

As described above, in a conventional diversity receiver, signals received by receiving antennas having different directivities are combined with each other to reduce a drop in the received signal level due to one of the receiving antennas. The reception quality can be maintained in a form supplemented by the other signal. In particular, when the received signal is an OFDM signal, by adding a guard interval, it is possible to reduce signal degradation in the case of combining with a multipath or ghost having a time difference equal to or shorter than the guard interval period.

However, the conventional OFD as described above
The M diversity receiver has the following problems. First, as a first point, in combining signals received by receiving antennas having different directivities,
Since simple combining does not take into account the time difference between multipaths and ghosts, it is difficult to always avoid deterioration in reception quality.

Second, reception quality is deteriorated when combining with a multipath or ghost delayed beyond the guard interval period of the OFDM signal.
Third, in order to avoid the problem described in the preceding section, the guard interval period must be further lengthened, resulting in a problem that transmission efficiency is reduced.

The fourth point is that no consideration is given to a case generally called a pre-ghost, in which a signal received by a sub-antenna is more temporally advanced than a signal received by a main antenna. For this reason, even if a ghost occurs before this, deterioration of reception quality cannot be avoided.

The fifth point is that no consideration is given to the case where the time difference between the multipath and the ghost fluctuates with time as in the case of mobile reception, for example. Combining is not possible, and deterioration of reception quality cannot always be avoided.

The present invention solves the above-mentioned problems, and enables signal synthesis such as a signal delayed over a guard interval period or a previous ghost to be performed while always avoiding deterioration of reception quality, and adapting to reception conditions. OFD capable of adaptive signal synthesis
It is an object to provide an M diversity receiver.

In order to solve the above problems, an OFDM diversity receiver according to the present invention employs the following configuration. (1) Equipped with a main reception antenna and a sub reception antenna having two different directivities, and has a synchronization symbol period and a guard interval period by a diversity reception system that combines a main reception signal and a sub reception signal obtained in each antenna. And said
A null symbol that stops all carriers as a synchronization symbol
In an OFDM diversity receiver that receives an OFDM (Orthogonal Frequency Division Multiplexing) OFDM signal,
The main reception signal includes at least the guard interval period.
A fixed delay circuit that performs a fixed delay time processing longer than
Variable delay circuit that performs variable delay time processing on the sub-received signal
A delay processing unit and a reception time difference detecting means for detecting a reception time difference between the main receive signal and the sub reception signals respectively delayed by this means, as reception time difference obtained by this means enters at least the guard interval period A delay time control means for controlling a delay time of the delay processing means; a synthesizing means for synthesizing and outputting a main reception signal and a sub reception signal respectively delayed by the delay processing means; A frame synchronization signal and a clock signal are reproduced from the synchronization symbol period of the main reception signal or the composite reception signal, and an OFDM signal is reproduced based on the frame synchronization signal.
Comprising a demodulating means for demodulating said reception time difference detection hand
The stage starts from the start of the null symbol period of the main reception signal.
From the point in time before the guard interval
Twice the guard interval from the start of the null symbol period of the signal
3 times the guard interval until after the interval period
Level of the main reception signal and the sub reception signal over the
By performing correlation detection on the difference, the main received signal and
The reception time difference between the reception signals is detected .

[0026]

[0027]

[0028]

( 2 ) In the configuration of ( 1 ), the reception time difference detection means causes the synthesis means to output only the main reception signal delayed by the fixed delay circuit of the delay processing means, and is obtained by the demodulation means. the frame synchronization signal and a clock signal, synchronized to the frame sync signal, before ghost
A first latch pulse for detecting the
A second method for detecting a ghost after the
Latch pulse and ghost after guard interval
Latches of the third latch pulse for detecting the latch
A timing generation circuit that generates a pulse and generates a determination timing signal after the generation of these latch pulses; and a latch circuit that latches a detection result of the correlation detection circuit at each timing of the latch pulse. The control means, upon input of the determination timing signal generated by the timing generation circuit, calculates a frame head of the sub-reception signal after the delay processing with respect to a frame head of the main reception signal after the delay processing from the pattern of the latch result of the latch circuit. It is determined whether or not the position is within the control range, and the control processing content of the delay time is selectively switched based on the determination result.

( 3 ) In the configuration of ( 2 ), the fixed delay circuit has a fixed delay time set to a time corresponding to the guard interval, and the timing generation circuit has at least a signal immediately before the frame synchronization signal, Immediately after the start of the frame synchronization signal, after the fixed delay time has elapsed from the start of the frame synchronization signal, first, second, and third latch pulses are generated, and after the third latch pulse is generated, the determination timing signal is output. Generated, the latch circuit latches the detection result of the correlation detection circuit at the timing of the first to third latch pulses, and the delay time control means controls the latch circuit at the generation timing of the determination timing signal. The time relationship between the main reception signal and the sub reception signal after the delay processing is determined from the latch result pattern of , The delay time for the variable delay circuit is controlled.

( 4 ) In the configuration of ( 3 ), the timing generation circuit generates the determination timing signal after a lapse of twice the fixed delay time after the start of the frame synchronization signal.

( 5 ) In the configuration of ( 3 ), the delay time control means may determine, based on a pattern of a latch result of the latch circuit, a delay of the main reception signal after the delay processing at the generation timing of the determination timing signal. It is determined whether or not the frame start position of the sub-reception signal after the delay processing is within the control range of the guard interval. If the frame start position is within the control range of the guard interval, control of the variable delay circuit is stopped, and control of the guard interval is performed. When not within the range, the delay time corresponding to the time difference between the two received signals obtained from the correlation detection result with respect to the variable delay circuit is determined immediately after the determination of the latch and time relationship by the third latch pulse, that is, the time following the synchronization symbol. The configuration is set before a symbol is started.

( 6 ) In the configuration of ( 3 ), the reception time difference detection means further detects the correlation detection period obtained by the correlation detection circuit by a clock signal counting process, so that the main reception signal and the sub reception signal are detected. A count processing circuit for judging a reception time difference from a signal, wherein the delay time control means is obtained by the counter processing circuit when it is judged in the judgment at the time of inputting the judgment timing signal that it is not within the control range of the guard interval. The delay time corresponding to the reception time difference is set immediately after the determination of the latch and the time relationship by the third latch pulse, that is, before the next symbol of the synchronization symbol is started.

[0034]

[0035]

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a block circuit diagram showing a configuration of an OFDM diversity receiver according to an embodiment of the present invention, FIG. 2 is a signal timing diagram showing operation timing of the embodiment, and FIGS. FIG. 4 is a signal timing chart for explaining operations of first, second, and third specific examples of the embodiment.

In FIG. 1, a main reception signal from a main reception antenna 1 is converted to an intermediate frequency signal by a first reception high frequency section 2, and a fixed delay circuit 7 performs a fixed time delay process of the same length as the guard interval period. After that, the signal is supplied to the demodulation circuit 6 via the synthesis circuit 5 in the next stage.

On the other hand, the sub reception signal from the sub reception antenna 3 having a different directivity from the main reception antenna 1 is converted into an intermediate frequency signal by the second reception high frequency unit 4 and delayed by the variable delay circuit 8. The delayed sub-received signal 15 is supplied to the synthesizing circuit 5 after passing through the next-stage switch (SW) circuit 9, and is synthesized with the delayed main received signal 14.

However, the switch circuit 9 is off in the transient state immediately after the power is turned on or immediately after the channel is switched, so that the signal synthesis is not performed. The switch is turned on by a switch control signal 25 given after the reception synchronization is sufficiently established, and a signal combining operation is performed.

Also, in the variable delay circuit 8, in a transient state immediately after power-on or immediately after channel switching, the delay time value is set to the same value as the delay time of the fixed delay circuit 7, in other words, the same time value as the guard interval period. It is supposed to be.

Accordingly, in the transient state, the reception synchronization is achieved only by the main reception signal from the main reception antenna 1, and after the synchronization is established, the demodulation circuit 6 obtains the frame synchronization signal 16 that matches the synchronization symbol period.

The demodulating circuit 6 demodulates the received signal synthesized by the synthesizing circuit 5 to generate a synchronizing monitor signal 17 and a clock signal 18 together with the frame synchronizing signal 16 and output them to the timing generating circuit 11.

Here, the synchronization monitor signal 17 is a monitoring signal as to whether or not the reception synchronization in the demodulation circuit 6 has been established. The timing generation circuit 11 performs, as a first operation,
After it is determined from the synchronization monitor signal 17 that synchronization has been sufficiently established over several frames, the switch control signal 25 is output to turn off the switch circuit 9 and sufficient reception synchronization is established. After that, control is performed so that the signal combining operation is performed.

The clock signal 18 is a signal serving as a reference of the demodulation circuit 6 including the synchronization processing operation, and is a pulse signal having a high frequency of several thousand to several tens of thousands times the symbol frequency. This clock signal 18 is applied to the count / latch circuit 12
Is also supplied.

As a second operation, the timing generation circuit 11 uses the frame synchronization signal 16 and the clock signal 18 from the demodulation circuit 6 to generate the first latch pulse 19, the second latch pulse 20, the third latch pulse 21, the determination timing signal 28, a delay count timing signal 29 is generated.

Here, the guard interval period, one frame period, symbol period and the like are values known to the receiver side as a transmission standard. Therefore, the timing generation circuit 11
If the reception synchronization is established and the frame synchronization signal 16 is obtained, the signal 1 can be obtained by a simple combination of logic circuits.
9 to 21, 28, and 29 can be easily generated.

On the other hand, the fixed delay circuit 7 and the variable delay circuit 8
Are supplied to the correlation detection circuit 10. This correlation detection circuit 10 performs level correlation detection of both inputs. The correlation detection result 26 is the count / latch circuit 1
2 is supplied.

The count / latch circuit 12 monitors the correlation detection result during the input period of the delay count timing signal 29 and counts the clock signal 18 during the period during which the correlation is detected, so that the variable delay circuit 8 Find the delay time set in. Further, at the falling point of the delay count timing signal 29, the levels of the first latch pulse 19, the second latch pulse 20, and the third latch pulse 21 are latched. The delay time information 30 and the latch signals 22, 23, 24 obtained in this way are supplied to the comparison and judgment circuit 13.

The comparison / determination circuit 13 receives the above-mentioned latch signals 22, 23, 24
By comparing the levels of the delay main reception signal 14 and the delay sub reception signal B15, it is determined whether or not the delay time is equal to or longer than the guard interval period. Then, the delay amount setting signal 27 is sent to the variable delay circuit 8 according to the determination result, and the delay time of the variable delay circuit 8 is reset based on the delay time information 30 obtained by the count / latch circuit 12.

The operation of the features of the present invention in the above configuration will be described below with reference to FIGS. First,
Signals 19 to 2 generated by the timing generation circuit 11
The timing relationship between 1, 28 and 29 is as shown in FIG. 2, (a) shows the demodulated output of the demodulation circuit 6,
(B) is the frame synchronization signal 16 synchronized with the synchronization symbol of the demodulation output. The first latch pulse 19 is shown in FIG.
As shown in (c), the pulse signal rises immediately before the start of the frame synchronization signal and has a high level period equal to the guard interval period. The second latch pulse 20 is shown in FIG.
As shown in (d), the pulse signal rises immediately after the start of the frame synchronization signal and has a high level period equal to the card interval period. The third latch pulse 21 is shown in FIG.
As shown in (e), the pulse signal rises immediately after the period corresponding to the guard interval period from the start of the frame synchronization signal, and has a high level period equal to the guard interval period.

As shown in FIG. 2 (f), the determination timing signal 28 rises immediately after the period corresponding to twice the guard interval period from the start of the frame synchronization signal,
The high level period is a pulse signal equal to the guard interval period, and is supplied to the comparison determination circuit 23.

The delay count timing signal 29 is shown in FIG.
As shown in (g), at a point in time earlier than the start of the frame synchronization signal by a guard interval equivalent period Tg, that is, at the time tb in the figure, and immediately after a period corresponding to twice the guard interval period after the start of the frame synchronization signal, In the figure, a high-level period falling at tc is a pulse signal equal to three times the guard interval period, and is supplied to the count and latch circuit 12.

Meanwhile, the correlation detection circuit 10, the slow fixed
The main reception signal 14 from the extension circuit 7 and the variable delay circuit 15
The level correlation detection with the sub-received signal 15 is performed, which is possible because the period of the synchronization symbol completely stops all carriers on the transmitting side. Row in correlation detection circuit 10
Level correlation detection means, for example,
From the level change of each signal,
Finds the start of a null symbol where the carrier is completely stopped
Time difference between the null symbol start points of both signals.
And

FIG. 3 shows that the delay time of the sub-reception signal 15 with respect to the main reception signal 14 is within the guard interval period td.
1 is shown. In FIG. 3, (a) shows the main reception signal 14 with a fixed delay, and (b) shows the sub-reception signal 15 with a variable delay. In the figure, Tg is the guard interface.
The bar equivalent period is shown.

Here, the correlation detecting circuit 10 is shown in FIG.
As shown, the correlation level difference between the main reception signal 14 and the sub reception signal 15
Is detected during the period from tb to tc in FIG.
The large part, that is, the hatched part in FIG.
The part without hatching overlaps from tb to tc in the period.
The high level correlation detection output 26 is obtained only during the
It is configured as follows.

When the correlation detection output 26 is latched by the count / latch circuit 12 using the first latch pulse 19, the second latch pulse 20, and the third latch pulse 21, the first latch signal 22, which is the latch output, is output. The second latch signal 23 and the third latch signal 24 are respectively shown in FIG.
(E) and (f) are obtained.

Thereafter, the comparison / judgment circuit 13 sends out the delay amount setting signal 27 simultaneously with the determination of the comparison / judgment result by the judgment timing signal 28 to reset the delay time of the variable delay circuit 8 according to the comparison / judgment result. .

However, in the case of FIG. 3, the first latch signal 22
Is low level, the second latch signal 23 is high level,
The latch signal 24 is at a low level. This indicates that the delay time of the sub reception signal 15 with respect to the main reception signal 14 is within the guard interval period. Therefore, in this case, the comparison determination circuit 13 operates so as not to reset the delay time.

As is apparent from FIG. 3 , when there is no time difference between the main received signal 14 and the delayed received signal 15 and they completely match, the first latch signal 22 is at the low level and the second latch signal 23 is at the low level. Becomes low level and the third latch signal 24 becomes low level, but also in this case, the comparison and determination circuit 13 operates so as not to reset the delay time.

FIG. 4 shows that the delay time of the sub time signal 15 with respect to the main reception signal 14 is equal to or longer than the guard interval period.
2 is shown. In FIG. 4, (a) shows the main reception signal 14 and (b) shows the sub reception signal 15, and each hatched portion indicates the head of the frame. Also,
In the figure, Tg indicates a period corresponding to a guard interval of the OFDM signal.

In this case, since the correlation detection output of the correlation detection circuit 10 is as shown in FIG. 4C, the correlation detection output 26 is divided into the first latch pulse 19, the second latch pulse 20, and the third latch pulse. When the count / latch circuit 12 latches the signal by the pulse 21, the first latched output
The latch signal 22, the second latch signal 23, and the third latch signal 24 are at a low level, a high level, and a high level, respectively, as shown in FIGS. 4D, 4E, and 4F. This indicates that the delay time of the sub reception signal 15 with respect to the main reception signal 14 is longer than the guard interval period.

In this case, the comparison and judgment circuit 13 determines the comparison and judgment result by the judgment timing signal 28 and, at the same time, sends out the delay amount setting signal 27 and
Is reset according to the result of the comparison.

In the count / latch circuit 12, the delay time td2 shown in FIG. 4C is counted by the clock signal 18 while the delay count timing signal 29 is at the high level. Is the sub-received signal 1 when the delay time of the variable delay circuit 8 is reset.
5 to reduce the delay time by td2. As a result, the main reception signal 14 and the sub reception signal 15 are synthesized by the synthesizing circuit 5 in a completely matched state without a time difference.

FIG. 5 shows a case where the sub-reception signal 15 is temporally ahead of the main reception signal 14 by td3. 5A also shows the main reception signal 14, FIG.
(B) is the sub-received signal 15, and each shaded portion indicates the head of the frame. Tg in the figure is OFD
The period corresponding to the guard interval of the M signal is shown.

In this case, since the correlation detection output of the correlation detection circuit 10 is as shown in FIG. 5C, the correlation detection output 26 is converted to the first latch pulse 19, the second latch pulse 20, and the third latch pulse. When the count / latch circuit 12 latches the signal by the pulse 21, the first latched output
The latch signal 22, the second latch signal 23, and the third latch signal 24 are at a high level, a low level, and a low level, respectively, as shown in FIGS. 5D, 5E, and 5F. This indicates that the sub reception signal 15 is temporally advanced with respect to the main reception signal 14.

At this time, as in the case of FIG. 4, the comparison / determination circuit 13 determines the comparison / determination result based on the determination timing signal 28 and, at the same time, sends out the delay amount setting signal 27 and outputs the delay time of the variable delay circuit 8. Is reset according to the comparison determination result.

[0067] Here, in the count latch circuit 12, similarly to the case of FIG. 4, the delay time td 3 the delay count timing signal 29 by the clock signal 18 shown in FIG. 5 (c) during the high-level The comparison and determination circuit 13 operates so as to increase the delay time of the sub reception signal 15 by td3 when the delay time of the variable delay circuit 8 is reset. As a result, the main received signal 14 and the sub-received signal B15 are synthesized by the synthesizing circuit 5 in a completely matched state with no time difference.

As described above, in the case of the present embodiment, it is possible to combine a time advance within the guard interval time and a time delay up to twice the guard interval time while avoiding intersymbol interference.

As described above, in this embodiment, the main reception signal from the main reception antenna 1 is subjected to the fixed delay time processing in advance, the timing signal is generated after the frame synchronization is established, and the variable delay time processing is performed. The delay or advance time of the main reception signal with respect to the sub reception signal by the sub reception antenna 2 is detected, the variable delay time is corrected, and then synthesized, and the synthesized signal is demodulated.

Therefore, even when the sub-reception signal from the sub-reception antenna 2 is delayed from the main reception signal by more than the guard interval time or when the time is advanced, there is no time difference. In this state, it can be synthesized by the synthesis circuit 5.

Therefore, even if the guard interval period is not lengthened, it is substantially equivalent to a longer guard interval period, and signal quality deterioration can be avoided without lowering the transmission efficiency.

In the above embodiment, for the sake of simplicity, the fixed delay time of the signal received by the main receiving antenna 1 is assumed to be the same as the guard interval period. Obviously, it is possible to cope with a longer time delay or advance with a longer time.

[0073]

As described above, according to the present invention, as a first point, in combining signals received by receiving antennas having different directivities, a sub receiving signal by a sub receiving antenna with respect to a main receiving signal by a main receiving antenna. Since the delay time is detected and the variable delay time is corrected and then synthesized, compared to the simple synthesis that does not consider the time difference,
Deterioration of reception quality can always be avoided.

The second point is that the main reception signal from the main reception antenna is subjected to fixed delay time processing in advance, a timing signal is generated after the frame synchronization is established, and the sub reception is performed by the sub reception antenna that has been subjected to variable delay time processing. Since the delay or advance time is detected from the signal, the OFDM
Even in the case of combining with a multipath or a ghost delayed beyond the guard interval period of the signal, the signal can be combined so as not to deteriorate the reception quality.

Third, even if the guard interval period is not lengthened, it is substantially equivalent to a longer guard interval period, and the effect of avoiding signal quality deterioration without lowering transmission efficiency can be obtained. Can be.

The fourth point is that the reception quality is deteriorated even in a case where the sub reception signal by the sub reception antenna is temporally advanced compared to the main reception signal by the main reception antenna. Can be avoided.

Fifth, since the operation of the present invention is performed for each synchronization symbol period, that is, for each frame start time,
For example, even when the time difference between the multipath and the ghost fluctuates over time, such as in the case of mobile reception,
Adaptive signal combining according to the reception state for each frame is possible, and an effect of always avoiding deterioration of reception quality can be obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing one embodiment of an OFDM diversity receiver according to the present invention.

FIG. 2 is a signal timing chart showing operation timing of the embodiment.

FIG. 3 is a signal timing chart for explaining the operation of the first specific example of the embodiment.

FIG. 4 is a signal timing chart for explaining the operation of the second specific example of the embodiment.

FIG. 5 is a signal timing chart for explaining the operation of the third specific example of the embodiment.

FIG. 6 is a block circuit diagram showing a configuration of a conventional diversity receiver.

FIG. 7 is a diagram illustrating a frame configuration of an OFDM signal.

FIG. 8 is a timing chart showing a state of combining when a reflected wave delay is within a guard interval time when an OFDM signal is received by diversity reception.

FIG. 9 is a timing chart showing a state of synthesis when a reflected wave delay is equal to or longer than a guard interval time when an OFDM signal is received by diversity reception.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Main receiving antenna 2 ... High frequency receiving part 3 ... Secondary receiving antenna 4 ... High frequency receiving part B 5 ... Synthesis circuit 6 ... Demodulation circuit 7 ... Fixed delay circuit 8 ... Variable delay circuit 9 ... Switch (SW) circuit 10 ... Correlation detection Circuit 11 ... Timing generation circuit 12 ... Count latch circuit 13 ... Comparison circuit 14 ... Main reception signal 15 ... Sub reception signal 16 ... Frame synchronization signal 17 ... Synchronization monitor signal 18 ... Clock signal 19 ... First latch pulse 20 ... First 2 latch pulse 21 third latch pulse 22 first latch signal 23 second latch signal 24 first latch signal 25 switch control signal 26 correlation detection output 27 delay setting signal 28 determination timing signal 29 Delay count timing signal 30 ... Delay time information Tg ... Guard interval equivalent period td1, td2, td3 ... Delay time

Claims (6)

(57) [Claims] 1. A synchronization symbol period and a guard interval period provided by a diversity reception system which comprises a main reception antenna and a sub reception antenna having two different directivities and combines a main reception signal and a sub reception signal obtained in each antenna. With
And a null symbol for stopping all carriers as the synchronization symbol.
OFDM (Orthogonal Frequency Division Multiplexing) system with symbols
An OFDM diversity receiver for receiving an FDM signal, wherein the main reception signal includes at least the guard interval period.
A fixed delay circuit that performs a fixed delay time processing longer than
Variable delay circuit that performs variable delay time processing on the sub-received signal
A delay processing unit and a reception time difference detecting means for detecting a reception time difference between the main receive signal and the sub reception signals respectively delayed by this means, as reception time difference obtained by this means enters at least the guard interval period Delay time control means for controlling a delay time of the delay processing means; synthesizing means for synthesizing and outputting a main reception signal and a sub reception signal respectively delayed by the delay processing means; The frame synchronization signal and the clock signal are reproduced from the synchronization symbol period of the main reception signal or the composite reception signal.
Demodulation means for performing FDM demodulation , wherein the reception time difference detection means comprises a null signal of the main reception signal.
Guard interval period equivalent time from the start of the vol period
At the start of the null symbol period of the main reception signal from the previous time
Up to twice the guard interval period
Over three times the guard interval, the main received signal
To perform correlation detection on the level difference between the
An OFDM diversity receiver for detecting a reception time difference between a main reception signal and a sub reception signal . 2. The receiving means according to claim 1, wherein said receiving time difference detecting means comprises:
Main reception delayed by the fixed delay circuit of the delay processing means.
A frame obtained by outputting only a signal and obtained by the demodulation means.
The frame synchronization is performed by a synchronization signal and a clock signal.
A first latch for detecting a pre-ghost synchronized with the signal.
Postpulse and ghost after guard interval time
A second latch pulse for detecting the
Latch to detect ghost after global
And generating three types of latch pulses.
After the generation of the third latch pulse, the judgment timing signal is generated.
Timing generation circuit and three types of latch pallets
The detection result of the correlation detection circuit at each
And a delay circuit for controlling the delay time.
When the generated judgment timing signal is input, the latch circuit
Main reception after the delay processing from the pattern of the path latch result
Of the sub-received signal after delay processing
Determine whether the frame start position is within the control range,
Based on the result of the determination, the control processing content of the delay time is
The OFDM diversity receiver according to claim 1, wherein the switching is selectively performed . 3. The fixed delay circuit according to claim 1, wherein the fixed delay time is
The timing generation circuit is set to a time corresponding to the guard interval ,
Immediately before the synchronization signal, immediately after the start of the frame synchronization signal,
After the fixed delay time has elapsed since the start of the frame synchronization signal
Respectively generate first, second, and third latch pulses.
And a determination time after the third latch pulse is generated.
A latch signal is generated, and the latch circuit outputs the first to third latch pulses.
The detection result of the correlation detection circuit is latched at a timing, and the delay time control means generates the determination timing signal.
At the raw timing, the pattern of the latch result of the latch circuit is
From the main reception signal and the sub reception signal after the delay processing
The variable delay circuit based on the determination result.
Controlling a delay time for the road.
3. The OFDM diversity receiver according to 2 . 4. The timing generation circuit according to claim 1 , wherein
Elapsed time twice as long as the fixed delay time after the start of the synchronization signal
Generating a decision timing signal later.
OFDM diversity receiver according to Motomeko 3. 5. The delay time control means according to claim 1 , wherein
Latch signal of the latch circuit
From the resulting pattern, the frame of the main received signal after the delay processing
Frame destination of sub-received signal after delay processing
Whether the head position is within the control range of the guard interval
Is determined, and when it is within the control range of the guard interval,
Stop the control of the variable delay circuit, and
When it is not within the control range of the tarball, the variable delay circuit
On the other hand, the time difference between the two received signals obtained from the correlation detection result
Latch a considerable delay time by the third latch pulse
Immediately after the determination of the time relationship, that is,
Claim set before the start of the bol
Item 4. The OFDM diversity receiver according to item 3 . 6. The receiving time difference detecting means, further comprising:
The correlation detection period obtained by the correlation detection circuit is
The main reception signal and the sub reception signal are detected by the count processing.
A count processing circuit that determines the reception time difference from the received signal
Wherein the delay time control unit, the determination timing signal input
Time is out of the control range of the guard interval.
When it is determined that the
The delay time corresponding to the transmission time difference is determined by the third latch pulse.
Immediately after determining the latch and time relationship,
It is set before the next symbol starts.
The OFDM diversity receiver according to claim 3 .