JP2971267B2 - Personal computer using flash memory as BIOS-ROM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a personal computer used as an IOS-ROM.

[0002]

2. Description of the Related Art Generally, a computer system such as a personal computer has a ROM (Read Only Memory) for storing a BIOS (Basic Input / Output Program). Conventionally, when the content of the BIOS-ROM has been destroyed or when the content of the BIOS has been upgraded, it has been necessary to replace the BIOS-ROM with a new chip.

Recently, flash memories have been commercially available as rewritable ROMs. The flash memory has various features such as erasing stored data in block units. Therefore, the flash memory is stored in B
It is convenient if it can be used as an IOS-ROM.

[0004]

As described above, as described above,
When the contents of the BIOS-ROM are destroyed or when the contents of the BIOS are upgraded, the BIOS-RO
M had to be replaced with a new chip. But,
Replacing the chip was very cumbersome because the computer housing had to be opened.

On the other hand, a flash memory generally has a control read-only area called a boot block at the end of a storage area. Therefore, when this type of flash memory is used as a BIOS-ROM, it is necessary to access this boot block immediately after the CPU is reset to execute a far jump instruction. In the normal state, it is necessary to access another area storing the BIOS. This BI
The OS preferably has compatibility with existing personal computers.

[0006] However, the boot block in which the far jump instruction is placed overlaps with an area in which a BIOS compatible with an existing personal computer is stored in a memory space (address space) visible from the CPU. Therefore, in order to access the boot block to execute the far jump instruction immediately after the power reset (power-on reset) and to access the BIOS storage area in the normal state, it is necessary to devise control of the address data. .

Further, a memory space allocated to an area of the BIOS-ROM area that is not accessed in a normal state, that is, an area other than an area storing the BIOS such as a boot block, can be released for access other than access to the BIOS-ROM. It is necessary to devise something.

The present invention has been made in view of the above circumstances. When a BIOS-ROM is constituted by a flash memory, a boot block is accessed immediately after a power reset to execute a far jump instruction, and a normal state is accessed. An object of the present invention is to provide a personal computer capable of accessing a storage area of a BIOS.

Another object of the present invention is to store a memory space allocated to an area of the BIOS-ROM that is not accessed in a normal state, that is, an area other than the area storing the BIOS such as a boot block, by accessing the BIOS-ROM. Another object of the present invention is to provide a personal computer that can be opened to other users.

[0010]

[0011]

Means for Solving the Problems] To achieve the above object, path over coarsely braided computer of the present invention, the second to the first storage area and a BIOS boot area is secured (basic input output program) is stored a BIOS-ROM and a flash memory having a storage area of, after power reset straight accesses a boot area and outputs a predetermined address data specifying the boot area on the BIOS-ROM, system start-up Then, the data processing means for performing an operation in accordance with the BIOS stored in the BIOS-ROM, and accessing the first storage area among the addresses output from the data processing means after system startup.
To the second storage area
In order to access the BIOS stored in the
Address conversion means an address specifying the storage area you translate the address designating the second storage area of,
Access to the boot area by the data processing means
Accordingly, whether the data stored in the BIOS-ROM is normal or not
Determining means for determining the BIO
If the storage data of the S-ROM is determined to be normal
Means for setting the address conversion means to a valid state;
It is characterized by having.

[0012]

[0013]

According to path over coarsely braided computers the present invention, electrostatic
Immediately after a power source reset, the flash memory
When the secured boot area is accessed, for example, boot
Execution of the far jump instruction stored at a predetermined position in the area
As a result, a BIOS composed of the flash memory
-Check the contents of the ROM and the contents of the BIOS-ROM.
If there is no problem, the flash that configures the BIOS-ROM
First memory (with a secured boot area) in flash memory
Area and the second storage area (where the BIOS is stored)
Address translation means for translating the attached address
By setting to the valid state, in the normal state after the system is started, the data is output to access the first storage area.
The second storage area based on the address conversion
Execution of access to the stored BIOS becomes possible, use flash memory having a boot area as a computer BIOS memory (BIOS-ROM).

[0014]

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) First, a system configuration of a personal computer according to a first embodiment of the present invention will be described with reference to FIG.

This personal computer is a portable computer and has a CP for controlling the entire system.
U11 is provided. The CPU 11 has, for example, the ability to process 16-bit data and 24-bit addresses. As the CPU 11, for example, Intel (USA)
The one having the same configuration and function as the 386SL can be used.

The system memory 13 is connected to a local bus of the CPU 11. This system memory 13
It is used as a main memory of the present system (personal computer system). The system memory 13 stores programs and data to be processed. In this embodiment, the system memory 13
Has a standard 2 MB storage capacity. The system memory 13 can be expanded to a maximum of 18 Mbytes by installing an expansion memory in the expansion slot 14. CP
U11 is connected to the system bus 15. The system bus 15 is used for transferring address data, data, and control data.

The system bus 15 has a BIOS (Basic
BIOS- in which Input / Output System) is stored
The ROM 17 is connected. This BIOS-ROM1
7 is composed of a flash memory. BIOS
-Details of the ROM 17 will be described later with reference to FIGS.

A super integration IC (SI) 19 is also connected to the system bus 15. The IC 19 includes two DMA controllers for direct memory access control, two programmable interrupt controllers (PIC), two programmable interrupt timers (PIT), two serial input / output interfaces (SIO), and a real-time Clock (RTC)
Is built in. As this IC 19, for example, 82360SL of Intel Corporation can be used. The system bus 15 also includes a hard disk drive (HD)
D) 21 and Super Integration IC (SI)
23 are connected.

Hard disk drive (HDD) 21
Has an IDE (Integrated Drive Electronics) interface, and its access is directly controlled by the CPU 11. This hard disk drive (HDD) 21
Has a storage capacity of 2.5 inches and 120 M / 200 Mbytes.

Super Integration IC (SI) 2
Reference numeral 3 contains a floppy disk controller (FDC) for controlling a floppy disk drive and a variable frequency oscillator (VFO) for generating a clock for FDC. As this IC 23, for example, T
9920 is available.

The IC 23 has a floppy disk drive (internal FDD) 25 built in the device as a standard.
Is connected. The IC 23 has an external floppy disk drive or a printer (PRT) as necessary.
/ FDD) 27 is connected. Further, a power controller 39 for controlling a power supply 41 of the system is connected to the IC 23. The power controller 39 outputs a power-on reset signal when power is turned on.

A display controller (DISP-CONT) 29 is also connected to the system bus 15. The display controller 29 controls display of a display panel 31 such as an LCD.

A keyboard controller (KBC) 33 is also connected to the system bus 15. This keyboard controller 33 controls a keyboard (KB) 35 connected to the controller 33. That is, the keyboard controller 33 scans the key matrix of the keyboard 35, receives a signal corresponding to a pressed key, and converts it into a predetermined key code. This key code is transmitted to the CPU 11 via the system bus 15 by handshake serial communication.

An extension connector 37 is further connected to the system bus 15. An expansion unit (expansion board) for expanding functions can be attached to the expansion connector 37.

Next, the configuration of the BIOS-ROM 17 and a memory space (address space) allocated to the BIOS-ROM 17 will be described with reference to FIGS.

First, the BIOS-ROM 17 stores 8 bits ×
The flash memory has a storage capacity of 128K, that is, a storage capacity of 128K bytes. As shown in FIG. 2, the area of the BIOS-ROM 17 from 0 to 120 Kbytes, that is, the physical address is 000000H-1DFF
The FH area is a main block 171 from which data can be read / written / erased. In addition, "H" at the end
Indicates a hexadecimal representation. However, "H" will be omitted in the following expressions for addresses. Also BIOS
The area from 120 Kbytes to 128 Kbytes of the ROM 17, that is, the area where the physical address is 1E000-1FFFF is a read-only boot block 172.
As the BIOS-ROM 17, for example, i28F001BX-T manufactured by Intel Corporation can be used.

A boot block 172 on the BIOS-ROM 17 is an area in which a program for executing a minimum function for controlling the system is stored. The boot block 172 includes a far jump instruction 173 and a BI
CR for checking the storage contents of the OS-ROM 17
A C (Cyclic Redundancy Check) routine 174 and a routine (address conversion and address mask routine) 175 for converting and masking addresses in the BIOS-ROM 17 are stored. The boot block 172 also includes an initialization routine 176 for minimum initialization processing, and a transfer routine 177 for transferring a rewrite routine used for rewriting the BIOS-ROM 17 from the floppy disk drive (FDD) 25 to the system memory 13. Is stored. The far jump instruction 173 is stored in an area of the BIOS-ROM 17 starting from address 1FFFO.

On the other hand, an area (low memory area) from 0 to 64 kbytes of the main block 171 on the BIOS-ROM 17 includes a BIOS including an IRT (initialization routine) and the like.
An OS, for example, a BIOS compatible with a conventional personal computer is stored. A system management routine is stored in the remaining area of 56 Kbytes (high memory area) from 64 Kbytes to 120 Kbytes of the main block 171. This system management routine is a program for setup, power save, suspend, resume, and the like.

As shown in FIG. 3, the 128-Kbyte area of the BIOS-ROM 17
In the memory space of the byte, it seems to exist in the last (High side) 128 Kbyte area of the area from 15 Mbytes to 16 Mbytes, that is, the area of addresses FE0000-FFFFFF. Also, BI
The 128K byte area of the OS-ROM 17 is
From 1 to 0 to 1M on 16M bytes of memory space
It looks like it exists in the last (High side) 128 Kbyte area of the area up to the byte, that is, the area of addresses 0E0000-0FFFFF.

When viewed from the CPU 11, the BIOS-RO
Immediately after power-on, as shown in FIG. 4A, the address of M17 has a low-side (first half) 64-Kbyte area (0-64 Kbytes) of E000 (segment address): 0000 (segment). Address) -E00
0: A 64 KB area (64 KB-128 KB) on the High side (the latter half) is F0000: 0 in FFFF.
00-F000: respectively assigned to FFFF. On the other hand, in the normal state, as shown in FIG. 4B, the 64 Kbyte area on the low side of the BIOS-ROM 17 is set to F000: 0000-F000: FFFF and Hi-level.
The 64 KB area on the gh side is E000: 0000-E00
0: Allocated to FFFF. That is, CP
The addresses of the low-side 64 Kbyte area and the high-side 64 Kbyte area of the BIOS-ROM 17 as viewed from U11 are as shown in FIG. 4A and FIG. Immediately after and the normal state is replaced. The details of such address conversion will be described later with reference to FIG. The address PQRS: TUVW is PQRS
The address can be converted to an address output from the CPU 11 by the addition operation of 0 + TUVW.

Next, a basic configuration centering on an address circuit for addressing the BIOS-ROM 17 will be described with reference to FIG. First, the BIOS-ROM 17 contains 12
A 17-bit address A 0-16 corresponding to a storage capacity of 8 Kbytes, a chip select signal ROMCS # (# indicates low active), a memory write signal MEMWT #, a memory read signal MEMRD #, and a write signal PR
OG is supplied.

The address bits 0-15 of the 24-bit address A 0-23 output from the CPU 11 are B
It is supplied to the IOS-ROM 17. Also, address bits
An EXOR (exclusive or) gate 47 performs an exclusive OR operation with the control signal INV to perform address conversion as shown in FIGS. 4 (a) and 4 (b).
The OR is taken and supplied to the BIOS-ROM 17.

The write signal PROG becomes a high voltage +12 V at the time of data writing, and becomes a ground voltage in other states.
The change of the voltage level of the write signal PROG is performed by the switching operation of the switch 45 according to the control signal ROMPRG. Note that a switch element such as a relay or an FET can be used instead of the switch 45.

The chip select signal ROMCS # is CP
The upper 8 bits A16-A23 of the 24-bit address A0-A23 output by U11 and the control signal DISE
It is generated by a mask circuit 49 having # as an input. The mask circuit 49 will be described with reference to FIG.

First, the mask circuit 49 includes the AND gate 5
1, 57, a NOR gate 53, OR gates 55 and 59, and a NAND gate 61. Of the 24-bit address A0-A23 output by the CPU 11, the upper 4 bits A20-A23 are supplied to the AND gate 51, and the A4
It is detected whether A23 is all "1" (F in hexadecimal notation). These four bits A20-A23 are NOR gate 53
And it is detected whether A20-A23 is all "0" (0 in hexadecimal notation). Both outputs of the AND gate 51 and the NOR gate 53 are supplied to an OR gate 55.

Output of OR gate 55 and address bit A
17-19 are supplied to an AND gate 57 to detect whether or not the address bits A20-A23 are all "1" or "0" and whether the address bits A17-19 are all "1". That is, address A0-23 is FF × XXX ×, F
It is detected whether it is any of Exxx, 0Fxxx, and 0Exxx (xxx is any value in the range of 0000-FFFF). The address bit A16 and the control signal DISE # are supplied to the OR gate 59.

Both outputs of the AND gate 57 and the OR gate 59 are supplied to a NAND gate 61. NAND gate 61
Outputs an active low-level chip select signal ROMCS # when both outputs of the AND gate 57 and the OR gate 59 are at a high level. On the other hand, when at least one of the outputs of the AND gate 57 and the OR gate 59 is at the low level, the inactive high level chip select signal ROMCS #
Is output.

With the configuration of the mask circuit 49 described above, in the state shown in FIG. 4 (b), the CPU 11 sends the BIOS-ROM 17 from 64K bytes to 128K bytes.
When an address designating the area up to the byte is output, A16 is "0" (low level), so that the signal DI
If SE # is at a low level, the chip select signal ROMCS # goes to a high level and the BIOS-RO
M17 enters a chip disable state. This allows
Access to the BIOS-ROM 17 is prohibited. In other words, addresses in the range of E000: 0000-E000: FFFF are masked. Details of the operation of the mask circuit 49 will be described later.

Next, the control signal INV (FIG. 5), the control signal DISE # (FIGS. 5 and 6), and the control signal ROM
A circuit that generates the PRG (FIG. 5) will be described with reference to FIG.

As shown in FIG. 7, the low active clear terminals (CLR) of the three D-type flip-flops (D-type FFs) 71, 73, 75 are connected to the low active supplied from the power supply controller 39 shown in FIG. Are commonly supplied.

Independent I / O data (1 bit) is supplied from the CPU 11 to each data input terminal (D) of each of the three D-type FFs 71, 73, 75, and its clock terminal (CK) is supplied to the CPU 11 Is supplied. The negative-phase output QN of the D-type FF 71 is a signal DIS.
E #, the positive-phase output Q of the D-type FF 73 becomes the signal INV, and the positive-phase output Q of the D-type FF 75 becomes the signal ROMPRG. Next, a schematic operation of the system having the above configuration will be described with reference to a flowchart of FIG.

In the system having this configuration, after the power is turned on,
As shown in FIG. 8, first, the operation is performed according to the program stored in the boot block 172 of the BIOS-ROM 17 (step P1). Here, the system is E
By accessing the boot block 172 without performing the address conversion by the XOR gate 47, the far jump instruction 1
73, a C for performing a cyclic redundancy check (CRC) of the stored content of the BIOS-ROM 17
The RC routine 174 is executed.

If the CRC is successful (no CRC error), the present system performs the processing of step P2 shown in FIG. In step P2, the present system
The BIOS-ROM is set to the state shown in FIG.
17 addresses are translated. Further, in step P2, the present system
Address of an 8K byte area, that is, E000: 0000
-E000: mask the address in the range of FFFF,
Thereafter, the operation is performed according to the BIOS stored in the area of 0 to 64 Kbytes of the BIOS-ROM 17 and the application program stored in the system memory 13.

On the other hand, if the CRC is unsuccessful (there is a CRC error), the present system uses a floppy disk (FD) 80 for rewriting the BIOS to be described later with reference to FIG.
File from the floppy disk drive (internal FDD) 25 to the BIOS-ROM
17 and restore the stored contents of the BIOS-ROM 17 (step P3). Next, the operation shown in FIG.
This will be described in more detail with reference to the flowchart of FIG.

First, when the power switch of the present system is turned on, the power controller 39 outputs a low-level power-on reset signal. This power-on reset signal is commonly supplied to the clear terminals (CLR) of the three D-type FFs 71, 73, and 75 shown in FIG. This gives D
The FFs 71, 73 and 75 are all cleared and the signal DI
SE # goes high, the signal INV and the signal ROMP
RG goes low.

The power-on reset signal from the power controller 39 is also supplied to the CPU 11. Thus, the CPU 11 is reset (step S1). Then, the CPU 11 outputs an initial address for executing the far jump instruction, for example, FFFFF0, and a memory read instruction (S2). When this instruction is decoded by the CPU 11, the memory read signal MEMRD # becomes active level (low level).

The address (FF) output from the CPU 11
FFF0), the address bit A16 is the D-type FF7
3 and supplied to the EXOR gate 47 together with the signal INV. Here, since the signal INV is at the low level, the address bit A16 is supplied to the BIOS-ROM 17 via the EXOR gate 47 as it is. This BIOS-R
The address (F) output from the CPU 11 is stored in the OM 17.
The address bits A 0-15 of FFFF0) are also supplied as they are.

In this case, the CPU 11 sends the BIOS-
The address of the ROM 17 looks as shown in FIG. Therefore, the address bits A 0-16 (1FF) of the address FFFFF0 output from the CPU 11
By F0), the boot block 172 of the BIOS-ROM 17 is addressed. Then, the far jump instruction 173 stored in the area starting from the address 1FFF0 of the boot block 172 and the vector address indicating the jump destination in the boot block 172 are read. The CPU 11 executes the far jump instruction 17
3 according to the vector address (step S
3). After the far jump instruction 173 is executed, B
The 128-Kbyte area of the IOS-ROM 17 is the CPU
3, the last (High side) 12 of the 0-1 Mbyte area of the 16 Mbyte memory space is shown in FIG.
It appears to be in the 8K byte area.

At the jump destination specified by the vector address, a CRC routine 174 for executing a CRC of the stored contents of the BIOS-ROM 17 is stored. Therefore, when the far jump instruction 173 is executed, the CRC (Cy) of the stored contents of the BIOS-ROM 17 is subsequently executed.
clic Redundancy Check) is performed according to the CRC routine 174 (step S4).

As a result of execution of CRC routine 174, BI
CRC of OS-ROM 17 succeeded (no CRC error)
Is determined (step S5), the CPU 11 executes a routine 17 for address conversion and address masking.
According to No. 5, high-level I / O data is set in each of the D-type FFs 71 and 73 (step S6). As a result, the signal DISE # goes low, and the signal INV
Becomes high level. Then, the CPU 11 executes the BIOS-
It operates according to the BIOS stored in the area of 0-64 Kbytes of the ROM 17 and the application program stored in the system memory 13 (step S7).

When the CPU 11 accesses the BIOS, the CPU 11 accesses the BIOS of a conventional personal computer.
F000: 0000-F as in the case of OS access
000: Output an address within the range of FFFF (that is, F0000-FFFFF). In this case, if the address conversion by the EXOR gate 47 described below is not performed, the BIOS
If the OS-ROM 17 is accessed, FIG.
As can be seen from FIG. 7, there is a disadvantage that the boot block 172 or the system management routine in the BIOS-ROM 17 is accessed. However, in this embodiment, the BIOS in the BIOS-ROM 17 can be correctly accessed by the address conversion by the EXOR gate 47.

First, when the signal INV becomes high level in the process of step S6, the CPU 11 outputs a BIO signal.
Address Fxxxxx output to access S
(Xxxxxx is any of the range of 0000-FFFF)
A16 is inverted in level by the EXOR gate 47 and converted from "1" to "0". A16 whose logical value is converted to "0" is stored in the BIOS-ROM.
17 is supplied. On the other hand, A 0-15 of the address Fxxx is directly supplied to the BIOS-ROM 17.

As described above, the address Fxxx output from the CPU 11 for accessing the BIOS is Ex.
The data is converted to “xxx” and supplied to the BIOS-ROM 17. As a result, the area within the range of 0 to 64 Kbytes of the BIOS-ROM 17, that is, the BIOS is accessed. And C
As described above, the PU 11 enters a normal state operating according to the BIOS and the allocation program stored in the system memory 13.

In this state, the CPU 11 sets the address Exx.
XX is output. Exxxxx of this address
The address bit A16, which is the least significant bit of the most significant digit (hexadecimal value E), is at low level ("0").
The signal DISE # is also at the low level. Therefore, the output of the OR gate 59 to which the address bit A16 and the signal DISE # are supplied becomes low level. in this case,
The output of the NAND gate 61, that is, the chip select signal R
OMCS # goes high and the BIOS-ROM 17
Is in an access prohibited state.

As described above, according to the present embodiment, the CPU 11
In the normal state where the device operates according to the BIOS and the application program, the address E000: 0000-
E000: An address within the range of FFFF is masked. Therefore, in the normal state, 64
The K-byte memory space can be opened to a part other than the BIOS-ROM 17, and the memory space can be used efficiently. Also, this released memory space is defined as BIOS-
Even if it is assigned to a memory area other than the ROM 17 or an I / O area and the area is accessed, the BIOS-ROM
There is no danger of incorrect access to (the area of 64K-128K bytes) or rewriting of the system management routine stored in the BIOS-ROM 17.

On the other hand, if it is determined in step S5 that the CRC is unsuccessful (there is a CRC error), the CPU 11 follows the initialization routine 176 stored in the boot block 172 of the BIOS-ROM 17 according to the BIOS-ROM1.
7 performs an initialization process necessary to rewrite the contents of the main block 171 with correct data (step S
8). That is, in step S8, the CPU 11 initializes the display controller (DISP-CONT) 29, initializes the system memory 13, initializes the FDC (floppy disk controller) in the super integration IC (SI) 23, and sets the keyboard controller (KBC). And 33) initialization and the like. Next, the CPU 11
According to the transfer routine 177 stored in the boot block 172 of the BIOS-ROM 17, the following steps S9 to S13 are performed.

First, the CPU 11 controls the display controller 29 to display an operation guide screen indicating that a floppy disk (FD) 80 having a data structure as shown in FIG. 10 should be inserted into the floppy disk drive (internal FDD) 25. The information is displayed on the display panel 31 (step S9). On this screen, after inserting the floppy disk,
The display also indicates that any key on the keyboard (KB) 35 should be operated.

The user inserts the floppy disk (FD) 80 into the floppy disk drive (FDD) 25 according to the instruction on the display screen, and then operates an arbitrary key on the keyboard (KB) 3. This key operation is detected by the CPU 11 (step S1).
0).

Here, the floppy disk (FD) 80 shown in FIG. 10 will be described. This FD80 is
This is an FD for rewriting the BIOS-ROM. The FD 80 has a BIOS file 81 and this BIOS file 8
1 stores a rewriting routine 82 for rewriting (restoring) the storage contents of the BIOS-ROM 17. The BIOS file 81 stores a BIOS and a system management routine. At a predetermined position of the rewriting routine 82, this FD 80 is
The identification data ID indicating that it is for ROM rewriting is stored.

When the CPU 11 detects that a key operation has been performed in step S10, the CPU 11 reads the identification data ID from a predetermined position of the FD inserted into the FDD 25, and the data ID is unique to the BIOS-ROM rewriting FD. It is checked whether the data is correct (steps S11 and S12).

If it is determined in step S12 that the identification data ID is incorrect, the CPU 11 sends the FD inserted into the FDD 25 to the FD 8 for rewriting the BIOS-ROM.
It is determined that it is not 0, and the process returns to step S9.

On the other hand, if it is determined in step S12 that the identification data ID is correct, the CPU 11 determines that the FD 80 for rewriting the BIOS-ROM (FIG. 10) is correctly inserted into the FDD 25, and The stored rewriting routine 82 is transferred to the system memory 13 (step S13). Thereafter, the CPU 11 performs the following steps S14 to S16 according to the rewriting routine 82 transferred to the system memory 13.

First, the CPU 11 operates the D-type FF 7 shown in FIG.
5 is set to high level I / O data (step S14). As a result, the signal ROMPRG becomes high level, and the switch 45 switches to the + 12V side. Then, the BIOS-ROM 1 composed of a flash memory
+ 12V is supplied to the terminal PROG of No. 7 and the BIOS-R
Data writing to the OM 17 becomes possible.

At this time, the D-type FFs 71 and 73 are in the same state (clear state) as when the power was reset, so that the signal DISE # is at the high level and the signal INV is at the low level. When the signal INV is at a low level,
Address bit A16 from CPU 11 is used as BIO
It is supplied to the S-ROM 17. In addition, since the signal DISE # is at the high level, if the output of the AND gate 57 in the mask circuit 49 is at the high level, the signal ROMCS # is at the low level regardless of the value of the address bit A16, and the BIOS-ROM 17 Access becomes possible.

[0066] In this case, a condition in which the output of the AND gate 57 becomes a high-les-<br/> bell is two-fold. The first condition is that the address bits A17-23 are all "1", that is, the address A0-23 is FFxxx (when A16 = "1") or FExxxxxx (A16 = (In the case of “0”). The range of addresses satisfying the first condition is shown in FIG.
The last (High side) 1 of the area from 15 MB to 16 MB in the 16 MB memory space shown in FIG.
FE0000-FFFFFF indicating a 28-Kbyte area. The second condition is that address bits A17-19 are all "1" and address bits A20-23 are all "0", that is, address A 0-23 is 0F ×××× (A16
= "1") or 0Exxx (when A16 = "0"). The range of addresses satisfying the second condition is the last (High) of the area from 0 to 1 Mbyte in the 16 Mbyte memory space shown in FIG.
0E0000-0FF indicating the 128 Kbyte area of
FFF.

Therefore, in this embodiment, the terminal PROG of the BIOS-ROM 17 is set to +
When 12 V is supplied, if the address bits A17-23 output from the CPU 11 satisfy the above condition, the signal ROM A17-23 regardless of the value of the address bit A16.
CS # becomes low level, and the BIOS-ROM 17 can be accessed. That is, the entire area of the main block 171 of the BIOS-ROM 17 becomes write accessible.

Then, the CPU 11 proceeds to step S14.
Is executed, the data can be written to the BIOS-ROM 17, and the contents of the BIOS file 81 on the FD 80 inserted in the FDD 25 are stored in the BIOS.
The contents of the BIOS file 81 are transferred to the S-ROM 17 using an address that satisfies the above conditions.
The writing to the main block 171 of the ROM 17 is controlled (step S15). Thus, the main block 1 of the BIOS-ROM 17 where the CRC error is found
71 is an FD80 for rewriting the BIOS-ROM.
Is rewritten to the contents of the BIOS file 81 stored in the.

When the rewriting of the contents of the BIOS-ROM 17 is completed, the CPU 11 controls the display controller 29 to give an operation guide to the effect that the power of the system should be turned off once and the power should be turned on again.
1 (step S16). The operation of the system after the power is turned on again is the same as the above-described series of operations.

As described above, in the above embodiment, the flash memory is used as the BIOS-ROM 17, and the terminal area (120-
(128K bytes) of the boot block 172 that is accessible. In the normal state, the CPU 11
From the above, the area (0-64 Kbytes) in which the BIOS compatible with the conventional personal computer is stored is stored in the area (6) on the terminal area side of the BIOS-ROM 17.
4 to 128 Kbytes), the address output from the CPU 11 can be converted to more specifically address bits A16.
The BIOS can be accessed by inverting the bits of.

In the above embodiment, in the normal state, in order to prohibit the CPU 11 from accessing a storage area (64-128 Kbytes) other than the BIOS on the BIOS-ROM 17, an address designating the area is masked. ing. Therefore, the memory space allocated to this area can be opened to other than the BIOS-ROM 17. Further, this freed memory space is allocated to a memory area other than the BIOS-ROM 17 or an I / O area.
/ O area and accessing that area,
There is no possibility that the IOS-ROM 17 is accessed by mistake.

Furthermore, in the above embodiment, when an error is found in the contents of the BIOS-ROM 17 after the power is turned on, the data from the BIOS-ROM rewriting FD 80 is used to rewrite the contents of the BIOS-ROM 17 to correct data. Opening the device housing
Complicated work such as replacing the OS-ROM 17 is not required.

In this embodiment, even if the CPU 11 is reset by a factor other than the power reset, the D-type FF
71, 73 and 75 are not reset. Therefore, even if a reset other than the power reset occurs, the BIOS-R
Storage area other than BIOS on OM17 (64-128K
Byte), that is, a state in which access to the storage area of the boot block 172 and the system management routine is prohibited. (Second embodiment)

In the first embodiment, after the power is reset, when an error is found in the execution of the CRC on the contents of the BIOS-ROM 17, the BIOS file 81 stored in the FD 80 for rewriting the BIOS-ROM is flashed. The data is transferred to the BIOS-ROM 17 composed of a memory. However, the present invention is not limited to the above embodiment, and it is convenient to be able to rewrite the contents of the BIOS-ROM 17 as necessary, for example, in the case of upgrading the BIOS. Therefore, a second embodiment in which this kind of rewriting is possible will be described mainly with reference to the system configuration diagram of FIG. 1, the block diagram of FIG. 11, and the flowchart of FIG. In FIG. 12,
The same processing steps as those in FIG. 9 are denoted by the same reference numerals.

In this embodiment, for example, when a predetermined pin (I / O port) 92 of the 1-bit I / O register 91 shown in FIG. 11 is forcibly grounded, the CPU 11 shown in FIG. Floppy disk (FD) 80 to BI
The BIOS file 81 is transferred to the OS-ROM 17.

As shown in FIG. 11, the pin 92 of the I / O register 91 is pulled up to the power supply voltage + V via the resistor 93. Switch 94 is provided between the ground and pin 92 (G ND). Therefore, when the user turns on the switch 94, the pin 92 pulled up is forcibly grounded.

For this reason, if the power supply of the system is already on, when the switch 94 is turned on,
A low level signal is set in the / O register 91.
If the system power is not turned on when the switch 94 is turned on, a low-level signal is set in the I / O register 91 when the system power is turned on thereafter. Also, while turning on the system power switch,
When the switch 94 is turned on, a low-level signal is set in the I / O register 91.

When the power switch of the system is turned on, a power-on reset signal is output from the power controller 39, and the CPU 11 is reset as in the first embodiment (step S1 in FIG. 12). At this time, D
The FFs 71, 73 and 75 are all cleared and the signal DI
SE # goes high, the signal INV and the signal ROMP
RG goes low.

When reset, CPU 11 resets initial address FFFFF for executing the far jump instruction.
0 and a memory read instruction, and the BIOS-ROM 1
7 from the boot block 172 to the far jump instruction 17
3 and the vector address (step S in FIG. 12).
2) The instruction 173 is executed according to the vector address (step S3 in FIG. 12). The operation up to this point is the same as that of the embodiment described with reference to the flowchart of FIG.

Unlike the previous embodiment, a program for reading the contents (state) of the I / O register 91 shown in FIG. 11 and branching according to the contents is stored at the jump destination designated by the vector address. .

The CPU 11 operates according to the program
The contents of the register 91 are read (step S2 in FIG. 12).
1) Check whether the signal is at a low level (FIG. 12)
Step S22). If it is determined in step S22 that the content of the I / O register 91 is at the low level, the data is stored in the boot block 172 of the BIOS-ROM 17 in the same manner as in the case where the CRC error is detected in the above embodiment. Then, the process branches to an initialization routine 176.

Thereafter, as in the above-described embodiment, the processing of steps S8 to S13 shown in FIG. 9 is executed according to the initialization routine 176 and further the transfer routine 177 on the boot block 172. Accordingly, if the BIOS-ROM rewriting floppy disk (FD) 80 is correctly inserted into the floppy disk drive (FDD) 25, the rewriting routine 82 stored in the FD 80 is transferred to the system memory 13. .

Next, according to the rewriting routine 82 transferred to the system memory 13, step S shown in FIG.
The processing of 14 to S16 is executed. As a result, the FD
BIOS file 81 stored in BIOS 80
-The data is transferred to the main block 171 of the ROM 17, and the content of the block 171 is rewritten. Then, in accordance with the instruction displayed in step S16, when the user once turns off the power of the system and then turns on the power again,
A series of operations at the time of resetting the power supply are performed.

On the other hand, if it is determined in step S22 that the contents of the I / O register 91 are not at the low level, that is, if the pin 92 of the I / O register 91 is not grounded, the above-described embodiment will be described. Far jump instruction 173
Is executed, the process jumps to the CRC routine 174, and the processing after step S4 shown in FIG. 9 is performed.

As described above, according to the second embodiment, the BIO
Regardless of whether or not there is an error in the contents of the S-ROM 17,
It is possible to arbitrarily rewrite the BIOS-ROM 17.

In the above embodiment, the switch 94 is operated to forcibly ground the pin 92 of the I / O register 91, so that the BIOS-ROM
The processing for rewriting 17 is performed. However, the invention is not limited to this. For example, a keyboard (KB)
The rewriting process may be performed by operating the specific key 35.

The rewriting process described above can be performed not only at the time of power reset but also in a normal state. However, for this purpose, in the method in which the rewriting process is performed by turning on the switch 94, the switch 9 in the normal state is used.
It is necessary that the CPU 11 reads the I / O register 91 periodically or that the CPU 11 is interrupted when the switch 94 is turned on when the ON operation of the switch 4 is performed.

Here, the BIOS-RO in the normal state
Rewriting of M17 will be briefly described. First CPU
When detecting that the switch 94 is turned on or that a specific key of the keyboard (KB) 35 is operated in the normal state, the low level is set to the DFFs 71 and 73 in accordance with the BIOS on the BIOS-ROM 17. , Set to the same state as at power reset.

Next, the CPU 11 performs the same processing as steps S8 to S13 shown in FIG. However, this process is performed in accordance with the BIOS on the BIOS-ROM 17, and therefore, the boot block 17 of the BIOS-ROM 17
2 is different from steps S8 to S13 shown in FIG. This step S
8 to S13, the BIOS-
If the floppy disk (FD) 80 for rewriting the ROM is correctly inserted into the floppy disk drive (FDD) 25, the rewriting routine 82 stored in the FD 80 is transferred to the system memory 13.

Next, according to the rewriting routine 82 transferred to the system memory 13, step S shown in FIG.
The same processing as in steps S14 to S16 is executed. As a result, the BIOS file 81 stored in the FD 80 is transferred to the main block 171 of the BIOS-ROM 17, and the contents of the block 171 are rewritten. Here, when the user once turns off the power of the system and then turns it on again, a series of operations at the time of resetting the power are performed.

In the above embodiment, the floppy disk drive (FDD) 25 stores the BIOS-ROM
Although the BIOS file 81 was transferred to 17, the present invention is not limited to this. For example, a hard disk drive (HD
D) A BIOS file 81 and a rewriting routine 82 as shown in FIG. 10 are stored in a predetermined area of a hard disk mounted on the HDD 21, and the BIOS file 81 is transferred from the HDD 21 to the BIOS-ROM 17. Is also good. In this case, the CPU 11 performs initialization processing similar to step S8 shown in FIG.
5 to the system memory 13, and then transfer the BIOS file 81 from the HDD 25 to the BIOS-ROM 17 by the same processing as in steps S14 to S16 shown in FIG. Therefore,
The processing corresponding to steps S9 to S12 shown in FIG. 9 becomes unnecessary. Also, the BIOS-RO can be transmitted from another external storage device, for example, an optical disk device, a memory card, an expansion device, or the like.
The BIOS file may be transferred to M17.

[0092]

As described above, according to the present invention, when the flash memory is used as the BIOS-ROM, the boot area (boot block) and the BIOS are both in the same memory space from the data processing means. Boot area immediately after a power reset , even if it appears to be
Check the contents of the BIOS-ROM with access to the
If there is no problem with the contents of the BIOS-ROM, boot
Converts the address assigned to the area and the BIOS
By setting the address conversion function to be valid, the BIOS can be accessed by the address conversion function in a normal state after system startup, and the flash memory having a boot area is stored in the BIOS memory (BIOS) of the computer.
S-ROM).

Further, according to the present invention, in the normal state, by masking an address designating the inside of the storage area other than the BIOS on the BIOS-ROM, access in this area is prohibited. The allocated memory space can be released to other than the BIOS-ROM.

[0094]

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing a system configuration of a personal computer according to a first embodiment of the present invention.

FIG. 2 is a memory map showing a configuration of a BIOS-ROM 17 in FIG.

FIG. 3 is an exemplary view for explaining a memory space allocated to the BIOS-ROM 17;

FIG. 4 shows an address of a BIOS-ROM 17 and a BIOS-ROM which can be seen from a CPU 11 in FIG.
17 and the CPU 1 in the normal state.
1 and the same BIOS address as the BIOS-ROM 17
FIG. 7 is a diagram for explaining the relationship with the area of the OS-ROM 17 in comparison.

FIG. 5 is a diagram showing a basic configuration centering on an address circuit for addressing a BIOS-ROM 17;

6 is a circuit diagram showing a configuration of a mask circuit 49 in FIG.

FIG. 7 is a block diagram of a circuit that generates various control signals used in the address circuit and the like shown in FIG. 5;

FIG. 8 is a flowchart outlining the operation of the computer system shown in FIGS. 1 to 7;

9 is a flowchart showing details of the flowchart shown in FIG. 8;

FIG. 10 illustrates a BIOS transferred to the BIOS-ROM 17;
4 is a data map showing a configuration of a floppy disk (FD) storing a file.

11 is a block diagram showing a configuration for instructing a personal computer according to a second embodiment of the present invention to transfer a BIOS file from the floppy disk of the data map shown in FIG. 10 to the BIOS-ROM 17;

FIG. 12 is a flowchart for explaining an operation at the time of power-on of the system of FIG. 1 when the configuration shown in FIG. 11 is applied;

[Explanation of symbols]

11 CPU, 13 system memory, 15 system bus, 17 BIOS-ROM, 19, 23 super integration IC (SI), 25 internal FDD, 3
DESCRIPTION OF SYMBOLS 1 ... Display panel, 33 ... Keyboard controller (KBC), 35 ... Keyboard (KB), 39 ... Power supply controller, 47 ... EXOR gate, 49 ... Mask circuit, 51, 57 ... AND gate, 53 ... NOR gate, 5
5,59 ... OR gate, 61 ... Nand gate, 71,7
3, 75 D-type flip-flop, 91 I / O register, 45, 94 switch, 80 floppy disk (FD), 81 BIOS file, 82 rewrite routine, 171 main block, 172 boot block, 173: Far jump instruction, 174: CRC routine, 175: Address conversion and address mask routine, 176: Initialization routine, 177: Transfer routine

Continuation of the front page (56) References JP-A-4-69742 (JP, A) JP-A-6-175829 (JP, A) JP-A-6-266552 (JP, A) JP-A-2-23427 (JP) JP-A-2-81130 (JP, A) JP-A-3-150651 (JP, A) JP-A-63-244133 (JP, A) JP-A-2-236730 (JP, A) IEEE PACIFIC RIM CONF. ON COMMUNICAT IONS, COMPUTERS AND SIGNAL PROCESSIN G. vol. 2, May 1991, VIC TORIA, BC, CANADA p. 692-695 JEX [Flash memory or BIOS for PC and notbook bookcomputers] Electronic materials, 30 [3] (1991-3) p. 115-124. [528] (1991-5-27) Nikkei BP p. 225 (58) Fields surveyed (Int. Cl. ⁶ , DB name) G06F 9/06, 9/445, 13/10 G06F 12/06, 12/16 JICST file (JOIS)

Claims (8)

(57) [Claims] 1. A first storage area in which a read-only boot area is secured and a first basic input / output program (BIO)
A BIOS-ROM comprising a flash memory having a second storage area storing a basic input / output system (S; Basic Input / Output System), wherein a flash jump instruction is stored at a predetermined position in the boot area; An external storage device in which a second basic input / output program is stored; and immediately after a power reset, predetermined address data for executing the far jump instruction is output to the BIO.
Accessing the boot area of the S-ROM, and after the system startup, the operation according to the first basic input output program stored in the BIOS-ROM row and arm over data processing unit, after the system start-up Inverts a logical value of a predetermined bit for identifying the first storage area and the second storage area in an address output from the data processing means, and accesses the first storage area. Out to do
Stored in the second storage area at the input address.
To access the first basic input / output program
Are assigned to the first storage area and the second storage area.
Address translation means for translating the input address; masking means for masking an address designating the second storage area among addresses output from the data processing means after the system is started; and the external storage. Means for inputting an instruction to transfer the second basic input / output program stored in the device to the BIOS-ROM; and execution of the far jump instruction by the data processing means. First determining means for determining whether or not the instruction has been input; and when the first determining means determines that the instruction has not been input from the input means, the BIOS-R
Second determining means for determining whether the data stored in the OM is normal; and when the second determining means determines that the data stored in the BIOS-ROM is normal, the address conversion means and the mask. Means for setting the means to an effective state; and when the first determination means determines that the instruction is input from the input means, and when the second determination means stores the data stored in the BIOS-ROM. When it is determined that there is an abnormality, the second basic input / output program stored in the external storage device is stored in the BIOS-R.
A personal computer, characterized in that to transfer the OM and means for rewriting said first basic input output program stored in the BIOS-ROM. 2. A first storage area in which a read-only boot area is secured and a second storage area in which a basic input / output program is stored.
A flash memory having a flash memory in which a far jump instruction is stored at a predetermined position in the boot area, and a flash memory for executing the far jump instruction immediately after a power reset. Of the BIO
Accessing the boot area of the S-ROM, and after the system startup, the a row arm over data processing means an operation according to pre-Symbol basic input output program stored in the BIOS-ROM, said after system start-up, the Of the addresses output from the data processing means, the first storage area and the second
The logical value of a predetermined bit for identifying the storage area is inverted , and output to access the first storage area.
The address stored in the second storage area
Before accessing the first basic input / output program,
The addresses allocated to the first storage area and the second storage area.
Address conversion means for converting the address, and execution of the far jump instruction by the data processing means.
According to the line, is the data stored in the BIOS-ROM normal?
Determining means for determining whether or not the data is stored in the BIOS-ROM by the determining means;
Is determined to be normal, the address conversion means
Means for setting to a valid state . 3. After starting the system, the data processing means
The second storage area of addresses output from the stage
3. The personal computer according to claim 2 , further comprising mask means for masking an address designating the inside . 4. The system according to claim 1 , wherein said mask means starts up the system.
Address the output from the data processing unit after the bottom
The predetermined bit is a logical value indicating the second storage area
Access to the BIOS-ROM is prohibited
Characterized by having means for generating a signal
The personal computer according to claim 3 . 5. The method according to claim 1, wherein said BIOS-RO
When it is determined that the stored data of M is normal,
Means for setting the disk means to an effective state.
The personal computer according to claim 4, characterized in that: 6. A first storage area in which a boot area is secured.
And the second storage area where the basic input / output program is stored
BIOS-ROM composed of flash memory
Immediately after the power reset, the boot on the BIOS-ROM.
Output the specified address data that specifies the
After accessing the boot area and starting up the system,
Basic input / output program stored in the BIOS-ROM
Data processing means for performing the following operation, and output from the data processing means after the system is started.
Access the first storage area among the addresses
The output of the second storage area
Access the first basic input / output program stored in the
Address to specify the inside of the first storage area.
Address to an address specifying the inside of the second storage area.
Address conversion means for accessing the boot area by the data processing means.
Accordingly, whether the data stored in the BIOS-ROM is normal or not
Determining means for determining whether the data is stored in the BIOS-ROM by the determining means
Is determined to be normal, the address conversion means
Means for setting to a valid state . 7. After starting the system, the data processing unit
The second storage area of addresses output from the stage
Mask means for masking an address designating the inside
7. The personal computer according to claim 6, wherein: 8. The storage device according to claim 1 , wherein said masking means is provided in said second storage area.
BIO to mask the address that specifies
Means for generating a signal for inhibiting access to the S-ROM
The personal computer according to claim 7 , wherein the personal computer is provided.