JP2902006B2 - Information presentation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a CAD for LSI design which synthesizes a hardware configuration that realizes hardware operation specifications by inputting the specifications.
The present invention relates to an information presentation device for a system.

(Prior Art) In recent years, as the scale of LSIs has increased, systems for automating LSI design have been developed with the aim of improving design efficiency. These systems are generally systems that support logic design that automatically synthesizes logic circuits based on a hardware description language at the register transfer level.However, recently, an algorithm description is input as an operation specification, and a data path structure and Systems that support functional design that determine the operation for each cycle time have also been developed. However, since the functional design level has a wide range of design choices, it is extremely difficult for the designer to completely automatically determine the desired data path structure and operation for each cycle time without imposing constraints such as fixing the architecture. is there. For this reason, usually, when a designer inputs an instruction (hereinafter, abbreviated as a synthesis instruction) of items such as operation specifications and arithmetic unit restrictions into a system in a function design, the system synthesizes a design plan satisfying the input instruction. After performing the evaluation, the designer sees the evaluation result, inputs a new synthesis instruction, and repeats the operation of synthesizing the next design plan, thereby determining the design plan that is considered to be the best. Conventionally, in the above repetitive work,
Although all possible synthesis instructions have been examined one by one, there is a problem that this method is very inefficient because there is no history of synthesizing past design plans.

For example, the operation specification input by the synthesis instruction is fixed to one, and the input restriction is limited to the number and type of the arithmetic units, and the second
The data flow graph immediately after the ASAP scheduling shown in the figure shows the design proposal when the operation units are assigned with the constraint numbers 1 to 3 of the operation unit constraint table shown in FIG. It looks like Figure 6. Here, ASAP scheduling (As Soon As Posiible scheduling) is to extract the order and parallelism of the operations included in the specification description, and to execute each operation at the earliest possible step. Is to determine. In FIG. 3, an arithmetic unit surrounded by parentheses is shown, for example, (+) indicates an adder,
(×) has a multiplier function, and (+,-) has an addition / subtraction function
Indicates ALU. The nodes of the graphs in FIGS. 4 to 6 represent operations, and for the case where an operation unit is assigned to the node, the identification number of the operation unit that executes the operation is shown on the right side of the node. . A broken line indicates a step cut, and a number written on the left end of the broken line indicates a step number. However, it is assumed that the cycle time is 25 ns, and all operations fall within the cycle time. FIG. 7 shows a performance table that shows an estimate of the area and speed, which are the performance of each design plan in response to the synthesis instruction, from this design plan. Here, the area is the sum of the areas obtained by subtracting the area conversion table in FIG. 8 for each of the configurations of the arithmetic units used in each design plan, and the speed is obtained by multiplying the cycle time by the number of steps required for processing. Things.

Here, the design plan that the designer makes ideal is, for example, design plan 1
In order to determine how to change the synthesis instruction, it is effective for the designer to know the restrictions on the operation units when the design plan 1 is synthesized. For that purpose, a tool that can store a history of instructions given to the system by the designer for each design plan and refer to it as necessary is indispensable. However, no such tool exists at present.

(Problems to be Solved by the Invention) As described above, in the related art, in order to obtain the best design plan, the designer has given the system a synthesis instruction with all possible synthesis instructions. Then, the design was performed in a very inefficient manner of selecting a design plan close to the ideal from a large number of synthesized design plans.

The present invention has been made in view of the above circumstances,
By designating any one of n design plans (n is a natural number of 1 or more) synthesized according to a designer's instruction and displaying history information corresponding to the design plan, a new design plan is synthesized. It is an object of the present invention to provide an information presenting apparatus that presents reference information easily and at high speed in determining an instruction at the time.

[Configuration of the invention]

(Means for Solving the Problems) The present invention relates to a CAD system for synthesizing a hardware configuration that implements hardware specifications by inputting hardware operation specifications, and a design that stores the performance of the synthesized n pieces of hardware. Plan storage means, history information storage means for storing a set of n design parameters corresponding to the n design plans, design plan designating means for designating a specific design plan, and the designating means. It is characterized by comprising history extracting means for extracting history information corresponding to the designated design plan from the history information storage means, and history displaying means for displaying the history extracted by the history extracting means.

(Operation) In the present invention, a hardware configuration for realizing the specifications is synthesized by inputting hardware operation specifications.
In the LSI design CAD system, the design plan designating means first designates one of the design plans for n pieces of history information corresponding to the synthesized n design plans (n is a natural number of 1 or more). Next, history extraction means extracts history information corresponding to the designated design plan, and history display means displays the extracted history information.

(Embodiment) Hereinafter, an embodiment of the present invention is shown in the data flow graph shown in FIG.
This will be described in detail with reference to the drawings, taking as an example the case where arithmetic unit assignment is performed in step 3. FIG. 1 is a configuration diagram of one embodiment of the present invention. This device is composed of a design plan storage unit 1, a history information storage unit 2, a performance display unit 3, a design plan designation unit 4, a history extraction unit 5, a history display unit 5, and a display 7. .

The design plan storage unit 1 stores a design plan synthesized by the functional design support system, a computing unit constraint table used when synthesizing the design plan, and a performance table indicating the performance of each design plan. Example of design plan and performance table stored here
This is shown in FIGS. The design plan shown in FIGS. 4 to 6 is obtained by assigning the operation units to the data flow graph immediately after the ASAP scheduling shown in FIG. 2 by using the constraint numbers 1 to 3 of the operation unit constraint table shown in FIG. This is the design plan when it was done. The operation unit constraints shown in FIG. 3 are for instructing the operation units that can be used at the time of assignment of the operation units in the system.
The operation enclosed in parentheses in the figure represents one arithmetic unit. For example, (+) indicates an adder, (x) indicates a multiplier, and (+,-) indicate an ALU having addition and subtraction functions. The nodes in the graphs of FIGS. 4 to 6 represent operations, and for the case where an operation unit is assigned to a node, the identification number of the operation unit that executes the operation is shown on the right side of the node. A broken line indicates a step cut, and a number written on the left end of the broken line indicates a step number. However, the cycle time
It is assumed that all operations fall within the cycle time of 25 ns. FIG. 7 shows a performance table for storing an estimate of the area and speed, which is the performance of each design plan in response to the synthesis instruction, from this design plan. Here, the area is the sum of the areas obtained by subtracting the area conversion table in FIG. 8 for each of the configurations of the arithmetic units used in each design plan, and the speed is obtained by multiplying the cycle time by the number of steps required for processing. It is.

The history information storage unit 2 stores a history table of inputs to the function design support system. As system history information, there are restrictions on the types and number of computing units, input operation specifications, AS
The cycle time required for AP scheduling, synthesis strategy instruction, etc. can be considered, but for the sake of simplicity in this embodiment, the cycle time is fixed at 25 ns, and the types of available computing units that the designer instructs the system when synthesizing the design proposal And only the number constraint are used as history information. The history table stores a design number and a constraint number of a computing unit constraint table used when the design numbers are combined. FIG. 9 shows an example of the history table.

The performance display unit 3 first retrieves all design numbers and corresponding constraint numbers from the history information storage unit 2. Next, the performance table stored in the design plan storage unit 1 is retrieved using the constraint number, and the performance for all design plans is obtained. Then, the performance of each design plan is plotted on a graph in which the horizontal axis of the display 7 is the area and the vertical axis is the speed, with a circle written around the design number.

The design plan designation section 4 selects one design plan from the graph displayed by the performance display section 3 and inputs the design number from, for example, a keyboard.

The history extracting unit 5 refers to the history table stored in the history information storage unit 2 based on the design number specified by the design plan designating unit 4 and determines the constraint number when the design plan of the design number is synthesized. Then, the operator constraint is obtained by subtracting the operator constraint table shown in FIG. 3 from the constraint number.

The history display unit 6 displays on the display 7 the arithmetic unit restrictions selected by the history extraction unit 5. Here, the area-speed graph of the performance display unit 3 and the arithmetic unit restrictions of the history display unit 6 are both displayed on the display 7, and the display method is a known multi-window method. In the present embodiment, two windows are used and are called a graph window 8 and an information display window 9, respectively.

Now, an example is given in which the performance table of FIG. 7 is displayed, and one of the design plans is designated to obtain the operation unit constraint when the design plan is synthesized. It shows how it works and how the process is performed.

The performance display unit 3 selects a design number and its performance for all data in the performance table of the design plan storage unit 1,
In the graph window 8, the horizontal axis represents the area, and the vertical axis represents the speed.
Figure).

Next, the design plan designating unit 4 searches the performance graph displayed by the performance display unit 3 for a design plan close to the ideal performance of the designer, and inputs the design number of the design plan from the keyboard.
Here, for example, when the performance of the design number 1 is close to the ideal and it is considered to create a higher-speed design plan while keeping the area as it is with reference to the constraint of the arithmetic unit, 1 is input.

Further, the history extracting unit 5 obtains the constraint number 1 corresponding to the design number 1 by referring to the history table of FIG. 9 using the design number 1 inputted by the design plan designating unit 4, and calculates the arithmetic unit with the constraint number 1. Referring to the constraint table, arithmetic unit constraint = ｛(+, −).
(X)｝ is obtained.

Finally, the history display unit 6 selects the operation unit constraint selected by the information extraction unit 5 = {(+,-). (×)｝ is displayed in the information display window 9 together with the design number (FIG. 11).

Here, looking at the constraints of the operation unit of the design plan 1, the ALU and the multiplier are used. Therefore, in order to increase the speed without changing the area, we will adopt a policy that uses ALUs but has different functions and synthesizes a new design plan. Therefore, an operator constraint using the ALU of (−, ×) instead of the ALU of (+, −), that is, the constraint number 4 is specified (the twelfth constraint).
FIG. 13), when the design plan 4 is synthesized, the data flow graph is as shown in FIG. 13, and the performance is as shown in FIG. As described above, by inputting the arithmetic unit constraint using the design history as a guideline, a high-speed design plan 4 having the same area as the design plan 1 and having the same area can be obtained.

As described above, by designating one of the synthesized design plans, the design plan and the history corresponding to the design plan can be displayed easily and quickly, and the designer can display the history as a guideline. As a result, a new design plan can be synthesized.

It should be noted that the present invention is not limited to the above-described embodiments, but can be implemented in an appropriate mode by making appropriate design changes. In the above embodiment, for simplicity,
Although the case where only the operation unit constraint instruction is used as the history is shown, the present invention can be implemented even if all of the input operation specifications, the synthesis result correction instruction, the synthesis strategy instruction, the work execution date, etc. are included in the history. It is. For example, an item for storing a pointer to a table in which a register sharing work history is recorded is added to the items of the history table in FIG. 9, and the leading pointer of the table is stored in the item, thereby making the register sharing work possible. The history can be displayed together with the operation unit restrictions. Furthermore, when the number of objects to be recorded is increased, the information to be displayed when a certain design proposal is instructed can be limited to, for example, information such as synthesis strategy instruction information, or can be all of the stored history. It is. As a result, only the information necessary for the designer can be highlighted and displayed.

Of course, in the above-described embodiment, the designating unit 4 inputs the design number of the design plan. However, by picking a circle plotted on the performance graph displayed in the graph window 8 using a mouse, the design unit 4 is input. It is also possible to further improve the operability by changing the input method so as to select.

Further, by adding an information display window, histories for a plurality of design plans can be easily displayed and compared at the same time.

〔The invention's effect〕

As described above, according to the present invention, by designating any of n (n is a natural number of 1 or more) design plans synthesized according to a designer's instruction, history information corresponding to the design plan can be obtained. By displaying the information, it is possible to easily and quickly present information that is helpful in determining an instruction when synthesizing a new design plan.

The designer can use that information to determine how to change the synthesis instruction, and it is extremely efficient to select a design idea that is close to ideal from all conventional possible design ideas. Therefore, it is not necessary to use a system having a bad design, and an ideal design plan can be efficiently obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an information presenting apparatus according to one embodiment of the present invention, FIG. 2 is a data flow graph immediately after ASAP scheduling for explaining the information presenting apparatus, and FIG. Figure showing the table, FIG. 4,
FIGS. 5 and 6 are diagrams showing design plans when arithmetic units are assigned to the data flow graphs of FIG. 2 with the constraint numbers 1 to 3 of the arithmetic unit constraint table, and FIG. 7 shows the performance of the design plans. FIG. 8 is a diagram showing a table for storing the area of the arithmetic unit, FIG. 9 is a diagram showing a history table, and FIG. 10 is a graph window showing the performance of the design proposals 1 to 3. The displayed figure, FIG. 11 is a view in which the system displays the operation unit restrictions of the design plan 1 in the information display window, and FIG.
FIG. 13 is a diagram showing a history table when design instruction synthesis is instructed with constraint number 4, and FIG. 13 shows a case where arithmetic units are assigned to the data flow graph of FIG. 2 with constraint number 4 of the arithmetic unit constraint table. FIG. 14 is a diagram showing a design plan, and FIG. 14 is a diagram showing a performance table for storing the performance of the design plan 4. 1 Design plan storage unit 2 History information storage unit 3 Performance display unit 4 Design plan designation unit 5 History extraction unit 6
... History display section, 7 display, 8 graph window, 9 information display window.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-205771 (JP, A) JP-A-2-162466 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 17/50 JICST (JOIS)

Claims (2)

(57) [Claims] In a CAD system for synthesizing a hardware configuration for realizing the hardware operation specifications by inputting the hardware operation specifications, design plan storage means for storing the performance of the synthesized n pieces of hardware, History information storage means for storing a set of n design parameters corresponding to each design plan, design plan designating means for designating a specific design plan, and design plan designating means designated by the designating means. An information presentation device comprising: a history extracting unit that extracts history information from the history information storage unit; and a history display unit that displays the history extracted by the history extracting unit. 2. The information presentation apparatus according to claim 1, wherein the performance of the hardware is an area and a speed.