JP2892117B2 - A method of manufacturing a semiconductor device - Google Patents

A method of manufacturing a semiconductor device

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Publication number
JP2892117B2
JP2892117B2 JP20454190A JP20454190A JP2892117B2 JP 2892117 B2 JP2892117 B2 JP 2892117B2 JP 20454190 A JP20454190 A JP 20454190A JP 20454190 A JP20454190 A JP 20454190A JP 2892117 B2 JP2892117 B2 JP 2892117B2
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Prior art keywords
resin
semiconductor device
insulating substrate
epoxy resin
bumps
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Expired - Fee Related
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JP20454190A
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Japanese (ja)
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JPH0491443A (en )
Inventor
カオ・ミン・タイ
次雄 坂本
雅之 斉藤
道也 東
三樹 森
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株式会社東芝
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、絶縁基板と半導体素子とがフリップチップ方式で接続された半導体装置の製造方法に関する。 DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (FIELD OF THE INVENTION) The present invention relates to a method for manufacturing a semiconductor device and the insulating substrate and the semiconductor element are connected by a flip chip method.

(従来の技術) 近年、半導体集積回路技術の進歩により、端子数が10 Advances in (prior art) In recent years, semiconductor integrated circuit technology, the number of terminals 10
0を越える半導体素子やパッドピッチが100μm以下の半導体素子が出現してきている。 Semiconductor elements and pad pitch exceeding 0 have appeared the following semiconductor device 100 [mu] m. それに伴い半導体素子の実装密度を高めるために、組立て時に電極の数に依存せず、一度にボンディングが可能でチップの実装が極めて小容積にできる、フリップチップ方式,ビームリード方式,テープキャリヤ方式等のワイアレスボンディングが注目されている。 To increase the packing density of the semiconductor device with it, without depending on the number of electrodes during assembly, can be the bonding is possible chip implementation of a very small volume at a time, flip chip method, beam lead method, a tape carrier system or the like wireless bonding of attention has been paid. 特にフリップチップ方式は他の方式のものよりボンディング強度が強く、信頼性が高いので期待されている。 In particular flip chip method has stronger bonding strength than the other methods, is expected because of its high reliability.

第5図にはフリップチップ方式を用いた従来の半導体装置の一例が示されている。 The Figure 5 is shown an example of a conventional semiconductor device using the flip chip method.

半導体素子1にはPb−Sn等の半田バンプ2が形成されている。 Solder bumps 2, such as Pb-Sn is formed in the semiconductor element 1. そしてバンプ2と、絶縁基板3に設けられた配線4とが相対向して接合している。 And the bumps 2, a wiring 4 formed in the insulating substrate 3 is bonded to face. このように構成された半導体装置では、半導体素子1と絶縁基板3との接合部であるバンプ2の接点柔軟度が低く、半導体素子1と絶縁基板3との熱膨張係数の不一致からバンプ2に熱歪みが生じ易いので接合不良が発生したり、最悪の場合には疲労破壊するという問題があった。 In the semiconductor device having such a configuration, the contact flexibility of the bump 2 is a junction between the semiconductor element 1 and the insulating substrate 3 is low, the mismatch in thermal expansion coefficient between the semiconductor element 1 and the insulating substrate 3 to the bump 2 bonding failure may occur because it is easy heat distortion occurs, in the worst case there is a problem that fatigue fracture.

そこで、第6図に示すように絶縁基板3と半導体素子1との間の隙間に保護用の樹脂5を充填してバンプ2を補強する半導体装置が考え出された。 Therefore, by filling a resin 5 for protection in the gap between the insulating substrate 3 and the semiconductor element 1 as shown in FIG. 6 semiconductor device that reinforces the bump 2 it is devised. このような半導体装置では、絶縁基板3と半導体素子1との間の隙間が狭いので、樹脂5を隙間に充填するために、樹脂5の粘度を低くする必要があった。 In such a semiconductor device, since a narrow gap between the insulating substrate 3 and the semiconductor element 1, in order to fill the resin 5 into the gap, it is necessary to lower the viscosity of the resin 5.

粘度を低くするには樹脂5の充填剤の含有量を減らせばよい。 To lower the viscosity may Reducing the filler content of the resin 5. しかしながらこのような樹脂5でバンプ2を封止すると、樹脂5の充填材の含有量が減った結果、樹脂5と絶縁基板3との熱膨張係数の差、樹脂5と半導体素子1との熱膨脹係数の差が大きくなり、熱ストレスに弱くなり信頼性が低下する。 However, when sealing the bumps 2 in such a resin 5, as a result of the content of the filler of the resin 5 is decreased, the difference in thermal expansion coefficient between the resin 5 and the insulating substrate 3, the thermal expansion between the resin 5 and the semiconductor element 1 difference coefficient is increased, weakened reliability thermal stress is reduced. たとえば、多量の樹脂5を用いてバンプ2を封止した半導体装置に熱衝撃試験を行ったところ、樹脂5やバンプ2に亀裂が入るという結果を招いた。 For example, was subjected to a thermal shock test in a semiconductor device encapsulated with bumps 2 with a large amount of resin 5, led to results that cracks in the resin 5 and the bump 2. また、熱衝撃試験でバンプ2に亀裂が入らない程度の量の樹脂5を用いてバンプ2を封止した半導体装置では、封止性が悪くなり信頼性が低下する。 In the semiconductor device encapsulated with bumps 2 with the amount of resin 5 to the extent that cracking does not enter into the bumps 2 in thermal shock test, sealing performance is deteriorated reliability is lowered. たとえば、高温高湿試験を行ったところ、樹脂5内に水分が容易に浸入した。 For example, was subjected to high-temperature high-humidity test, moisture is easily penetrates into the resin 5.

また、樹脂5に溶剤を混合しても粘度を低くすることができる。 Further, it is possible to lower the viscosity by mixing the solvent with the resin 5. しかしながらこのような樹脂5でバンプ2を封止すると、絶縁基板3と半導体素子1との間の隙間が狭いので、樹脂5が硬化するときに溶剤が完全に揮発しなかったり、溶媒が揮発するときの発砲により接続不良が生じたり、または溶剤が揮発するときに発生したボイドが完全に消滅せず、これが原因して樹脂5中に水浸入路が形成され、装置の信頼性が低下するという問題があった。 However, when sealing the bumps 2 in such a resin 5, since the narrow gap between the insulating substrate 3 and the semiconductor element 1, or not solvent is completely evaporated when the resin 5 is cured, solvent volatilizes that poor connection or caused by fire, or solvent voids that occur when the volatilization is not completely eliminated, this water entry path is formed in the resin 5 by causing the reliability of the device is reduced when there was a problem. とくに高温高湿に対する信頼性が悪かった。 In particular, it was poor reliability with respect to high-temperature and high-humidity.

(発明が解決しようとする課題) 上述の如くバンプを樹脂で封止するには、樹脂の粘度を下げる必要があった。 (Inventive will to challenge Solved) above as bumps is sealed with resin, it is necessary to lower the viscosity of the resin. そのために充填剤の含有量が少ない樹脂でバンプを封止した半導体装置があったが、このような半導体装置では樹脂と絶縁基板及び半導体素子とのそれぞれの熱膨張係数の差が大きいので熱ストレスに弱く、亀裂が生じ易くなり、信頼性が低下するという問題があった。 There was a semiconductor device encapsulated with bumps in the resin containing a small amount of the filler for the thermal stress because the difference between the respective thermal expansion coefficients of such a semiconductor device with the resin and the insulating substrate and the semiconductor element is large weakly, easily crack occurs, the reliability is lowered. また、溶剤が混合した樹脂でバンプを封止した半導体装置もあったが、このような半導体装置では溶剤が揮発する際に生じる発砲による断線や、樹脂内に残ったボイドに起因する水分浸入により信頼性が低下するという問題があった。 Although solvent was also a semiconductor device encapsulated bumps in a mixed resin, or disconnection by fire which occurs when the solvent is volatilized in such a semiconductor device, the moisture penetration due to voids remaining in the resin reliability is lowered.

本発明は、上記事情を考慮してなされたもので、その目的とするところは、耐熱衝撃性,耐湿性に優れた半導体装置の製造方法を提供することにある。 The present invention has been made in view of these circumstances, and its object is to provide thermal shock resistance, a method of manufacturing a semiconductor device with excellent moisture resistance.

[発明の構成] (課題を解決するための手段) 上記の目的を達成するために、本発明の半導体装置の製造方法は、絶縁基板と、この絶縁基板に形成された配線にバンプを介してフェイスダウンに接続された半導体素子と、前記バンプを封止する樹脂組成物とを有する半導体装置の製造方法において、溶剤を含まない第1の樹脂組成物で前記バンプを封止する工程と、前記絶縁基板に接合に保ちつつ前記第1の樹脂組成物を溶剤を含む第2の樹脂組成物で覆う工程とを有することを特徴とする。 [Configuration of the Invention] To achieve the above object (Means for Solving the Problems) The method of manufacturing a semiconductor device of the present invention includes an insulating substrate, via the bumps to wiring formed on the insulating substrate a semiconductor element connected to the face-down, in the manufacturing method of a semiconductor device having a resin composition for sealing the bumps, the step of sealing the bumps in the first resin composition containing no solvent, the said first resin composition while keeping the bonding to the insulating substrate and having a step of covering with a second resin composition containing a solvent.

(作用) 本発明によれば、バンプを封止している第1の樹脂組成物を第2の樹脂組成物で覆ったので、第1の樹脂組成物自身または第1の樹脂組成物と絶縁基板との界面から浸入する水分等を防止できる。 According to (action) the present invention, since the cover the first resin composition which seals the bumps in the second resin composition, the first resin composition itself or the first resin composition and the insulating It can prevent moisture from entering from the interface with the substrate. また、第2の樹脂組成物は溶剤を含むので硬化する際に比重の重い充填剤が沈降し、絶縁基板付近での充填剤の濃度が高くなる。 The second resin composition is precipitated heavy filler with a specific gravity when the cure because it contains a solvent, the higher the concentration of filler in the vicinity of the insulating substrate. その結果、第2の樹脂組成物と絶縁基板との界面から浸入する水分等を防止でき、また、絶縁基板と第2の樹脂組成物との界面近傍での熱膨張係数の差が小さくなるので剥離,亀裂が発生し難くなる。 As a result, it is possible to prevent moisture from entering the interface between the second resin composition and the insulating substrate, also, the difference between the insulating substrate and the thermal expansion coefficient in the vicinity of the interface between the second resin composition is reduced peeling, cracking hardly occurs. さらに溶剤により第1の樹脂組成物と第2の樹脂組成物とが溶着するので第1の樹脂組成物と第2の樹脂組成物との密着強度が強まる。 Furthermore the adhesion strength between the first resin composition and the second resin composition since the first resin composition and the second resin composition is welded is strengthened by the solvent.

(実施例) 以下、図面を参照しながら実施例を説明をする。 (Example) Hereinafter, the description of the embodiments with reference to the accompanying drawings.

第1図は本発明の第1の実施例に係る半導体装置の断面図を示し、第2図は同半導体装置の平面図を示している。 Figure 1 shows a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, Figure 2 shows a plan view of the semiconductor device. なお、第1図は第2図の半導体装置のA−A線に沿った断面図である。 Incidentally, FIG. 1 is a sectional view taken along line A-A of the semiconductor device of FIG. 2.

これを製造工程に従い説明すると、最初、半導体素子 This will be described in accordance with manufacturing processes, first, a semiconductor element
11の電極、すなわちアルミボンディングパッド上に、銅バンプをコアとし、電気メッキにより半田バンプ12を形成する。 11 of the electrode, i.e. on the aluminum bonding pad, the copper bumps as the core, by electroplating to form the solder bumps 12. 次に、厚さ1mm程度の無アルカリガラスからなる絶縁基板13上に、ITO(Indium Tin Oxide),クロム,金をそれぞれ厚さ1000Å,1000Å,2000Å程度に蒸着し、この金属積層膜をパターニングして配線14を形成する。 Next, on the insulating substrate 13 made of alkali-free glass having a thickness of about 1mm, ITO (Indium Tin Oxide), deposited chromium, respectively thickness 1000Å gold, 1000Å, to about 2000 Å, and patterning this metal laminated film Te to form the wiring 14.

次に、バンプ12と配線14との位置合わせを行い、半導体素子11と絶縁基板13とをフェイスダウンで接合する。 Next, the alignment between the bumps 12 and the wiring 14, a semiconductor element 11 and the insulating substrate 13 is bonded face-down.
このときの位置合わせの方法として、半導体素子11と絶縁基板13とにそれぞれ位置合わせ用のマークを設け、対応するマーク同士を一致させることにより位置合わせしてもよい。 As a method for alignment of this time, it provided the mark respectively for alignment in the semiconductor element 11 and the insulating substrate 13 may be aligned by matching the corresponding mark each other.

次に、半導体素子11と絶縁基板13との間の隙間に、第1の樹脂組成物として例えば、溶剤を含まないエポキシ樹脂15を含浸する。 Then, the gap between the semiconductor element 11 and the insulating substrate 13, for example, as a first resin composition, impregnating the epoxy resin 15 that does not contain a solvent. そして、エポキシ樹脂15が半導体素子11と絶縁基板13との間の線間を埋めてバンプ12を封止したら、所定の硬化条件よりも緩やかな条件でエポキシ樹脂15を硬化させ半硬化状態に保つ。 Then, when sealing the bumps 12 to fill the inter-line between the epoxy resin 15 between the semiconductor element 11 and the insulating substrate 13 is kept in a semi-cured state to cure the epoxy resin 15 in moderate conditions than the predetermined curing conditions .

次に第2の樹脂組成物としてフェノール硬化エポキシ樹脂16を用いて、エポキシ樹脂15が露出しないように覆う。 Then with phenol cured epoxy resin 16 as a second resin composition, covering as epoxy resin 15 is not exposed. このとき第1図,第2図に示すように、フェノール硬化エポキシ樹脂16が半導体素子11の裏面を覆い半導体素子11を保護すると共に、フェノール硬化エポキシ樹脂 Figure 1 this time, as shown in FIG. 2, with a phenol cured epoxy resin 16 protects the semiconductor element 11 covers the back surface of the semiconductor element 11, a phenol cured epoxy resin
16と半導体素子11及び絶縁基板13との密着強度を強め、 16 and strengthening the adhesion strength between the semiconductor element 11 and the insulating substrate 13,
半導体素子11と絶縁基板との接続を強固なものとする。 The connection between the semiconductor element 11 and the insulating substrate and strong.

この後、エポキシ樹脂15,16を同時に本硬化して半導体素子11及び絶縁基板13との接合が完成する。 After this, the bonding between the semiconductor element 11 and the insulating substrate 13 by the curable epoxy resin 15, 16 at the same time to complete. ここで、 here,
エポキシ樹脂15を半硬化状態にし、このエポキシ樹脂15 The epoxy resin 15 and a semi-cured state, the epoxy resin 15
をフェノール硬化エポキシ樹脂16で覆い、両エポキシ樹脂15,16を同時に硬化する方法を採用したのは、この方法が最もエポキシ樹脂15,16間の密着性が良くなるからである。 Covered with phenol cured epoxy resin 16, was adopted a method of curing both epoxy resin 15 and 16 at the same time, this method is because most adhesion between the epoxy resin 15 and 16 is improved.

上述したフェノール硬化エポキシ樹脂16として第1表に示したものが使用できる。 Those shown in Table 1 as a phenol cured epoxy resin 16 as described above can be used. 例えば、住友化学社製の多官能エポキシ樹脂(ESX−221),昭和高分子社製のフェノール樹脂(BRG−556),東芝セラミック社製のシリカ充填材,UCC社製のシランカップリン剤,三菱化成社製のカーボンブラック,四国化成社製のイミダゾール系触媒,一般市販の酢酸セロソルブ,トルエン,MEKをそれぞれ13.2,6.0,80.0,0.5,0.3,0.1,6.0,6.0,6.0重量部で組成したもの用いる。 For example, Sumitomo Chemical Co., Ltd. of polyfunctional epoxy resin (ESX-221), Showa Kobunshi Co. phenolic resin (BRG-556), Toshiba Ceramic Co. silica filler, UCC Co. silane coupling agent, Mitsubishi those compositions Kasei carbon black, manufactured by Shikoku Chemicals Corporation imidazole-based catalyst, the general commercial cellosolve acetate, toluene, MEK at each 13.2,6.0,80.0,0.5,0.3,0.1,6.0,6.0,6.0 parts used.

このようにして製造された半導体装置では、バンプ12 In the semiconductor device manufactured in this way, the bumps 12
を封止したエポキシ樹脂15がフェノール硬化エポキシ樹脂16により覆われているので、エポキシ樹脂15とバンプ Because sealed epoxy resin 15 is covered by a phenolic-cured epoxy resin 16, epoxy resin 15 and the bumps
12の界面から浸入する水分等を防止できる。 Water or the like intruding from 12 interface can be prevented. また、エポキシ樹脂16は溶剤を含むので傾斜材料の役割を果たすため、エポキシ樹脂16中の組成物に浮沈が生じ、硬化する際に比重の重い充填剤が沈降し、絶縁基板13とエポキシ樹脂16との接合面近傍で充填剤の濃度が高くなる。 Also serves gradient material for since the epoxy resin 16 containing a solvent, floating and sinking occurs in the composition of the epoxy resin 16, a heavy filler to settle specific gravity upon curing, insulating substrate 13 and the epoxy resin 16 the concentration of the filler is increased by bonding the vicinity of the. その結果、絶縁基板13とエポキシ樹脂16との接合面に水分等が入し難くなり、耐湿性が向上する。 As a result, moisture and the like at the interface between the insulating substrate 13 and the epoxy resin 16 is hardly incident to improve the moisture resistance. また充填剤と絶縁基板13との熱膨張係数の差は小さいため、絶縁基板13に接合するエポキシ樹脂16の熱膨張係数が絶縁基板13のそれに近付き、剥離や亀裂が生じ難くなり、耐熱衝撃性が向上する。 Since the difference in thermal expansion coefficient between the filler and the insulating substrate 13 is small, the thermal expansion coefficient of the epoxy resin 16 for bonding the insulating substrate 13 approaches to that of the insulating substrate 13, becomes the peeling and cracking hardly occurs, the thermal shock resistance There is improved. またエポキシ樹脂16に含まれる溶剤により、 By addition the solvent contained in the epoxy resin 16,
僅かであるが、エポキシ樹脂15が溶かされ、溶着が生じ、エポキシ樹脂15とエポキシ樹脂16との密着強度が強くなり信頼性が向上する。 Is a small, epoxy resin 15 is melted, the welding occurs, thereby improving the adhesion strength becomes stronger reliability of the epoxy resin 15 and the epoxy resin 16.

本実施例のように、バンプ12を溶剤を含まない第1の樹脂組成物で封止し、更にこの第1の樹脂組成物を溶剤を含む第2の樹脂組成物で覆うことで、耐湿性、耐熱衝撃性が改善され、信頼性の高い半導体装置を得ることができる。 As in this embodiment, the bumps 12 sealed by the first resin composition containing no solvent, by further covering the first resin composition in the second resin composition containing a solvent, moisture resistance , thermal shock resistance is improved, it is possible to obtain a highly reliable semiconductor device.

なお、本実施例では半硬化状態のエポキシ樹脂15をフェノール硬化エポキシ樹脂16で覆った後、両エポキシ樹脂15,16を同時に硬化させたが、必要に応じて、例えば製品形態や仕様状況に合わせて、所定の硬化条件で硬化させたエポキシ樹脂15をエポキシ樹脂16で覆ってもよい。 Note that in this embodiment the epoxy resin 15 in a semi-cured state was covered with a phenolic curing epoxy resin 16 has been cured both epoxy resin 15 and 16 at the same time, if necessary, for example, match the product forms and specifications conditions Te, the epoxy resin 15 may be covered with an epoxy resin 16 was cured at a predetermined curing condition. 逆に、半導体素子11と絶縁基板13との間の隙間に含浸した直後のエポキシ樹脂15、すなわちほとんど硬化してない状態でエポキシ樹脂15をエポキシ樹脂16が覆い、 Conversely, the epoxy resin 15 immediately after impregnation in the gap between the semiconductor element 11 and the insulating substrate 13, i.e., the epoxy resin 15 covers the epoxy resin 16 in a state that hardly cured,
両エポキシ樹脂15,16を同時に硬化させてもよい。 Both epoxy resin 15, 16 may be cured simultaneously.

第3図には本発明の第2の実施例に係る半導体装置の断面図が示されている。 It is shown cross-sectional view of a semiconductor device according to a second embodiment of the present invention in Figure 3. なお、第1図と同一部分には同一符号を付して詳しい説明は省略する。 Incidentally, in FIG. 1, the same parts more are denoted by the same reference numerals description is omitted.

この実施例が先に説明した実施例と異なる点は、フェノール硬化エポキシ樹脂16aが半導体素子11の裏面を覆わないで、溶剤を含まないエポキシ樹脂15を封止したことにある。 Example differs from the embodiment described above, the in phenol cured epoxy resin 16a does not cover the back surface of the semiconductor element 11 is to seal the epoxy resin 15 that does not contain a solvent. このようにして製造された半導体装置では、 In the semiconductor device manufactured in this way,
半導体素子11がエポキシ樹脂16aにより保護されず露出するが、耐環境試験の結果は第1の実施例のそれと較べても遜色なく、信頼性が向上したのを確認した。 Although the semiconductor element 11 is exposed without being protected by an epoxy resin 16a, the result of the environmental test is not favorably compared to that of the first embodiment, it was confirmed that the reliability is improved.

第4図に本発明の第3の実施例に係る半導体装置の断面図を示す。 It shows a cross-sectional view of a semiconductor device according to a third embodiment of the present invention in Figure 4. なお、第1図と同一部分には同一符号を付して詳しい説明は省略する。 Incidentally, in FIG. 1, the same parts more are denoted by the same reference numerals description is omitted.

この実施例が第1,第2の実施例と異なる点は、半導体素子11と絶縁基板13との間の隙間をエポキシ樹脂15で完全に埋めていないことにある。 This embodiment first is different from the second embodiment, there the gap between the semiconductor element 11 and the insulating substrate 13 that is not completely filled with epoxy resin 15. すなわちエポキシ樹脂15 That epoxy resin 15
aは、バンプ12を封止するのに必要な部分だけ半導体素子11と絶縁基板13との間の隙間を埋めている。 a is fills a gap between only the parts required to seal the bumps 12 and the semiconductor element 11 and the insulating substrate 13.

この実施例では、中央部分に空気が存在しているが、 In this embodiment, the air is present in the central portion,
これにより信頼性が損なわれることはなく、先の実施例と同様の効果が得られた。 Thus never reliability is impaired, the same effect as the previous embodiment is obtained.

本発明者等は、第1図,第3図,第4図に示される構成の半導体装置と、第6図に示される構成の半導体装置との耐環境性を実際の装置を用いて調べてみた。 The present inventors have first view, FIG. 3, and examined using a semiconductor device of the structure shown in Figure 4, the actual device environment resistance of the structure of the semiconductor device shown in FIG. 6 saw.

−40〜100℃で1サイクル各30分の熱衝撃試験を行ったところ、第1図,第3図,第4図に示される構成の半導体装置の600サイクル後におけるそれぞれのバンプ接合部分の抵抗は約1Ω以下であったが、第6図に示される構成の半導体装置では300サイクルを経過しないうちに、樹脂5に亀裂が入り接続が取れなくなる部分が生じた。 -40 to 100 was subjected to a thermal shock test of one cycle each 30 minutes at ° C., FIG. 1, FIG. 3, the resistance of each of the bump bonding portions after the 600 cycles of the semiconductor device structure shown in Figure 4 Although about was 1Ω or less, before it passed 300 cycles in the semiconductor device of the structure shown in FIG. 6, the portion not 0.00 cracked connected to the resin 5 has occurred.

また、70℃,90%RHの高温高湿放置試験を行ったところ、第1図,第3図,第4図に示される構成の半導体装置の1000H後におけるそれぞれのバンプ接合部分の抵抗は、約1Ω以下で安定であったが、第6図に示される構成の半導体装置では、600Hでバンプ接合部分に不良が生じた。 Further, 70 ° C., was subjected to high-temperature high-humidity storage test of RH 90%, Figure 1, Figure 3, the resistance of each of the bump bonding portions after 1000H of the semiconductor device of the configuration shown in Fig. 4, was stable up to about 1Ω, but the semiconductor device of the structure shown in FIG. 6, failure occurs in the bump bonding part 600H.

なお、本発明は上述した実施例に限定されるものではない。 The present invention is not limited to the embodiments described above. 実施例では溶剤を含まない第1の樹脂組成物としてエポキシ系の樹脂を用いたが、アクリル系樹脂,シリコーン系樹脂等を用いても同様の効果が得られる。 It was used an epoxy resin as a first resin composition without solvent in the examples, an acrylic resin, the same effect can be a silicone-based resin is obtained. 要は、半導体素子11と絶縁基板13との間の隙間に含浸可能で、半導体素子11と絶縁基板13との間の隙間に充填されてもほぼ一様に硬化可能な性質を有する溶剤を含まない樹脂組成物であればよい。 In short, it can be impregnated into the gap between the semiconductor element 11 and the insulating substrate 13, contain a solvent having a substantially uniform curable properties be filled in the gap between the semiconductor element 11 and the insulating substrate 13 it may be a free resin composition. また、上記実施例では、溶剤を含む第2の樹脂組成物としてエポキシ系の樹脂であるフェノール硬化エポキシ樹脂16を用いたが、アクリル系樹脂,シリコーン系樹脂,、ブタジエン系樹脂等を用いても同様の効果が得られる。 Further, in the above embodiment, with phenol cured epoxy resin 16 is a resin of epoxy as a second resin composition containing a solvent, an acrylic resin, even with silicone resin ,, butadiene resin the same effect can be obtained. 要は、傾斜材料となり充填剤が沈降して耐湿性、耐熱衝撃性を向上させるものであればよい。 In short, humidity filler becomes gradient material is settled, as long as it can improve the heat shock resistance.

また、上記実施例では半導体素子11と絶縁基板13とをバンプ12を介して接合させた後に、エポキシ樹脂15でバンプ12を封止したが、予め絶縁基板13上にエポキシ樹脂 Also, after bonding the semiconductor element 11 and the insulating substrate 13 through the bumps 12 in the above embodiment, sealing the bumps 12 with an epoxy resin 15, an epoxy resin on the previously insulated substrate 13
15をポッティングして、半導体素子11と絶縁基板13とを接合してもよい。 15 and potted, may be bonded to the semiconductor element 11 and the insulating substrate 13. この場合、配線14とバンプとは絶縁性接着剤を介して接続されているので、半田バンプ12のように接続用材料で構成されたバンプを用いる必要がなくなるので、金,銅等のバンプ材料を用いることが可能となる。 In this case, since it is connected through an insulating adhesive between the wiring 14 and the bump, because there is no need to use a bump made of a connecting material such as solder bumps 12, gold, bump material such as copper it is possible to use. また、第1の樹脂組成物としてエポキシ系樹脂以外に、前述したアクリル系樹脂,シリコン系樹脂等の樹脂を用いても同様の効果が得られるのは勿論のことである。 Besides the epoxy resin as a first resin composition, the above-mentioned acrylic resin, similar effects by using a resin such as silicone resin obtained it is of course possible.

また、無アルカリガラス以外の絶縁基板13の材料として、セラミック,ガラスエポキシ,金属コア,ポリイミドまたは紙フェノール等を用いてもよい。 Further, as a material of the insulating substrate 13 other than the alkali-free glass, ceramic, glass epoxy, metal core, may be used polyimide, or paper phenol. また、ITO,クロム,金の積層膜以外の配線14の材料としては、ニッケル,銅,チタン,ITO,クロム,アルミニウム,モリブデン,タンタル,タングステン,金,銀,パラジュウムあるいはこれら配線材料を複数組合わせたものを用いてもよい。 Further, ITO, chromium, as the material of the wiring 14 except the laminated film of gold, nickel, copper, titanium, ITO, chromium, aluminum, molybdenum, tantalum, tungsten, gold, silver, palladium or multiple combinations of these wiring materials may also be used was.

なお、上記実施例では銅バンプをコアとし、電気メッキを用いて半田バンプ12を形成したが、コアの金属は必ずしも必要ではない。 In the above embodiment the copper bumps and the core has formed the solder bumps 12 using an electroplating, metal core is not always necessary. また、半田バンプ12を形成する際、電気メッキを用いず、真空蒸着法を用いて半田バンプ12を形成したり、溶融半田中に半導体素子11を浸漬させて半田バンプ12を形成してもよい。 Further, when forming the solder bumps 12, without using an electroplating, or forming solder bumps 12 by a vacuum evaporation method, may be formed of solder bumps 12 by immersing the semiconductor element 11 in the solder melting . さらにまた、使用する製品や製造工程に応じて錫と鉛との割合を変えたり、他の金属材料を用いて半田以外のバンプ材料を用いてもよい。 Furthermore, changing the ratio of tin and lead in accordance with the products and processes used, it may be used bump materials other than solder using other metal materials. 例えば、液晶表示装置等のように温度条件が制約される製品には、インジウム,ビスマス,カドニウム等の低融点の金属を用いてバンプを形成してもよい。 For example, the product temperature is constrained to such a liquid crystal display device, indium, bismuth, may be formed a bump with a low melting point metals such as cadmium.
また、バンプの耐腐食性を図りたい場合には、銀,アンチモン等のバンプ材料を用いるとよい。 When it is desired aim the corrosion resistance of bumps, to use silver or bump material and antimony. その他、本発明の要旨を逸脱しない範囲で、種々変形して実施できる。 Other, without departing from the scope of the present invention can be variously modified.

[発明の効果] 本発明によれば、樹脂に水分が浸入するのを防止でき耐湿性が改善される。 According to [Effects of the Invention] The present invention, moisture resistance can prevent moisture in the resin from penetrating is improved. また、絶縁基板と樹脂との接合面での熱膨脹率の差が小さくなるので耐熱衝撃性も改善される。 Furthermore, thermal shock resistance is also improved because the difference in coefficient of thermal expansion at the bonding surface between the insulating substrate and the resin is reduced. その結果、耐環境性が向上し、信頼性の高い半導体装置を得ることができる。 As a result, environmental resistance is improved, it is possible to obtain a highly reliable semiconductor device.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

第1図は本発明の第1の実施例に係る半導体装置の断面図、第2図は同半導体装置の平面図、第3図は本発明の第2の実施例に係る半導体装置の断面図、第4図は本発明の第3の実施例に係る半導体装置の断面図、第5,第6 Sectional view of a semiconductor device according to the first embodiment of Figure 1 the present invention, FIG. 2 is a plan view of the semiconductor device, cross-sectional view of FIG. 3 is a semiconductor device according to a second embodiment of the present invention , Figure 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention, the fifth, sixth
図は従来の半導体装置の断面図である。 Figure is a cross-sectional view of a conventional semiconductor device. 11……半導体素子、12……バンプ、13……絶縁基板、14 11 ...... semiconductor device, 12 ...... bump, 13 ...... insulating substrate, 14
……配線、15,15a……エポキシ樹脂、16,16a……フェノール硬化エポキシ樹脂。 ...... wiring, 15,15a ...... epoxy resin, 16,16a ...... phenolic cured epoxy resin.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 坂本 次雄 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝総合研究所内 (72)発明者 東 道也 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝総合研究所内 (56)参考文献 特開 平2−56941(JP,A) 特開 平1−209750(JP,A) 特開 昭60−63951(JP,A) 特開 平2−56941(JP,A) (58)調査した分野(Int.Cl. 6 ,DB名) H01L 21/56 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Tsuguo Sakamoto Kawasaki-shi, Kanagawa-ku, Saiwai Komukaitoshiba-cho, address, Ltd. Toshiba the laboratory (72) inventor Michiya Azuma Kawasaki-shi, Kanagawa-ku, seafood Komukaitoshiba town address 1 Toshiba Corporation General within the Institute (56) reference Patent flat 2-56941 (JP, a) JP flat 1-209750 (JP, a) JP Akira 60-63951 (JP, a) JP flat 2-56941 (JP, a) (58 ) investigated the field (Int.Cl. 6, DB name) H01L 21/56

Claims (2)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】絶縁基板と、この絶縁基板に形成された配線にバンプを介してフェイスダウンに接続された半導体素子と、前記バンプを封止する樹脂組成物とを有する半導体装置の製造方法において、溶剤を含まない第1の樹脂組成物で前記バンプを封止する工程と、前記絶縁基板に結合した状態を保ちつつ前記第1の樹脂組成物を溶剤を含む第2の樹脂組成物で覆う工程とを有することを特徴とする半導体装置の製造方法。 And 1. A insulating substrate, a semiconductor element connected to the face-down through the bumps formed wirings in the insulating substrate, in the manufacturing method of a semiconductor device having a resin composition for sealing the bumps covers a step of sealing the bumps in the first resin composition containing no solvent, the while maintaining a state bound to the insulating substrate of the first resin composition in the second resin composition containing a solvent the method of manufacturing a semiconductor device characterized by a step.
  2. 【請求項2】前記第2の樹脂組成物で前記半導体素子の裏面を覆わないことを特徴とする請求項1に記載の半導体装置の製造方法。 2. A method of manufacturing a semiconductor device according to claim 1, characterized in that in the second resin composition does not cover the back surface of the semiconductor element.
JP20454190A 1990-08-01 1990-08-01 A method of manufacturing a semiconductor device Expired - Fee Related JP2892117B2 (en)

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US6046076A (en) * 1994-12-29 2000-04-04 Tessera, Inc. Vacuum dispense method for dispensing an encapsulant and machine therefor
US5915170A (en) * 1994-09-20 1999-06-22 Tessera, Inc. Multiple part compliant interface for packaging of a semiconductor chip and method therefor
US6870272B2 (en) 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US5659952A (en) * 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US6169328B1 (en) 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
US6284563B1 (en) 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US6686015B2 (en) 1996-12-13 2004-02-03 Tessera, Inc. Transferable resilient element for packaging of a semiconductor chip and method therefor
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