JP2890971B2 - Semiconductor logic integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic integrated circuit, and more particularly to a function test of an internal macro cell.

[0002]

2. Description of the Related Art As shown in FIG. 3, a function test of a macro cell in a conventional logic integrated circuit is performed by a selector 5 and a macro cell.
The test data input terminal TIN and the test data output terminal OUT of the circuit under test 14 having the cell 6 are connected to the logic integrated circuit 1.
The test signal section and the determination section of the external IC tester b are connected via n test input terminals T1 to Tn and one test output terminal TO, respectively.

That is, n test input parallel signals SIP of m bits are supplied to the input terminal Ti of the logic integrated circuit 1b.
(I = 1 to n) are supplied to the input terminal TIN of the selector 5 of the circuit under test 14 via the test node NT.
The bit test output signal STO is supplied from the output terminal OUT of the macro cell 6 to the determination unit of the IC tester connected to the output terminal TO of the logic integrated circuit 1b via the test output signal line 11, and Functional tests have been performed.

Here, the selector 5 selects the normal input signal SRI in the normal mode and the test input parallel signal SIP in the test mode according to the select control signal S7 supplied to the control terminal S.

[0005]

In this conventional semiconductor logic integrated circuit, the number of signal lines connected to the external terminals requires the number of input / output terminals of the circuit under test. There are problems such as limiting the number of terminals to be used or increasing the total number of terminals.

[0006]

A semiconductor logic integrated circuit according to the present invention holds a selector for inputting a test input sequence signal from an external IC tester and branching / distributing the input signal into n signals and the n select signals. A test / input signal sequence / parallel conversion unit having a selector / latch unit having a latch, and n two-port RAMs each of which temporarily stores n signals of the latch and outputs a test input parallel signal; A selector for inputting a select control signal to select the test input parallel signal and the normal input signal according to a mode, inputting an output signal selected by the selector, performing logic processing, and outputting to the outside via an output terminal And a circuit under test having a macro cell to be tested that outputs a signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention.
The logic integrated circuit 1 includes a selector 2 for inputting an m-bit test input sequence signal SIS, a selector
A latch unit 13 and n 2-port Rs each receiving the latch output and outputting a test input parallel signal SIP
AM4 and control signals SS and S for controlling their operations.
A test input signal sequence / parallel converter 7 having a control circuit 12 for outputting L and SCV is inserted between a conventional test input signal terminal T1 and a test input node NT.

Next, the operation of the block will be described. External I
A test input sequence signal SIS consisting of n consecutive m-bit signals input from the C tester via the test input terminal T1 is distributed to i (i = 1 to n) by the selector 2 of the selector / latch unit 13. , To the next latch 3 ,
The data is latched in the order of 1 to n for each unit of m bits .

When the input to all the latches 3 is completed, the contents are written to n 2-port RAMs 4 each having an m-bit input / output configuration . The test input parallel signal SIP written in each 2-port RAM 4 and converted from a sequence to a parallel can be read out at any time and is input to the macro cell 6. 2 port RAM4
Spreads the test input parallel signal SIP over multiple signals.
After accumulating once, macros are sequentially created at that access speed.
・ High-speed function test because it can be supplied to cell 6
Test at operating speed of macro cell 6 in actual use
Is possible. Also, in the 2-port RAM 4, the macro
Reading from the cell 6 and writing from the latch 3 are performed in parallel.
Test execution time.
You. The selector 5 sorts the macro cell 6 between the normal mode and the function test mode.
Thus, the normal input signal line 8 and the test input signal line 9 at the time of the test are selected.

The output signal of the macro cell 6 depends on the normal or test mode. The normal output signal SRO is sent to the normal output signal line 10 and the test output signal STO is sent to the outside via the test output signal line 11. Is supplied to the test signal output terminal T2 connected to the terminal. The operation of each of these blocks is controlled by control signals SS, SL, SCV, SM from the control circuit unit 12. The same applies to the case where a plurality of circuits under test are tested.

FIG. 2 is a block diagram of a second embodiment of the present invention. In the logic integrated circuit 1a of this embodiment, a two-port RAM 4D for storing an expected output value is added to the blocks of the first embodiment, and a selector
At the same time as distributing the input signal of the circuit under test 14 by the latch section 13a, the expected output value is written to the two-port RAM 4D. Circuit under test 1 via test input node NTU
The test output signal STO obtained from the test input parallel signal SIP given to S.4 is compared with the expected value SE written in the two-port RAM 4D using the comparison circuit 15, and the comparison result output signal SCO is compared. The signal is supplied to the test signal output terminal T2 via the output signal line 20.

In this embodiment, since the expected output value is also stored in the RAM 4D, an external test determination unit is not required by comparing the output value with the test output result. The number of terminals for both input and output can be reduced.

[0013]

As described above, according to the present invention, the number of input terminals required for the function test of the macro cell which is the circuit under test can be reduced, and the effect becomes larger as the number of macro cells increases. growing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of an example of a conventional semiconductor logic integrated circuit.

[Explanation of symbols]

1, 1a Integrated circuit device 2 Selector circuit 3 Latch circuit 4, 4D, 4U 2-port RAM 5 Selector 6 Macro cell 7, 7a Test input signal sequence / parallel converter S7 Select control signal 8 Normal input signal line 9 Test input signal Line 10 Normal output signal line 11 Test output signal line 12, 12a Control circuit 13, 13a Selector / latch circuit 14 Tested circuit 15 Comparison circuit 16 Comparison output signal line NT, NTD, NTU Test input node SCO Comparison output signal SIS, SISa Test input sequence signal SL, SLa Latch control signal SS, SSa Select control signal SRO Normal output signal STO Test output signal T1 Test signal input terminal T2 Test signal output terminal

Claims (2)

(57) [Claims] A selector / latch unit having a selector for inputting a test input sequence signal from an external IC tester and branching / distributing the signal into n pieces, and a latch for holding the n number of select signals, respectively; a test input signal sequence / parallel conversion unit having n 2-port RAMs for temporarily storing n signals and outputting test input parallel signals, and selectively controlling the test input parallel signals and the normal input signal A selector for inputting a signal and selecting it in accordance with a mode, and a macro cell to be tested for inputting an output signal selected by the selector, performing logic processing and outputting an output signal to the outside via an output terminal A semiconductor logic integrated circuit including a circuit under test. 2. The test input signal sequence / parallel conversion section has n 2-port RAMs for temporarily storing an expected value of a test output signal of a circuit under test, and a test output terminal of the circuit under test and a test output signal. 2. The semiconductor logic integrated circuit according to claim 1, wherein a comparison circuit for inputting the expected value and the test output signal and outputting a comparison output signal is inserted between the terminal and a terminal.