JP2888405B2 - Cyclic data control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed processing system having a function of controlling transmission and reception of control data by a plurality of stations connected to a loop transmission line and an external control device, and more particularly to a loop transmission line. The present invention relates to a method of controlling cyclic data by detecting a change in cyclic data transmitting the data.

[0002]

2. Description of the Related Art FIG. 15 is a block diagram showing a configuration example of a conventional control dataway station for implementing a protocol. In FIG. 15, 19 is a station. A media access unit 13 is connected to a line connection unit 12 connected to the line 11. The buffer memory 14 for transmitting and receiving data to and from the media access unit 13 has a transmission buffer memory 14a and a reception buffer memory 14b. Station 19 also has D
An MA transfer control unit 15, a cyclic memory 16, and an event transmission control unit 17 are provided, and an external control device 8 is connected.

FIG. 17 shows a configuration diagram of a frame. FIG. 17A shows the structure of the token frame 20, where (10-SD) is the start delimiter and (10-FC)
Is a frame control, and (10-ED) is an end delimiter.

FIG. 17B is a diagram showing the structure of a data frame 21, where (11-SD) shows a start delimiter,
(11-FC) is the frame control, (11-DA) is the destination address, (11-SA) is the source address, and (11-FC)
(INFO) is an information area, (11-FCS) is a frame check sequence, (11-ED) is an end delimiter,
(11-FS) is a frame status. further,
For data frames that transmit cyclic data,
(11-INFO) is further divided into transmission control information 22 and cyclic data 23, and the transmission control information 22 includes address offset information (12-OFFSET) and transmission data amount (12-LENGTH).

FIG. 16 is an overall schematic diagram of a control data way (distributed processing system) configured by using the above stations. In FIG. 16, a plurality of stations 19a, 19b, and 19c are connected to the loop transmission path 25, and each of the stations 19a, 19b, and 19c is connected to the media access unit 1 as shown in FIG.
3, a cyclic memory 16 and an event transmission control unit 17 are provided, and external control devices 18a, 18b, 18c
Is connected.

Next, the operation of the conventional example will be described.
When the station 19 connected to the loop transmission path 25 acquires the token frame 20 having the configuration shown in FIG. 17A, the station 19 transmits the data frame 21 having the configuration shown in FIG. Acquire rights. In this data frame 21, the data in the area of the cyclic memory set to be transmitted by the own station is carried and transmitted. That is, the offset address from the beginning of the cyclic memory of the cyclic data block to be transmitted to the address offset information (12-OFFSET) of the transmission control information 22 is determined by the transmission data amount (12-LE
NGTH) carries the number of words of the cyclic data block to be transmitted, and the cyclic data 23 carries actual data on the cyclic memory according to the transmission area.

Further, the destination address (11-DA) of the data frame 21 is transmitted as a broadcast address so that all stations can receive it (see FIG. 18). As the source address, an individual address of the transmitting station is set. This data frame 21
The station that has received the transmission control information 22
From the address separated from the top of the cyclic memory by the offset address indicated by the address offset information (12-OFFSET) of (12-LEN).
GTH) expands the received cyclic data 23 by the data length shown in FIG. 16 (see FIG. 16).

[0008] Since the token is passed to all stations according to the connection order on the transmission path, by transmitting its own cyclic data frame when acquiring the token,
The contents of the cyclic memories of all the stations are kept the same with a certain delay time. Therefore, when the external control devices 18a, 18b and 18c write data in the transmission area of their own connected station in the cyclic memory 16, the cyclic memories of all the stations 19a, 19b and 19c connected to the loop after a certain time delay. The written contents are reflected in the same area of No. 16. By reading this by the external control devices 18a, 18b, 18c, data transmission between the external control devices via the cyclic memory 16 can be performed.

In such a cyclic data transmission, in order for a certain external control device to detect a change in cyclic data at an arbitrary address, the external control device periodically reads the cyclic data whose change is to be detected, and reads the previous value. The polling method by software, such as storing the latest value in the previous value, was used.

[0010]

In the conventional distributed processing system, the method of transmitting cyclic data and the method of detecting change of cyclic data are performed by the above-mentioned configuration. However, there has been a problem that the change of the cyclic data cannot be detected quickly, and the load on the external control device is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the detection of a change in cyclic data is performed not by an external control device but by a transfer control unit of each station. Accordingly, an object of the present invention is to provide a cyclic data control method capable of reducing the load on an external control device and promptly detecting a change in cyclic data.

[0012]

According to the first aspect of the present invention, when the latest cyclic data is received, the change detection control circuit 9 temporarily stores the data in the latest value register 5a and stores the data in the latest value cyclic memory 4a. In the same cycle as writing the data, the previous value from the previous value cyclic memory 4b is tested by the output of the OR circuit 6b, and if the output is insignificant, the reception of the latest cyclic data is continued, and the output is If significant, an interrupt signal is generated externally by the interrupt signal generation circuit 7 and the latest cyclic data stored in the latest value register 5a is written to the same address of the previous value cyclic memory 4b, and then the latest cyclic data is written. Continues receiving data, but keeps the latest cyclic memo until the change detection lock is released from outside. It is characterized in that for performing control to only write the latest cyclic data 4a.

According to a second aspect of the present invention, there is provided the configuration of the first aspect, further comprising an address of the cyclic memory at which the change of the cyclic data is detected and the exclusive OR circuit 6a.
Registers 5b and 5d for storing the outputs of
An external interface circuit 8 for reading the contents of the registers 5b and 5b from outside is provided.

According to the third aspect of the present invention, the change detection control circuit 9 stores the latest cyclic data in the latest value register 5a when receiving the latest cyclic data, and writes the data into the latest value cyclic memory 4a. In the cycle, the previous value is read from the previous value cyclic memory 4b, the mask data is read from the change detection mask memory 4c, and the output of the OR circuit 6b is tested. If the output is insignificant, the reception of the latest cyclic data is continued. If the output is significant, an interrupt signal is generated externally by the interrupt signal generation circuit 7 and the latest cyclic data stored in the latest value register 5a is written to the same address of the previous value cyclic memory 4b. After that, reception of the latest cyclic data is continued, but the change detection lock is externally released. Until that is characterized in carrying out the control to only write the latest cyclic data current value cyclically memory 4a.

According to a fourth aspect of the present invention, there is provided the configuration of the third aspect, wherein the registers 5b and 5d for storing the address of the cyclic memory in which the change of the cyclic data is detected and the output of the AND circuit 6c are respectively provided. And an external interface circuit 8 for reading from outside.

In the invention of claim 5, the change detection control circuit 9 stores the data in the latest value register 5a once when the latest cyclic data is received, and writes the data in the latest value cyclic memory 4a. In the cycle, the previous value is read from the previous value cyclic memory 4b, the ON change detection mask data is read from the ON change detection mask memory 4d, and the OFF change detection mask data is read from the OFF change detection mask memory 4e. If the output is insignificant, the reception of the latest cyclic data is continued. If the output is significant, an interrupt signal is generated externally by the interrupt signal generation circuit 7 and stored in the latest value register 5a. The latest cyclic data stored is written to the same address of the previous value cyclic memory 4b. Receiving the latest cyclic data thereafter, but performing control such that only the latest cyclic data is written to the latest value cyclic memory 4a until the change detection lock is released from the outside. It is.

According to a sixth aspect of the present invention, there is provided the configuration of the fifth aspect, further comprising an address of the cyclic memory in which the cyclic data change is detected and an on-change AND circuit 6e.
And an external interface circuit 8 for reading the contents of the register from the outside, provided respectively with registers 5b and 5g for storing the output of the register 5h and a register 5h for storing the output of the off-change AND circuit 6g. It is.

[0018]

According to the first aspect of the present invention, when the latest cyclic data is received, the data is temporarily stored in the latest value register 5a. The previous value from the previous value cyclic memory 4b is tested by the output of the OR circuit 6b in the same cycle as writing data to the latest value cyclic memory 4a. If the output is insignificant, reception of the latest cyclic data is continued, and if the output is significant, the interrupt signal generation circuit 7 generates an interrupt signal to the outside. Further, the latest cyclic data stored in the latest value register 5a is written to the same address of the previous value cyclic memory 4b, and thereafter, the reception of the latest cyclic data continues, but the change detection lock is externally released. Until the latest cyclic data is written to the latest cyclic memory 4a.

According to the second aspect of the present invention, the register 5b
Stores the address of the cyclic memory at which the change of the cyclic data is detected, and the register 5d stores the output of the exclusive OR circuit 6a. The external interface circuit 8 reads the contents of the registers 5b and 5d from outside.

According to the third aspect of the present invention, when the latest cyclic data is received, the data is temporarily stored in the latest value register 5a, and in the same cycle as writing the data to the latest value cyclic memory 4a, the previous value is stored. The previous value is read from the cyclic memory 4b, the mask data is read from the change detection mask memory 4c, and the output of the OR circuit 6b is tested. If the output is insignificant, reception of the latest cyclic data is continued, and if the output is significant, the interrupt signal generation circuit 7 generates an interrupt signal to the outside. The latest cyclic data stored in the latest value register 5a is written to the same address of the previous value cyclic memory 4b, and thereafter,
The reception of the latest cyclic data continues, but the latest cyclic data is written to the latest value cyclic memory 4a until the change detection lock is released from outside.

According to the fourth aspect of the present invention, the register 5b
Stores the address of the cyclic memory at which the change of the cyclic data is detected, and the register 5d stores the output of the AND circuit 6c. The external interface circuit 8 reads the contents of the registers 5b and 5d from outside.

In the present invention, when the latest cyclic data is received, this data is stored in the latest value register 5a, and in the same cycle as writing the data to the latest value cyclic memory 4a, the previous value data is stored. The previous value is read from the click memory 4b, the ON change detection mask data is read from the ON change detection mask memory 4d, and the OFF change detection mask data is read from the OFF change detection mask memory 4e. Then, the output of the OR circuit 6h is tested. If the output is insignificant, reception of the latest cyclic data is continued. If the output is significant, an interrupt signal is generated by the interrupt signal generating circuit 7 to the outside. You. Also, the latest cyclic data stored in the latest value register 5a is stored in the previous value cyclic memory 4.
b, the reception of the latest cyclic data continues, but the latest cyclic data is written to the latest value cyclic memory 4a until the change detection lock is released from the outside.

According to the invention of claim 6, the register 5b
Stores the address of the cyclic memory at which the change of the cyclic data is detected, and the register 5g stores the output of the on-change AND circuit 6e. The external interface circuit 8 reads the contents of the registers 5b and 5g from outside.

[0024]

Embodiment 1 (Claims 1 and 2). FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. FIG. 1 shows a first embodiment in which the contents of a conventional DMA transfer control unit 15 are improved.
1 shows a configuration of a DMA transfer control unit. In FIG. 1, a latest value cyclic memory 4a is connected to a cyclic data receiving circuit 1 via an address bus 2 and a data bus 3a. Further, the latest value register 5a is connected to the data bus 3a, and the address register 5b is connected to the address bus 2. In the previous value cyclic memory 4b, the address bus 2 is connected to the address input, and the data bus 3b is connected to the data input / output. The latest value register 5a and the previous value register 5c are connected to the data bus 3b. Exclusive OR circuit 6a
The A input is connected to the output of the latest value register 5a, and the B input is connected to the output of the previous value register 5c. The output of the exclusive OR circuit 6a is connected to the change bit register 5d and the OR circuit 6b, and the output of the OR circuit 6b is connected to the interrupt signal generation circuit 7. Outputs of the address register 5b and the change bit register 5d are connected to the external interface circuit 8. Then, there is a change detection control circuit 9 for controlling each of the above components.

FIG. 2 shows a typical flow of processing in the first embodiment in chronological order. FIGS. 3 and 4 show flowcharts of this processing. The operation of the first embodiment will be described with reference to FIGS. When the latest cyclic data is received, the change detection control circuit 9 temporarily stores the data in the latest value register 5a (step 31) and writes the data to the latest value cyclic memory 4a (step 32) in the same cycle as The previous value is read from the previous value cyclic memory 4b (step 33). At this time, the latest value cyclic memory 4a and the previous value cyclic memory 4b
Are connected to the same address bus 2 and therefore access data having the same address offset. The previous value data is set in the previous value register 5c via the data bus 3b. Then, the exclusive OR circuit 6a performs an exclusive OR operation for each bit of the output of the latest value register 5a and the output of the previous value register 5c (step 34). If there is a difference between the previous value and the latest value, the changed bit becomes significant. All the outputs for each bit of the exclusive OR circuit 6a are subjected to a logical OR operation by the logical OR circuit 6b. if,
If any bits are significant (step 35),
That is, if there is a difference between the previous value and the latest value in any of the bits, the output of the OR circuit 6b becomes significant.

If the output of the OR circuit 6b is insignificant, the change detection control circuit 9 continues to receive the next cyclic data, and the change detection processing is canceled here. If the output is significant, the interrupt signal generation circuit 7 generates an interrupt signal to the outside (step 3).
7). At this time, the change detection control circuit 9 writes the latest cyclic data stored in the latest value register 5a to the address stored in the address register 5b of the previous value cyclic memory 4b (step 36), and thereafter updates the latest cyclic data. Continue receiving data.

From outside, the address register 5b and the change bit register 5d are passed through the external interface circuit 8.
Can be read at any time.

However, after detecting a change in cyclic data,
If the cyclic data change detection process is performed continuously,
Before reading the values of the address register 5b and the change bit register 5d from outside through the external interface circuit 8,
Since new cyclic data change detection may occur and be overwritten with new data, in order to avoid this, the change detection lock (step 38) is released from the outside via the external interface circuit 8. (Step 39), only the latest cyclic data is written in the latest value cyclic memory (steps 40 and 41), and the above change detection processing is not performed.

Embodiment 2 (corresponding to claims 3 and 4). 5 and 6 are diagrams showing a second embodiment of the present invention. 5 and 6
2 shows a configuration of a DMA transfer control unit according to a second embodiment in which the contents of the DMA transfer control unit 15 of the conventional example are improved.
5 and 6, the latest value cyclic memory 4a is connected to the cyclic data receiving circuit 1 via the address bus 2 and the data bus 3a. Further, the latest value register 5a is provided on the data bus 3a.
Is connected to an address register 5b. In the previous value cyclic memory 4b, the address bus 2 is connected to the address input, and the data bus 3b is connected to the data input / output. In the change detection mask memory 4c, the address bus 3 is connected to the address input, and the data bus 3c is connected to the data input / output. The latest value register 5a and the previous value register 5c are connected to the data bus 3b. A change detection mask register 5d is connected to the data bus 3b. The A input of the exclusive OR circuit 6a includes:
The output of the latest value register 5a is connected to the output of the last value register 5b, and the B input is connected to the output of the previous value register 5b. The output of the exclusive OR circuit 6a is connected to the A input of the AND circuit 6c, and the output of the change detection mask register 5d is connected to the B input. The output of the AND circuit 6c is connected to the change bit register 5d and the OR circuit 6b, and the output of the OR circuit 6b is connected to the interrupt signal generation circuit 7. Outputs of the address register 5b and the change bit register 5d are connected to the external interface circuit 8. Then, there is a change detection control circuit 9 for controlling each of the above components.

Next, the operation of the second embodiment will be described with reference to FIGS. FIG. 7 shows a typical processing flow of the second embodiment in chronological order. 8 and 9 show flowcharts of the processing. 5 and 6, the change detection control circuit 9 temporarily stores the latest cyclic data in the latest value register 5a when receiving the latest cyclic data (step 6).
1) In the same cycle as writing data to the latest value cyclic memory 4a (step 62), the previous value is read from the previous value cyclic memory 4b (step 63), and the change detection mask data is read from the change detection mask memory 4c. (Step 64). At this time, since the latest value cyclic memory 4a, previous value cyclic memory 4b, and change detection mask memory 4c are connected to the same address bus 2, data having the same address offset is accessed. The previous value data is set in the previous value register 5c via the data bus 3b. The change detection mask data is set in the change detection mask register 5d via the data bus 3c.

Thereafter, the exclusive OR circuit 6a performs an exclusive OR operation for each bit of the output of the latest value register 5a and the output of the previous value register 5c (step 65).
If there is a difference between the previous value and the latest value, the changed bit becomes significant. The output of the exclusive OR circuit 6a is ANDed with the output of the change detection mask register 5d for each bit by the AND circuit 6c. Even if there is a difference between the previous value and the latest value, if the corresponding bit of the change detection mask data is not significant (step 66), the result of the logical product is not significant. The logical sum circuit 6b performs a logical sum operation on all the outputs for each bit of the logical product circuit 6c. If any bit is significant, that is, if there is a difference between the previous value and the latest value in any bit and the change detection is not masked, the output of the OR circuit 6b becomes significant.

If the output of the OR circuit 6b is insignificant, the change detection control circuit 9 continues to receive the next cyclic data, and the change detection processing is canceled here. If the output is significant, the interrupt signal generation circuit 7 generates an interrupt signal to the outside (step 6).
8). At this time, the change detection control circuit 9 writes the latest cyclic data stored in the latest value register 5a to the address stored in the address register 5b of the previous value cyclic memory 4b (step 67), and thereafter updates the latest cyclic data. Continue receiving data. From outside, the values of the address register 5b and the change bit register 5d can be read at any time through the external interface circuit 8.

However, after detecting a change in cyclic data,
If the cyclic data change detection process is performed continuously,
Before reading the values of the address register 5b and the change bit register 5d from outside through the external interface circuit 8,
Since new cyclic data change detection may occur and be overwritten with new data, in order to avoid this, until the change detection lock (step 69) is released from the outside via the external interface circuit 8. (Step 70), only the latest cyclic data is written into the latest value cyclic memory (steps 71 and 72), and the above-described change detection processing is not performed.

Embodiment 3 (corresponding to claims 5 and 6). FIG.
FIG. 11 is a diagram showing a third embodiment of the present invention. FIG.
FIG. 11 shows a configuration of a DMA transfer control unit according to a third embodiment in which the contents of the DMA transfer control unit 15 of the conventional example are improved. 10 and 11, a cyclic data receiving circuit 1 is connected to an address bus 2 and a data bus 3a via a data bus 3a.
The latest value cyclic memory 4a is connected. Further, the latest value register 5a is connected to the data bus 3a, and the address register 5b is connected to the address bus 2. In the previous value cyclic memory 4b, the address bus 2 is connected to the address input, and the data bus 3b is connected to the data input / output. ON change detection mask memory 4
As for d, the address bus 2 is connected to the address input, and the data bus 3d is connected to the data input / output. In the OFF change detection mask memory 4e, the address bus 2 is connected to the address input, and the data bus 3e is connected to the data input / output. The latest value register 5a is connected to the data bus 3b.
And the previous value register 5c. Data bus 3
The ON change detection mask register 5e is connected to d.

The off change detection mask register 5f is connected to the data bus 3e. The output of the previous value register 5b is connected to the previous value inversion circuit 6d. The A input of the ON change AND circuit 6e receives the output of the previous value inversion circuit 6d.
The output of the latest value register 5a is connected to the B input. The latest value register 5a outputs the latest value inverting circuit 6f.
The output of the latest value inversion circuit 6f is connected to the A input of the OFF change AND circuit 6g, and the output of the previous value register 5b is connected to the B input. ON change AND circuit 6e
Is connected to an on-change bit register 5g.
An OFF change bit register 5h is connected to the output of the OFF change AND circuit 6g. An OR circuit 6h for ORing all the bits of the output of the ON change bit register 5g and the output of the OFF change bit register 5h is connected, and an interrupt signal generation circuit 7 is connected to the output of the OR circuit 6h. I have. Outputs of the address register 5b, the ON change bit register 5g, and the OFF change bit register 5h are connected to the external interface circuit 8. Then, there is a change detection control circuit 9 for controlling each of the above components.

Next, a third embodiment will be described with reference to FIGS.
Will be described. FIG. 12 shows a typical processing flow of the third embodiment in chronological order. 13 and 14 show flowcharts of the processing. 10 and 11, when the latest cyclic data is received, the change detection control circuit 9 temporarily stores the data in the latest value register 5a (step 91), and writes the data in the latest value cyclic memory 4a (step 92). ) In the same cycle,
The previous value is read from the previous value cyclic memory 4b (step 93), the ON change detection mask data is read from the ON change detection mask memory 4d (step 94), and the OFF change detection mask data is read from the OFF change detection mask memory 4e (step 95). ). At this time, since the latest value cyclic memory 4a, previous value cyclic memory 4b, ON change detection mask memory 4d, and OFF change detection mask memory 4e are connected to the same address bus 2, data having the same address offset is accessed. I do. Data bus 3
The previous value data is set in the previous value register 5c via b. The ON change detection mask data is set in the ON change detection mask register 5e via the data bus 3d, and the OFF change detection mask data is set in the OFF change detection mask register 5f via the data bus 3e.

Thereafter, the output of the previous value register 5c is subjected to an inversion operation for each bit by the previous value inversion circuit 6d, and the output of the previous value inversion circuit 6d and the output of the latest value register 5a are output by the on-change AND circuit 6e. An AND operation is performed for each bit (step 96). If the previous value is insignificant and the latest value is significant, the changed bit becomes significant. The output of the on-change AND circuit 6e is latched by the on-change bit register 5g. Simultaneously with the on-change detection operation, the output of the latest value register 5a is inverted for each bit by a latest value inversion circuit 6f.
And the output of the previous value register 5c are subjected to an AND operation for each bit in the OFF change AND circuit 6g (step 97). If the latest value is insignificant and the previous value is significant,
Bits that have changed become significant. The output of the off change AND circuit 6g is latched by the off change bit register 5h.

The logical sum circuit 6h performs a logical sum operation on all of the outputs of the on-change logical product circuit 6e and the off-change bit register 5h for each bit (step 98). If any of the bits is significant (step 99), that is, if there is a difference between the previous value and the latest value in any of the bits and the on-change detection mask or the off-change detection mask is not set, the logical sum is calculated. The output of circuit 6h becomes significant. If the output of the OR circuit 6h is insignificant, the change detection control circuit 9 continues to receive the next cyclic data, and the change detection processing is canceled here. If the output is significant, the interrupt signal generation circuit 7 generates an interrupt signal to the outside (step 101). At this time, the change detection control circuit 9 stores the latest cyclic data stored in the latest value register 5a in the previous value cyclic memory 4b.
(Step 100), and then the reception of the latest cyclic data is continued. From outside, the values of the address register 5b, the on-change bit register 5g, and the off-change bit register 5h can be read at any time through the external interface circuit 8.

However, after detecting a change in cyclic data,
If the cyclic data change detection process is performed continuously,
Before reading the values of the address register 5b, the on-change bit register 5g, and the off-change bit register 5f from outside through the external interface circuit 8, a new cyclic data change detection may occur and may be overwritten with new data. Therefore, in order to avoid this, until the change detection lock is released from the outside via the external interface circuit 8 (step 103), only the latest cyclic data is written to the latest value cyclic memory (steps 104 and 105). And the above change detection process is not performed.

As described above, according to the first embodiment, it is not necessary for the external control device to detect the change of the cyclic data by the polling method, so that the detection can be performed at high speed and the load on the external control device can be increased. Can be reduced.

According to the second embodiment, by setting the change detection mask data, it is possible to specify in detail the bits for detecting the change in the cyclic data word. Further, by making all the change detection mask data insignificant, it can be excluded from the change detection target.

According to the third embodiment, by setting the ON change detection mask data, it is possible to specify in detail the bit to be detected when the value changes from 0 to 1 in the cyclic data word. Further, by setting the OFF change detection mask data, it is possible to specify in detail the bit to be detected when the value changes from 1 to 0 in the cyclic data word.

[0043]

As described above, according to the first aspect of the present invention,
When the latest cyclic data is received, this data is temporarily stored in the latest value register, and the previous value from the previous value cyclic memory is tested by the output of the OR circuit in the same cycle as writing the data to the latest value cyclic memory. If the output is insignificant, reception of the latest cyclic data is continued, and if the output is significant, an interrupt signal is generated by an interrupt signal generation circuit to the outside and the latest cyclic data stored in the latest value register is stored. Writes cyclic data to the same address in the previous value cyclic memory and then continues receiving the latest cyclic data, but only writes the latest cyclic data to the latest value cyclic memory until change detection lock is released from outside The external control device uses a polling method. It is not necessary to perform change detection in cyclic data by which the load is reduced in the external control device, also, there is an advantage that it is possible to perform quickly the change detection of cyclic data.

According to the second aspect of the present invention, there is provided a register for storing the address of the cyclic memory at which the change of the cyclic data is detected and the output of the exclusive OR circuit, and reads the contents of the register from outside. Since the external interface circuit is provided, it is possible to read out information on the change of the cyclic data from the outside, and the same effect as the first aspect can be obtained.

According to the third aspect of the present invention, when the latest cyclic data is received, the data is temporarily stored in the latest value register, and the previous value cyclic memory is written in the same cycle as writing the data to the latest value cyclic memory. From the previous value, the mask data is read from the change detection mask memory, and the output of the OR circuit is tested. If the output is insignificant, the reception of the latest cyclic data is continued, and if the output is significant, an interrupt signal is output. The generation circuit generates an interrupt signal to the outside, writes the latest cyclic data stored in the latest value register to the same address of the previous value cyclic memory, and then continuously receives the latest cyclic data. Until the change detection lock is released. The change detection mask data is set so that the bit for detecting a change in the cyclic data word can be specified in detail, and the change detection mask data can be specified. Can be excluded from the change detection target, and the effect that the change of the cyclic data can be promptly detected can be obtained.

According to the fourth aspect of the present invention, a register is provided for storing the address of the cyclic memory in which the change of the cyclic data is detected and the output of the AND circuit, and the external interface for reading the contents of the register from outside is provided. Since the circuit is provided, it is possible to read out information on the change of the cyclic data from the outside, and the same effect as the third aspect can be obtained.

According to the fifth aspect of the present invention, when the latest cyclic data is received, this data is temporarily stored in the latest value register, and the previous value cyclic memory is written in the same cycle as writing the data to the latest value cyclic memory. From the previous change, the on-change detection mask data from the on-change detection mask memory, and the off-change detection mask data from the off-change detection mask memory, and examines the output of the OR circuit. Continue to receive the click data, and if the output is significant, cause the interrupt signal generation circuit to generate an interrupt signal to the outside and replace the latest cyclic data stored in the latest value register with the previous value cyclic memory. Write to the address, then continue receiving the latest cyclic data, but change from outside Until the output lock is released, control is performed such that only the latest cyclic data is written to the latest value cyclic memory. Therefore, by setting the ON change detection mask data, for example, 0 in the cyclic data word can be set. The bit to be detected when changing from 1 to 0 in the cyclic data word can be specified in detail by setting the OFF change detection mask data. Thus, an effect is obtained that the change of cyclic data can be detected quickly.

According to the sixth aspect of the present invention, the register storing the address of the cyclic memory where the cyclic data change is detected and the register storing the output of the on-change AND circuit and the register storing the output of the off-change AND circuit are respectively provided. Provided,
Since an external interface circuit for reading the contents of the register from the outside is provided, it is possible to read information on a change in cyclic data from the outside, and the same effect as that of the fifth aspect can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a typical processing flow in the first embodiment in a time-series manner.

FIG. 3 is a flowchart showing a flow of the above processing in the first embodiment.

FIG. 4 is a flowchart showing a flow of the processing in the first embodiment.

FIG. 5 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 7 is a diagram showing a typical processing flow in the second embodiment in a time-series manner.

FIG. 8 is a flowchart showing a flow of the above processing in the second embodiment.

FIG. 9 is a flowchart showing a flow of the above processing in the second embodiment.

FIG. 10 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 12 is a diagram showing a typical processing flow in a time series according to the third embodiment.

FIG. 13 is a flowchart illustrating a flow of the above-described processing in the third embodiment.

FIG. 14 is a flowchart illustrating a flow of the above-described processing in the third embodiment.

FIG. 15 is a block diagram showing a configuration of a station of a control dataway in an embodiment or a conventional example.

FIG. 16 is an overall schematic diagram of a control dataway configured using the stations.

FIG. 17 is a diagram showing a configuration of a frame.

FIG. 18 is a diagram showing a relationship between cyclic memory data and transmission / reception frames in a conventional example.

[Explanation of symbols]

 4a Latest value cyclic memory 4b Previous value cyclic memory 5a Latest value register 5b Address register 5c Previous value register 6a Exclusive OR circuit 6b OR circuit 7 Interrupt signal generation circuit 8 External interface circuit 9 Change detection control circuit 4c Change detection Mask memory 5d change bit register 6c AND circuit 5e ON change detection mask register 5f OFF change detection mask register 4d ON change detection mask memory 4e OFF change detection mask memory 18, 18a, 18b, 18c External control devices 19, 19a, 19b, 19c station 25 loop transmission path

Continuation of the front page (56) References JP-A-7-38593 (JP, A) JP-A-5-130175 (JP, A) JP-A-62-281611 (JP, A) JP-A-61-228599 (JP, A) JP-A-61-147630 (JP, A) JP-A-58-18740 (JP, A) JP-A-54-136244 (JP, A) Mitsubishi Electric Technical Report, Vol. 65 No. 7, July 1991, Jiro Katsuhara, et al., "Plant Control Core Dataway System", pages. 675-680 Mitsubishi Electric Technical Report, Vol. 69 No. 8, August 1995 issue, Masatoshi Haruta et al., "Information Control Basic System-Integrated Control Bus for Large-Scale Plants," pages. 715-720 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/42 H04Q 9/00 321 JICST file (JOIS)

Claims (6)

(57) [Claims] 1. The control data transmission / reception is controlled by a plurality of stations connected to a loop-shaped transmission line and an external control device.
A broadcast address is set as a destination address of a data frame in which transmission area information including the transmission area data of the station that has acquired the token in the cyclic memory, the address offset from the beginning of the cyclic memory, and the transmission data amount is set. By transmitting the data frame to all the stations, the station receiving the data frame, from the address having the address offset of the transmission area information received from the beginning of its own cyclic memory, the transmission data amount of the transmission area information, In a distributed processing system that expands received data, the latest cyclic memory that stores the latest cyclic data, the previous cyclic memory that stores the previous value, and the latest cyclic data that is received from the network A latest value register that temporarily stores the address, an address register that stores an address of the latest value of the cyclic data in the cyclic memory, an exclusive OR circuit that takes an exclusive OR of the latest value and the previous value, A logical sum circuit for calculating a logical sum of all the bits of the output of the logical sum circuit, an interrupt signal generating circuit for generating an interrupt signal to the outside when the output of the logical sum circuit is significant, and controlling each of the above components. A change detection control circuit for performing control to detect a change in cyclic data, and the change detection control circuit temporarily stores the data in the latest value register when receiving the latest cyclic data, and In the same cycle as writing data to the memory, the previous value from the previous value cyclic memory is tested by the output of the OR circuit. If the output is significant, the reception of the latest cyclic data is continued, and if the output is significant, the interrupt signal generation circuit generates an interrupt signal to the outside and the latest cyclic data stored in the latest value register. The data is written to the same address of the previous value cyclic memory, and then the reception of the latest cyclic data is continued. A cyclic data control method, comprising: 2. An external interface circuit for providing a register for storing an address of a cyclic memory in which a change in cyclic data is detected and an output of an exclusive OR circuit, and for reading the contents of the register from outside The method according to claim 1, wherein: 3. The transmission and reception of control data is controlled by a plurality of stations connected to a loop transmission path and an external control device.
By setting the destination address to the broadcast address, the data frame containing the transmission area data consisting of the data of the transmission area of the station that has acquired the token in the cyclic memory, the address offset from the beginning of the cyclic memory, and the transmission data amount is set. The station that has transmitted the data frame to all stations and received the data frame expands the received data from the address having the address offset of the transmission area information received from the head of its own cyclic memory by the transmission data amount of the transmission area information. In such a distributed processing system, the latest value cyclic memory for storing the latest cyclic data, the previous value cyclic memory for storing the previous value, and the bit of the cyclic data for which the change is detected are specified. Change detection A change detection mask memory for storing the mask data, a latest value register for temporarily storing the latest cyclic data received from the network, an address register for storing the address of the latest cyclic data on the cyclic memory, An exclusive OR circuit that takes the exclusive OR of the previous value and the previous value; an AND circuit that takes the logical product of the output of the exclusive OR circuit and the change detection mask data; A logical sum circuit for calculating a logical sum, an interrupt signal generating circuit for generating an interrupt signal to the outside when the output of the logical sum circuit is significant, and detecting a change in cyclic data by controlling the above-described components. A change detection control circuit for performing control, and the change detection control circuit temporarily receives the latest cyclic data when receiving the latest cyclic data. In the same cycle as writing data to the latest value cyclic memory, the previous value is read from the previous value cyclic memory, the mask data is read from the change detection mask memory, and the output of the logical sum circuit is stored. If the output is insignificant, the reception of the latest cyclic data is continued, and if the output is significant, an interrupt signal is generated externally by the interrupt signal generation circuit and stored in the latest value register. The latest cyclic data is written to the same address in the previous value cyclic memory, and then the reception of the latest cyclic data continues.However, until the change detection lock is released from the outside, the latest Cyclic characterized by performing control to write only cyclic data Data control method. 4. A register for storing an address of a cyclic memory in which a change in cyclic data is detected and an output of an AND circuit, and an external interface circuit for reading the contents of the register from outside. 4. The method according to claim 3, wherein: 5. The transmission and reception of control data is controlled by a plurality of stations connected to a loop transmission path and an external controller, and when each of the stations acquires a token,
By setting the broadcast address to the destination address of the data frame that carries the transmission area data consisting of the data in the transmission area of the station that acquired the token in the cyclic memory, the address offset from the beginning of the cyclic memory, and the amount of transmission data The data frame is transmitted to all the stations, and the station receiving the data frame receives the transmission data amount of the transmission area information from the address having the address offset of the transmission area information received from the head of its own cyclic memory. In a distributed processing system that expands data, the latest cyclic memory that stores the latest cyclic data, the previous cyclic memory that stores the previous value, and which bits of the cyclic data are turned on detection An on-change detection mask memory that stores on-change detection mask data that specifies whether the off-change detection is performed, and an off-change detection mask memory that stores off-change detection mask data that specifies which bit of the cyclic data is to be detected as an off-change. A latest value register for temporarily storing the latest cyclic data received from the network, an address register for storing the address of the latest cyclic data in the cyclic memory, and a detection of the latest value, the inverted value of the previous value, and the ON change. An on-change AND circuit for performing an AND operation with the mask data, an OFF-change AND circuit for performing an AND operation of inversion of the latest value and the previous value and the OFF change detection mask data, and all bits of the output of the ON AND circuit circuit And an OR circuit for performing an OR operation with all the bits of the output of the OFF AND circuit, and when the output of the OR circuit is significant An interrupt signal generation circuit for generating an interrupt signal for the unit, and a change detection control circuit for controlling each of the above components to detect a change in cyclic data. When the cyclic data is received, this data is temporarily stored in the latest value register, and in the same cycle as writing the data to the latest value cyclic memory, the previous value from the previous value cyclic memory is read from the ON change detection mask memory. ON change detection mask data
The off-change detection mask data is read from the off-change detection mask memory, and the output of the OR circuit is tested. If the output is insignificant, reception of the latest cyclic data is continued. An interrupt signal is generated externally by the interrupt signal generation circuit, and the latest cyclic data stored in the latest value register is written to the same address of the previous value cyclic memory, and then the reception of the latest cyclic data is continued. However, until the change detection lock is externally released,
A method of controlling cyclic data, characterized in that control is performed such that only the latest cyclic data is written to the latest value cyclic memory. 6. A register for storing an address of a cyclic memory in which a change in cyclic data has been detected and an output of an on-change AND circuit, and a register for storing an output of an off-change AND circuit. 6. A cyclic data control method according to claim 5, further comprising an external interface circuit for reading data from outside.