JP2875289B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a solid-state imaging device which is a photoelectric conversion device, and an amplifying device for amplifying a photoelectric conversion signal of a photodiode, a selection operation thereof, and a pre-amplifier. The present invention relates to a technology effective when a switch element performing a charging operation is used in a pixel amplification type solid-state imaging device using a MOSFET (insulated gate type field effect transistor).

[Conventional technology]

As a response to the demand for high sensitivity and a high S / N ratio of the solid-state imaging device, for example, a photoelectric conversion signal formed by a photodiode is reported as reported in 1986 There is one that directly reads out to the outside by a source follower amplifier.

[Problems to be solved by the invention]

In the above-mentioned conventional pixel cell, there has been a problem of a process variation of an element for reading a photoelectric conversion signal to the outside. An object of the present invention is to provide a solid-state imaging device capable of obtaining high-sensitivity and high-quality image signals without being affected by process variations.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows.

A photoelectric conversion element, a switch element for reading a signal from the photoelectric conversion element, a first capacitor electrically connected to the switch element, and a second capacitor, wherein the first capacitor is The first connected to the switch element
And a second electrode electrically connected to the second capacitor, a precharge voltage is applied at a first timing via the switch element, and the precharge voltage is applied at a second timing. A voltage corresponding to a substantial photoelectric conversion signal from the photoelectric conversion element is applied, the second electrode is brought into a floating state at the first or second timing, and the second capacitor is connected to the second capacitor. At the timing when the electrode is brought into a floating state, it is connected in series with the first capacitor, and holds an output signal obtained by subtracting a voltage corresponding to the photoelectric conversion signal from the precharge voltage as a reference. And a solid-state imaging device.

[Action]

According to the above-described means, since the photoelectric conversion signal is extracted through the capacitor, the pixel signal output is amplified in accordance with the capacitance ratio between the capacitance value of the photodiode and the capacitor for reading, and the selection path is selected. In this case, it is possible to prevent an adverse effect on an image due to variations in element characteristics.

〔Example〕

FIG. 2 is a main part circuit diagram of an embodiment of a color pixel amplification type solid-state imaging device to which the present invention is applied. FIG. 1 shows a pixel array of three rows and three columns, a selection circuit thereof, and a signal readout circuit, which are exemplarily shown as representatives. Each circuit element constituting the solid-state imaging device is formed on a single semiconductor substrate such as single crystal silicon, though not particularly limited, by a known semiconductor integrated circuit manufacturing technique.

The solid-state imaging device includes the following circuits. 1
One pixel cell consists of a photodiode D1 whose anode electrode is coupled to the circuit ground potential,
Amplification MOSFET Q2 with gate coupled to cathode side electrode of D1
And a switch MOSFET Q1 for supplying a precharge (reset) voltage to the cathode electrode of the photodiode D1 and a selection switch MOSFET Q3 provided on the source side of the amplification MOSFET Q2.

The drain of the amplifying MOSFET Q2 is the same as the drain of Q1
And the gate of the switch MOSFET Q3 is coupled to a second row selection line (vertical scanning line) HL12 extending in the horizontal direction. The drains of the similar amplification MOSFETs Q5 and Q8 and the gates of the switch MOSFETs Q6 and Q9 of the other pixel cells arranged on the same row are coupled in the same manner as the MOSFETs Q2 and Q3. The gate of the switch MOSFET Q1 for precharging is coupled to a first row selection line (vertical scanning line) HL11 that is arranged to extend in the horizontal direction. Similarly, switch MOSFETs Q4 and Q7 for precharging other pixel cells arranged in the same row are also coupled to the first row selection line HL11.

The source of the switch MOSFET Q3 for reading is coupled to a column signal line (vertical signal line) V1 arranged to extend in a vertical row. The sources of similar switch MOSFETs of other pixel cells arranged in the same column are also coupled to the signal line V1. This means that the source of the readout switch MOSFETs Q6 and Q9 is also coupled to the similar column signal lines V2 and V3 in the pixel cells in other columns.

Reset switch MOSFETs Q16 to Q18 are provided between the column signal lines V1 to V3 and the terminal VRV, respectively.
A reset voltage is supplied to the terminal VRV. The gates of these reset switch MOSFETs Q16 to Q18 are commonly connected and coupled to terminal VRP. The terminal VRP is supplied with a reset signal for resetting read capacitors CV1 to CV3 described later.

In the pixel cell of this embodiment, in order to perform color imaging, a color filter of yellow Ye is formed in the pixel cell of the first row and the first column, and the pixel of the second column of the first row is formed. A color filter of cyan Cy is formed in the cell, a color filter of green G is formed in the pixel cell of the first column in the second row, and a white filter is formed in the pixel cell of the second row in the second row. A (transparent) W filter is formed. Each color filter is formed by repeating the same pattern using the above configuration as a basic pattern.

In this embodiment, the first row selection lines HL11 and HL31 of the odd-numbered rows exemplarily shown as the representatives are respectively read in order to independently read the respective color pixel signals corresponding to the color filters as described above. It is coupled to a timing signal line extending in the vertical direction via switch MOSFETs Q10 and Q14. This timing signal line is coupled to terminal PDR1. This terminal PDR1 is supplied with a reset timing signal for resetting the pixel cells in the odd-numbered rows. The even-numbered first row selection line HL21 exemplarily shown as the representative is coupled to a timing signal line extending in the vertical direction via a switch MOSFET Q12. This timing signal line is connected to terminal PD
Combined with R2. This terminal PDR2 is supplied with a reset timing signal for resetting the pixel cells in the even rows.

The odd-numbered second row selection lines HL12 and HL32 exemplarily shown as the representatives are respectively connected to the switch MOSFETs Q11, Q11,
It is coupled to a timing signal line extending in the vertical direction via Q15. This timing signal line is coupled to terminal VD1. The terminal VD1 is supplied with a timing signal for reading out the odd-numbered rows of pixel cells. The even-numbered second row selection line HL22 exemplarily shown as the representative is coupled to a timing signal line extending in the vertical direction via a switch MOSFET Q13. This timing signal line is connected to terminal VD2
Is combined with The terminal VD2 is supplied with a timing signal for reading out the pixel cells in the even-numbered rows.

Switch MOSFETs Q10, Q11, Q12, Q13 and Q1 in the same row as above
The gates of Q4 and Q15 are commonly used, and the vertical selection signals VS1, VS2 and VS2 formed by the vertical shift register VSR.
VS3 is supplied.

In FIG. 2, a circuit symbol is added to each element constituting the pixel cells assigned to the second and third rows in order to prevent the drawing from becoming complicated. Is omitted.

In this embodiment, the following readout circuit is added to take out the photoelectric conversion signal of the photodiode D1 or the like as described above without being affected by the process variation of the element characteristics in the source follower amplification MOSFET Q2, the switch MOSFET Q3, and the precharge MOSFET Q1. It is.

Each of the column signal lines V1 to V3 is coupled to one electrode of each of the capacitors CV1 to CV3. The other electrodes of these capacitors CV1 to CV3 are on the one hand coupled to control lines extending laterally via switch MOSFETs Q20 to Q22. This control line is coupled to terminal CRV. The terminal CRV is supplied with a voltage for resetting the capacitors CV1 to CV3 and a voltage for reading data from a pixel cell into the capacitors CV1 to CV3. The gates of the switch MOSFETs Q20 to Q22 are commonly coupled and switch-controlled by a control signal supplied from a terminal CRP. A timing signal for resetting the capacitors CV1 to CV3 is supplied to the terminal CPR.

The other electrode of the capacitor CV1 is connected to the capacitor CS via the switch MOSFETs Q23 and Q24, respectively.
Connected to one electrode of 1 and CS2. These capacitors
The other electrodes of CS1 and CS2 are connected to a control line connected to the terminal CRV. One electrode of each of the capacitors CS1 and CS2 is coupled to an output signal line extending in the lateral direction via switch MOSFETs Q29 and Q30, respectively. The above switch
An output signal line corresponding to MOSFET Q29 is coupled to terminal S1. The terminal S1 outputs a yellow Ye color pixel signal. An output signal line corresponding to the switch MOSFET Q30 is coupled to the terminal S2. The terminal S2 outputs a green G color pixel signal. The gates of the switch MOSFETs Q29 and Q30 are supplied with a vertical selection signal HS1 formed by a horizontal shift register HSR.

The other electrode of the capacitor CV2 is connected to the capacitor CS3 via switch MOSFETs Q25 and Q26, respectively.
And one electrode of CS4. These capacitors C
The other electrodes of S3 and CS4 are connected to a control line connected to the terminal CRV. One electrode of each of the capacitors CS3 and CS4 is coupled to an output signal line extending in the lateral direction via switch MOSFETs Q31 and Q32. Switch MO above
An output signal line corresponding to SFET Q31 is coupled to terminal S3. The terminal S3 outputs a cyan Cy color pixel signal. The output signal line corresponding to the switch MOSFET Q32 is connected to the terminal S
Combined into 4. The terminal S4 outputs a white W color pixel signal. The gates of the switch MOSFETs Q31 and Q32 are supplied with a vertical selection signal HS2 formed by a horizontal shift register HSR.

The other electrode of the capacitor CV3 is connected to the capacitor CV3.
A switch MOSFET and a capacitor having the same circuit as V1 are provided. This corresponds to the fact that the signal line V3 is connected to the pixel cells of yellow Ye and green G similarly to the signal line V1. However, the gates of the output switch MOSFETs Q33 and Q34 corresponding to the output capacitors CS5 and CS6 are supplied with the vertical selection signal HS3 formed by the horizontal shift register HSR.

An example of the read operation of the second solid-state imaging device is described as a third example.
A description will be given with reference to the equivalent circuit diagram shown in the figure and the timing diagram shown in FIG.

FIG. 3 shows a photodiode D1 and MOSFETs Q1 to Q3.
Is a read equivalent circuit diagram focusing on a pixel cell composed of. In this equivalent circuit diagram, the ground potential of the circuit is given to the terminals VRV and CRV.

Before reading out the pixel cells, the timing signals CRP and VRP
Is set to the high level, and the switch MOSFETs Q20 and Q16 are turned on. Therefore, the capacitor CV1 is reset by applying the circuit ground potential to both ends. Thus, the potential Va of the output electrode of the capacitor CV1 is set to the circuit ground potential. The same applies to all other capacitors CV2, CV3, etc., not shown.

After the timing signal VRP is set to a low level and the switch MOSFET Q16 is turned off, the timing signal H
L12 (VD1) is set to high level. At this time, it is assumed that the vertical shift register VSR sets the vertical selection signal VS1 of the first row to a high level. The above timing signal HL12
In synchronization with the high level of (VD1), the switch MOSFET Q3 for reading is turned on. Therefore, the photoelectric conversion voltage accumulated in the photodiode D1 is transmitted to the capacitor CV1 via the gate and source of the source follower amplification MOSFET Q2 and the switch MOSFET Q3. Similarly, the photoelectric conversion voltage of the corresponding pixel cell is transmitted to the other capacitors CV2, CV3, and the like.

The photoelectric conversion voltage taken into the capacitor CV1 is
The precharge voltage by the precharge operation performed on the photodiode D1 corresponds to the remaining voltage discharged by the photocurrent generated in the photodiodes D1 to D3. At this time, the precharge voltage is
Amplification that causes variations in the conductance characteristics, such as variations in the conductance characteristics, and reads the remaining voltage
The threshold voltage between the gate and the source of the MOSFET Q2 and the like and the conductance characteristics of the switch MOSFET Q3 and the like vary. Therefore, the voltage taken into the capacitor CV1 is affected by the process variation of each element as described above.

In this embodiment, the voltage taken in the capacitor CV1 is not output as it is, but the timing signal supplied to the terminal CRP is set to a low level to set the switch MOSF.
Turn off the ETQ20. As a result, the output side of the capacitor CV1 enters a floating state. After this, the terminal PD
Keep RV at a constant DC potential and connect to terminal PDR1 (HL11)
Is supplied with a high-level timing signal. As a result, since the vertical selection signal VS1 is at the high level as described above, the switch MOSFET Q1 is turned on, and the precharge voltage is supplied to the photodiode D1.

Accordingly, the voltage on the signal line side V1 of the capacitor CV1 becomes a voltage according to the precharge voltage, and the output side of the capacitor CV1 is level-shifted accordingly. In other words, the photodiode D is connected to the output electrode of the capacitor CV1.
Only the photoelectric conversion voltage formed by 1 appears. Because the pre-charge voltage is used as a reference, the process variation of the pre-charge MOSFET Q1 can be offset to zero. Further, since the output signal is formed using the above precharge voltage as a reference voltage instead of the ground potential of the circuit, the process variation of the amplification MOSFET Q2 and the switch MOSFET Q3 is canceled. Such a photoelectric conversion voltage is taken into the capacitor CS1 connected in series with the capacitor CV1.

Therefore, the switch MOSFET Q
When 29 is turned on, only the photoelectric conversion voltage formed by the photodiode D1 held by the capacitor CS1 is obtained at the terminal S1 via the switch MOSFET Q20.

The capacitor CV1 and the like are coupled to the source side of the switch MOSFET Q3 and the like. Since the source of the MOSFET constitutes a parasitic photodiode, a false signal such as a smear easily accumulates. In this embodiment, the influence of the false signal can be eliminated by turning off the switch MOSFET Q23 for selectively connecting the read capacitor CS1 and the like after capturing the signal charge.

In the equivalent circuit diagram of FIG. 3, since the reading of one pixel cell is described, the switch MOSFET Q23 provided between the capacitors CS1 and VC1 is omitted. Since the reading of the photoelectric conversion voltage is performed in parallel with the other capacitors CV2 and CV3 (not shown) in the same manner as described above, the signal voltage held in the capacitor connected in series with the capacitors is synchronized with the horizontal scanning signals HS2 and HS3. Then, each is serially output.

Although not shown, each timing signal for reading a signal from the pixel cell to the capacitor is generated in a horizontal blanking period.

FIG. 5 is a timing chart showing an example of the independent read operation of the color pixel in the circuit of the embodiment shown in FIG.

Since one pixel is composed of the above four color pixels, the vertical shift register VSR simultaneously sets two rows L1 and L2. Also, an interlace gate circuit is provided at the output of the vertical shift register VSR to simultaneously select the above-mentioned one row L1 and two rows in an odd field and to simultaneously select the second row L2 and a third row L3 in an even field. It may be. As described above, 1 is used for the odd field and the even field.
The image signals can be obtained in such a manner as to be selected one by one and the spatial center of gravity corresponding to the interlace is moved up and down.

Therefore, in the first half of the horizontal retrace period, the timing signals CDP1, VD1, and PDR1 are generated in the same order as described above, and the signal of the pixel cells in the first row L1 is transferred to the capacitor CS.
1, let CS3, CS5, etc. hold. After this, the timing signal V
After the RP and CRP are once set to the low level and then set to the high level again to perform the same precharge operation, the timing signals CDP2, VD2 and PDR2 are generated in the same order as described above. As a result, the signal of L2 in the second row is
2, CS4, CS6, etc.

Then, when the horizontal blanking period ends and the video period starts, the horizontal scanning signals HS1 to HS3 and the like are formed in a time series in accordance with the shift operation of the horizontal shift redest HSR. Therefore, the terminals S1 and S1 are synchronized with the horizontal scanning signal HS1.
Yellow Ye held in capacitors CS1 and CS2 from 2
And the green G signal are output from the terminals S3 and S4 in synchronization with the horizontal scanning signal HS2 to output the cyan Cy and white W signals held in the capacitors CS3 and CS4. Hereinafter, each color pixel signal is output independently in the same order in synchronization with the horizontal scanning operation.

Although the circuit configuration described above is formed on a semiconductor substrate, it is necessary to pay attention to parasitic effects such as crosstalk between wirings.

(Embodiment I) FIGS. 1 and 6 are layout diagrams of a pixel portion in this embodiment. In FIGS. 1 and 6, the same symbols are used as in FIG. 1 and FIG. 6 in order to correspond to the circuit diagrams in FIG. 2 and FIG. Although not particularly limited, a description will be given below using an N substrate. FIG. 6 shows a set of a Ye pixel cell, a Cy pixel cell, a G pixel cell, and a W pixel cell to which a color filter has been applied. FIG. 1 shows an enlarged view of the Ye pixel cell shown in FIG.

In the figure, the photodiode light receiving sections of the Ye and W pixels include:
Boron is ion-implanted as a BL implantation layer (BL). This is to increase the photodiode capacitance of the Ye and W pixels so that they are saturated at the same illuminance as G and Cy. Thereby, it is possible to prevent a highlight phenomenon in which a signal is colored when the signal is saturated. In addition, it is also possible to adopt a configuration in which the highlight phenomenon is prevented by external circuit processing or the like and the BL implant layer is unnecessary. The arrangement of the photodiode section and the MOS transistor section in each pixel is such that the photodiode section and the MOS transistor section are alternately arranged in the horizontal scanning line direction, so that the degree of modulation in the horizontal direction can be increased.

Hereinafter, FIG. 1 will be described in detail. FIG. 1A shows a pattern layout for one pixel cell and its periphery. FIG. 1B shows only the gate electrode G1 for the pixel section and the P ⁺ layer (P1) provided thereunder, and FIG. 1C shows the gate electrodes (G1, G2A, G2B, G
2C) and the field oxide film L (commonly referred to as a LOCOS oxide film). In FIG.1A, 7A-7A, 7B
FIGS. 7A, 7B and 7C show the longitudinal sectional structures of the portions -7B and 7C-7C, respectively.

The pixel is a photodiode D1 and MOSFET shown in Fig. 1C.
Q1, Q2, and Q3 (Q1 to Q3 correspond to the transistors in FIG. 3 and represent a precharge switch MOSFET, a source follower amplification MOSFET, and a read switch MOSFET, respectively). The N layer (N1) of the photodiode section D1 is an implantation layer that plays a role of deepening the N layer of the photodiode to improve the sensitivity on the long wavelength side. The photodiode section
D1 and the MOSFET section are electrically separated by the field oxide film L in FIG. 1C.

In this embodiment, as shown in FIG. 1B, the electrical isolation between the pixel cells is made by a gate electrode G1 of polysilicon one layer.
(PDRV) and the P ⁺ layer under the G1 electrode (P1). The gate electrode G1 (PDRV) is for configuring a MOS structure with each pixel cell as a diffusion region.
Also serves as an implantation prevention mask when forming a diffusion region of the OS transistor. Also, as shown in FIGS. 1A and 7C,
Contact hole (C1) between G1 electrode and substrate diffusion layer (N ⁺ layer)
The power supply potential of the source follower amplifier Q2 and the power supply potential of the precharge MOSFET Q1 are shared. In this way, the G1 electrode is used as a common power supply line for the MOS transistors Q1 and Q2. Therefore, a P ⁺ layer (P1) is formed as a PFB implantation layer under the G1 power supply, and the threshold voltage of the MOSFET that gates the G1 electrode is set. The voltage can be set sufficiently higher than the power supply voltage of the power supply line.

This makes it possible to simultaneously perform electrical isolation between pixels while using the G1 electrode as a power supply for the source follower amplifier Q2 and a power supply for the precharge MOSFET Q1.
The effect of such a pixel separation structure is as follows.

(1) Since the G1 electrode serving as the power supply line covers the entire light receiving surface of the solid-state imaging device in a mesh shape, the swing of the power supply line due to the flow of transient current can be suppressed by the gate-substrate capacitance. (The P-well is fixed at a certain DC potential, and the insulating film under the gate is very thin, resulting in a large capacitance value.) (2) The dark current which becomes a problem in pixel separation by the field oxide film SiO _{2 is} Since the structure does not generate stress strain, it can be suppressed to a sufficiently small value.

(3) When a shallow P ⁺ layer is formed on the photodiode surface,
Dark current generated on the surface of the photodiode having a poor interface state can be swept out to the well through the P ⁺ layer below the G1 electrode, and the sensitivity can be increased.

(4) By dividing each pixel by the P ⁺ layer, the well resistance of the substrate can be reduced.

Other than the above, in the case where the G1 electrode is not used in common with the power supply line, the pixel separation may be performed using only the gate electrode G1 (PDRV) or only the P ⁺ layer (P1). Of course. This technique is not limited to solid-state imaging devices, but is widely used for general semiconductor integrated circuits.

In this embodiment, a layout of a polysilicon two-layer structure is shown. As shown in FIG.
The gate electrode G1 of the MOS transistor is the first layer polysilicon, and the gate electrodes G2A and G2 of the active MOS transistor are
B and G2C are used as the second layer polysilicon. By using the first layer polysilicon for the gate electrode G1, pixel separation can be performed irrespective of the operating potential of the second layer gate, and damage in the oxidation process of the second layer polysilicon used as the active MOS gate can be reduced. The number of layers can be reduced as compared with polysilicon.

Further, the gate electrode of the MOS transistor for pixel division may be used as the second layer polysilicon, and the gate electrode of the active MOS transistor may be used as the first layer polysilicon. This case is a disadvantage in the example described above.
Although a short circuit between the active MOS gate electrodes due to the etching residue of the first layer polysilicon can be eliminated, the drive pulse for the active MOS gate causes the M for pixel division to be removed.
The threshold voltage needs to be sufficiently high so that the OS transistor is not turned on.

As shown in FIGS. 1A and 7A, the gate line G2A of the two-layer polysilicon is for connecting to the photodiode D1 through the contact hole (C2) as the gate line of the source follower amplifier Q2. As shown in FIG. 1C, the gate line G2B is connected to the row selection line HL11 as the gate line of the precharge switch MOSFET Q1, and the gate line G2C is connected to the row selection line HL11 as the gate line of the read switch MOSFET Q3.
Connected to HL12.

In FIG. 1C, the gate line HL12 (G2
B) and the gate line HL11 (G2C) running at the lower end of the pixel are arranged in parallel in the horizontal scanning line direction so as not to intersect with each other, so that patterning can be performed on the same layer and the number of steps can be reduced. The reason that the LOCOS oxide film L is drawn out of the gate line HL12 in parallel with the gate line HL12 to the middle of the photodiode portion is that the LOCOS oxide film L reduces the coupling capacitance between the gate line HL12 and the photodiode portion D1 and reduces This is to prevent coupling noise. Further, the gate line HL11 is disposed so as to overlap the pixel separation electrode G1, and the aperture ratio of the pixel can be increased.

On the other hand, in FIG. 1A, a region E shows a mask region for preventing E implantation for threshold voltage control (to prevent DMOS), and plays a role of lowering the threshold voltage of this region. The region EE shows the EE implantation layer and the switch MOSFET Q3
The threshold voltage of Q3 is raised to prevent a leak current at the time of off.

As shown in FIG. 1C, the transistor channel length L of the MOSFETs Q1, Q2, and Q3 is formed by the second polysilicon gate width, and the channel width W is equal to the field oxide film L and the first layer polysilicon gate for partitioning ( Or the vertical distance of the P ⁺ layer (P1)). The MOS transistor portion of each pixel is connected to an aluminum output line (V) connected via a contact hole (C3) shown in FIGS. 1A and 7C.
Light is shielded by 1), eliminating the need to provide a new light-shielding film.

10A and 10B show a process flowchart of the main part of the present invention. In the figure, A shows a section 7A-7A in FIG. 1A, B shows a section 7B-7B, and C shows a section 7C-7C. The manufacturing process will be described below in the order according to the flowchart of FIG.

(A) On a N substrate, boron implant (Implan is Implan
This is a step of forming a P well by thermal diffusion. The EE implant implants boron further to form a high VthMOS region. In the figure, RP indicates a photoresist.

(B) In this step, after boron implantation is performed on the light receiving portion of the Ye, W pixel, thermal diffusion is performed in nitrogen, and the capacitance of the photodiode D1 is adjusted so that the signal current is saturated at the same illuminance.

(C) This is a step of performing phosphorus implantation on the light receiving section to form a deep N-type photodiode D1.

(D) In the figure, SiN indicates a nitride. This is a step of forming a field oxide film (L) by ion-implanting boron and performing thermal diffusion and thermal oxidation while attaching SiN.
The previously implanted boron forms a P ⁺ region on the lower surface of the field oxide film and acts as a channel stopper.

(E) A step of forming a P ⁺ layer (P1) for pixel division by boron implantation. After ion implantation, thermal diffusion is performed in nitrogen.

(F) In the figure, GI1 is an oxide film formed by the first gate oxide film and determines the thickness of the gate insulating film of the MOS transistor below the gate electrode G1. This is a step of performing boron implantation in order to prevent DMOS (Depletion-type MOS) in a region other than the periphery of the MOSFET Q2.

(G) N ⁺ diffusion of MOSFET Q1 and Q2 and first polysilicon gate G
This is a step of performing a TH photo at a C1 contact portion for making a connection with 1. The TH photo is an oxide film at the contact part that allows a direct connection between the polysilicon gate G1 and the N ⁺ diffusion layer as shown in Fig. Refers to a photo process for removing

(H) The step of forming the first polysilicon gate G1. After removing GI1, GI2 is formed. GI2 is an oxide film formed by the second gate oxide film, and the gate electrode G2
(G2A, G2B, G2C) Determines the thickness of the gate insulating film of the MOS transistor below. A contact hole C2 for making a connection between the photodiode D1 and the second polysilicon gate G2A is formed using a TH photo.

(I) forming a second polysilicon gate G2 (G2A, G2B, G2C);

(J) Phosphorus implantation, thermal diffusion in nitrogen, MOSFET
This is a step of forming N ⁺ diffusion in the region and forming an N ⁺ layer on the surface of the photodiode portion. These diffusion regions are formed in regions not hatched in FIG. 1C, that is, regions other than the polysilicon gate and the LOCOS oxide film. Thereafter, in order to make the photodiode D1 into a buried N-type, the surface of the photodiode may be made P ⁺ by boron implantation.

(K) After depositing the PSG (P ₂ O ₅ · SiO ₂ ) interlayer protective film, an aluminum output line connected to the N ⁺ diffusion of MOSFET Q3 through contact hole C3 is formed so as to cover the MOS transistor portion. It is a process.

Embodiment II FIG. 8 shows another embodiment of the present invention. 9A, 9B, and 9C show vertical cross-sectional structures of portions 9A-9A, 9B-9B, and 9C-9C in FIG. 8, respectively.

FIG. 8 shows a layout of a polysilicon three-layer structure. In the figure, the gate electrode G1 of the MOS transistor for pixel division is made of first layer polysilicon, the gate line G2A of the source follower amplifier Q2 and the switch MOS for precharging.
The gate line G2B of the FET Q1 is a second-layer polysilicon, and the gate line G3 of the readout switch MOSFET Q3 is a third-layer polysilicon.

With the three-layer structure, a larger aperture ratio can be obtained than in Example I, but the wiring capacitance of the middle gate line G2B is twice as large as that between G3 on the upper surface and between G1 on the lower surface. Therefore, there is a disadvantage that the waveform of the driving pulse is distorted. Further, as shown in FIG. 8 and FIG. 9C, N ⁺ layer (N2) is by phosphorylation process performed in order to reduce the electrical resistance of the G1 electrode, N ⁺ layer formed by diffusion from the through-hole (C1) In the case where does not reach the adjacent N ⁺ layer, that is, does not reach the outside of the G1 electrode, an N ⁺ layer is formed in advance to establish conduction with the adjacent N ⁺ layer. Therefore, it is not necessary when conduction with the N ⁺ layer can be obtained by diffusion from C1.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, readout from a pixel cell is performed with reference to a precharge voltage via a capacitor, so that noise due to variations in element characteristics of a precharge MOSFET and an amplification MOSFET does not occur, and a high-sensitivity, high-quality image signal is obtained. be able to.

[Brief description of the drawings]

FIG. 1A is a layout diagram showing one embodiment of a pixel unit basic cell of a pixel amplification type solid-state imaging device to which the present invention is applied. FIGS. 1B and 1C are layout diagrams showing main parts in FIG. 1A. FIG. 2 is a main part circuit diagram showing an embodiment of a pixel amplification type solid-state imaging device to which the present invention is applied, FIG. 3 is an equivalent circuit diagram for explaining the readout operation, and FIG. FIG. 5 is a timing chart for explaining an example of the read operation, FIG. 5 is a timing chart for explaining an example of a color image signal read operation, and FIG. 6 is a pixel amplification type solid-state to which the present invention is applied. FIG. 7A is a sectional view taken along section line 7A-7A in FIG. 1A, and FIG. 7B is a sectional view taken along section line 7B-7B in FIG. 1A. 7C is a cross-sectional view taken along section line 7C-7C of FIG. 1A, and FIG. FIG. 9A is a layout view of a main part showing another embodiment of a pixel unit basic cell of a pixel amplification type solid-state imaging device to which the present invention is applied; FIG. 9A is a cross-sectional view taken along section line 9A-9A in FIG. 9B is a sectional view taken along section line 9B-9B in FIG. 8, FIG. 9C is a sectional view taken along section line 9C-9C in FIG. 8, FIG. 10A and FIG. FIG. 4 is a main part process flow chart showing an embodiment of a pixel amplification type solid-state imaging device to which is applied. VSR: Vertical shift register, VSRE: Vertical shift register for sensitivity setting, HSR: Horizontal shift register.

Continuation of front page (56) References JP-A-63-294182 (JP, A) JP-A-63-276377 (JP, A) JP-A-1-154678 (JP, A) (58) Fields studied (Int) .Cl. ⁶ , DB name) H01L 21/339 H01L 27/14-27/148 H04N 5/335

Claims (1)

(57) [Claims] A first capacitor electrically connected to the switch element; a first capacitor electrically connected to the switch element; and a second capacitor electrically connected to the switch element. Has a first electrode connected to the switch element and a second electrode electrically connected to the second capacitor, and is pre-charged at a first timing via the switch element. Charge voltage is given,
At a second timing, a voltage corresponding to a substantial photoelectric conversion signal from the photoelectric conversion element is applied, and at the first or second timing, the second electrode is brought into a floating state, Is connected in series with the first capacitor at a timing when the second electrode is brought into a floating state, and a voltage corresponding to a photoelectric conversion signal is subtracted from the reference precharge voltage. A solid-state imaging device which holds an output signal.