JP2839822B2 - Manufacturing method of high flatness wafer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high flatness wafer whose rear surface is vacuum-sucked flat.

[0002]

2. Description of the Related Art The back surface of a wafer for forming a semiconductor element remains an etched surface and has no luster, so that the front and back sides can be easily distinguished visually and optically. However, as the diameter of the wafer becomes larger and the element becomes finer, the flatness requirement at the time of exposure becomes severer, and a wafer having a higher flatness is desired.

[0003]

By the way, it is more difficult to distinguish a front side and a back side of a wafer whose back surface has been polished as compared with a wafer having a normal etched surface as a back surface, and it is necessary to distinguish by a special identification mark. Further, in the case of a large-diameter wafer of 8 inches or more, there is no escape space for air at the time of vacuum suction, and in a normal vacuum chuck, the wafer does not have an air passage, so that the wafer partially expands and becomes a void, which may cause pattern collapse due to exposure. Vacuum suction is performed slowly or time is left after suction.

[0004] Also, when the wafer is separated from the vacuum chuck, since there is no air passage, a large amount of air must be jetted strongly to partially adhere to the vacuum chuck, which complicates the shape of the vacuum chuck. There is a disadvantage that the wafer is transferred to the surface and the flatness is reduced. For this reason, there is a wafer in which only the convex portion of the irregularities on the back surface is polished and removed, the glossiness is reduced, the air escape at the time of vacuum suction is half-polished to the same level as the etched back surface, and then the surface is polished on one side. Further, simultaneous double-side polishing by a double-side polishing machine is effective for the production of a wafer having a high flatness.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and achieves high flatness by simultaneous polishing on both sides to satisfy the exposure conditions of an 8-inch 64M fine element, and to form a vacuum by forming an air passage on the back surface. An object of the present invention is to manufacture a high flatness wafer in which chucking and desorption by a chuck are made easier than on an etched back surface, and a pattern defect and a decrease in flatness due to transfer to a surface during vacuum suction are reduced.

[0006]

SUMMARY OF THE INVENTION According to the present invention, there is provided a method of manufacturing a high flatness wafer, which comprises lapping or grinding the wafer.
Selective etching process for post-etching to make matte surface
And one side electrolytic grinding on the front side of the wafer to smooth the matte surface
One-side grinding process to make the surface smooth, the front surface smooth and the back surface matte
Wafers on the front side as product wafers
Surface accuracy that can meet the case, and the back side
Set the polishing amount within the range where the recess is not completely removed
The surface is mirror-finished by polishing, and the back
Is characterized by comprising a double-side polishing step of leaving a concave portion serving as an air passage .

[0007]

According to this method, selective etching is performed on both surfaces of a wrapped or ground wafer to form a matte surface having irregularities including grooves serving as air passages, and the wafer surface is ground to remove irregularities, and then subjected to double-side polishing. While removing the grinding damage on the front surface and making it mirror-finished, the concave portion is left on the back surface of the wafer, and the convex portion is polished and removed, and the grooves that serve as air passages are formed, making it easy to vacuum chuck with high flatness Becomes

[0008]

FIG. 1 is an explanatory view showing one embodiment of a method of manufacturing a high flatness wafer according to the present invention. In this method, first, both surfaces 1A and 1B of the wafer 1 subjected to lapping after the slicing shown in FIG.
Pear surface 2 having a large number of uneven portions 2A as shown in FIG.
To Etching of silicon is performed with a mixed solution of nitric acid, hydrofluoric acid and acetic acid. The surface is oxidized by nitric acid, dissolved and removed by hydrofluoric acid, and the reaction is controlled by acetic acid. Conventionally, the reaction rate is increased so that the surface layer containing the processing damage is uniformly dissolved and removed, thereby minimizing the disruption of the flatness formed by lapping, and the composition is nitric acid (50%). The standard ratio of hydrofluoric acid (70%) to acetic acid (90%) is 1: 6: 3, and the roughness is about Rmax 2 μm.

The etchant used for selective etching increases the ratio of acetic acid and adds water to reduce the overall reaction rate, but processing damage is selectively etched in the region. In other words, after the processing damage due to the lapping is etched off, the reaction suppression effect by acetic acid is greatly exerted on the convex portion, and only the concave portion is strongly etched, so that the slight unevenness is emphasized and the surface becomes matte, and the roughness is about Rmax 4 μm. .

[0010] Since the deep processing damage due to lapping is a rotation locus at the time of lapping, the processing damage due to lapping is a rotation locus formed in a parabolic shape from a large number of central portions, and often reaches the edge of the wafer. This becomes a groove by selective etching, and becomes a passage for air.

The number, length and depth of the grooves suitable for attaching and detaching the vacuum chuck can be controlled more easily by lapping than by using grinding. The grinding process can be performed by freely selecting the grain size of the grinding wheel, the rotation of the wafer, and the rotation of the grinding wheel.

The etching solution has the following composition. The composition of the selective etchant is nitric acid (50%)-hydrofluoric acid (70%)-acetic acid (90%)-water ratio of 1: 6: 5:
1 is preferable, and Rmax is 5 μm and PV (peak-valley difference) is 10 μm under the etching conditions of a temperature of 50 ° C. and a time of 10 minutes. When the composition ratio of acetic acid is 1: 6: 4: 1 or less, the selective etching property of the processing strain is reduced, and a matte finish is not obtained.
When the ratio is 1 or more, the suppression of the reaction is increased. And the water is 1:
When the ratio is 6: 5: 0.5 or less, the selective etching property of the processing strain is lowered, and the pattern is not matted. When the ratio is 1: 6: 6: 2 or more, the reaction time is significantly increased.

The average depth of the concaves and convexes formed by the selective etching is limited by removing the grinding damage by double-side polishing and forming a mirror surface so that the concave portion 2A becomes about half the PV value. Generally, it is desirable to set the etching conditions to about 5 to 10 μm by appropriately setting the etching conditions. If it is less than 5 μm, even if electrolytic grinding is performed, damage cannot be completely removed. If it is more than 10 μm, the amount of polishing on both sides increases, and the back surface is also mirror-finished.

Next, the front side 1A of the wafer 1 is shown in FIG.
As shown in FIG. 1B, one side is ground, and as shown in FIG. For this single side grinding, 20
If the electrolytic grinding No. 00 is used, the grinding damage is less than 3 μm, and if a mirror polishing of 5 μm is performed, a good mirror surface is formed. If electrolytic grinding is not used, grinding damage is increased and it becomes difficult to form a mirror surface. Single side grinding amount T
Reference numeral 1 is such that the concave portion 2A of the matte surface 2 on the wafer surface side 1A can be completely removed and a mirror surface can be formed.

Further, the wafer 1 is polished on both sides as shown in FIG. 1C, and the surface 1A is polished as shown in FIG.
Is a mirror surface 8. The double-side polishing machine that can be used at that time may be the same as the conventional one. A carrier plate is arranged between the upper surface plate and the lower surface plate that are opposed to each other, and each one is inserted into a carrier hole formed on the outer periphery of the carrier plate. One wafer 1 is inserted, the carrier plate is planetary-rotated, and a pH 10 mechanochemical polishing solution in which colloidal silica is suspended is supplied to both surfaces of the wafer, and the wafer is polished with a polishing cloth fixed to the opposite surface of each platen. Both sides are rubbed at the same time and polished mechanochemically.

It is well known that double-side polishing can easily obtain high flatness, and TTV (Total Thickness Value) 1
μm or less. Compared to this, TTV 2μm for single side polishing
Therefore, the flatness of the exposure range is ensured by tilting the vacuum chuck. For example, in 16M, the flatness LTV (Total Thickn) in the range of 20 × 20 mm is secured.
ess Value) 0.5 μm or less. If the TTV is improved, the LTV is inevitably improved, and the trouble of tilting during exposure is reduced, and the productivity is improved. Also, the SOI bonded wafer must have a TTV of 1 μm or less.

The polishing amount T2 by this mechanochemical polishing
Is set so that the smooth surface 4 on the wafer front side 1A can be polished to a surface accuracy capable of satisfying the standard as a product wafer, and the concave portion 2A of the matte surface 2 on the wafer back side 1B cannot be completely removed. You. For this reason, when the PV value is set to 10 μm by matte etching and the single-side grinding is set to 5 μm by electrolytic grinding No. 2000, the amount of mirror polishing on both sides is 5 μm, and a half having a large number of continuous groove-shaped recesses 6A is formed on the wafer back side 1B. A pear surface 6 is formed. The glossiness of the back surface can be easily distinguished from the mirror surface, and the result of measurement with a glossmeter is shown in Table 1.

[0018]

[Table 1]

If an oxide film having a thickness of about 100 nm is formed before grinding and the surface is ground and both surfaces are polished, the amount of polishing on the back surface is reduced, and the amount of polishing removal on the convex portions is reduced. Thereby, the groove depth can be controlled.

Since the back surface is as smooth as the mirror surface, traces of vacuum tweezers and traces of belt conveyance have conventionally been conspicuous and avoided, but this characteristic is not a drawback but rather these deposits are harmful to the production of submicron devices. Therefore, it is important to take measures to minimize such traces and to clean them if they occur. Further, particles hardly adhere to this surface, and even if particles or metal impurities adhere, they can be easily removed by washing.

[0021]

According to the method of manufacturing a high flatness wafer according to the present invention, selective etching is performed on both surfaces of the wafer after lapping or grinding to form a large number of concave grooves starting from the rotation locus by lapping or grinding. Use a large-diameter wafer because it has a passage that facilitates the escape of air during vacuum chucking by leaving a concave groove on the back surface of the wafer while leaving a concave groove on the back surface of the wafer while making the surface of the wafer a mirror surface to improve the flatness. When exposing a submicron fine element using a stepper, there is no chuck defect, productivity is improved, and defects due to particles and contamination can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a method for manufacturing a high flatness wafer of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon wafer 1A Wafer front side 1B Wafer back side 2 Pear surface formed by selective etching 2A Recessed groove 4 Smooth surface formed by grinding 6 Semi-polished surface after polishing 6A Groove concave passage 8 Mirror surface after polishing

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/308 H01L 21/308 B

Claims (2)

(57) [Claims] 1. A selective etching step in which a wafer is lapped or ground and then subjected to etching to form a matte surface, a single-side grinding process in which the front side of the wafer is electrolytically ground on one side to make the matte surface smooth, and a surface is smooth. Wafer with matte surface on the back side and product wafer on the front side
Surface accuracy, and the back side is completely recessed
Polishing on both sides by setting the polishing amount within the range not completely removed
This makes the front surface mirror-like and the back surface has air
And a double-side polishing step of leaving a concave portion serving as a passage for the wafer. 2. The composition of an etching solution used for the selective etching is 1: 6: (4-6) :( 0.5-2) in a ratio of hydrofluoric acid-nitric acid-acetic acid-water. The method for manufacturing a high flatness wafer according to claim 1, wherein: