JP2830757B2 - Silicon tester measuring jig - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the measurement of semiconductor wafers, and more particularly to a silicon tester device for measuring a wafer to be measured using a silicon tester wafer comprising a semiconductor wafer having at least a part of the function of an LSI tester. About.

[0002]

2. Description of the Related Art In a conventional semiconductor chip or wafer measurement, various power supplies such as clocks, addresses, and data for the number of I / Os required by an LSI tester and the number of chips required for a chip or a wafer to be measured are used. A signal is supplied, the output from the chip or wafer to be measured is taken into an LSI tester, and the judgment is made by the judgment circuit.

FIG. 3 shows, as an example of a conventional wafer measurement (test), an 8-chip parallel measurement of a DRAM (dynamic random access memory) in a wafer measurement using a memory tester which is a kind of LSI tester. .

Referring to FIG. 3, 21 is a memory tester main body, 22 is a power / signal cable, 23 is a wafer prober,
24 is a vacuum chuck table, 25 is a wafer to be measured (DRAM),
26 is a probe card for 8 chips, and 27 is a contact needle with a bonding pad in a wafer for 8 chips.

A power supply potential and signals for eight chips necessary for measurement are supplied from the memory tester main body 21, and these power supply potentials and signals are supplied to a probe / signal via a power / signal cable 22.
The data is supplied to the eight memory chips on the wafer 25 to be measured from the contact needle 27 attached to the card 26, and the output data from the eight memory chips on the wafer 25 to be measured is supplied from the contact needle 25 to the power / signal cable. The signal is transmitted to the memory / tester main body 21 via 22 and is compared with the expected value pattern by the comparator. After the measurement of eight chips is completed, the probe card 26 is moved by the wafer prober 23 for the measurement of the next eight chips.

[0006]

In the measurement of a wafer by the conventional wafer prober, parallel measurement is sequentially performed on up to eight chips among the chips in the wafer to measure all the chips in the wafer. However, there is a problem that it takes a long time.

Therefore, the present invention has solved the above-mentioned problems,
Provided is a completely new concept of a silicon tester measuring device that enables simultaneous measurement of all chips on a measured wafer using a silicon tester wafer composed of a semiconductor wafer having at least a part of the function of an LSI tester. With the goal. Another object of the present invention is to provide a measuring device for a silicon tester capable of measuring a high temperature.

[0008]

According to the present invention, there is provided a silicon test device.
The test fixture for the tester is the function of the LSI tester on the semiconductor wafer.
A circuit group that functions at least a part of
A plurality of wafers on the wafer to be measured,
Silicon tester wafer that performs chip measurement in parallel
And the silicon tester wafer and the measured wafer
Means for electrically connecting the silicon tester
Has a vacuum chuck hole to fix the wafer with a vacuum chuck
The first member to be measured and the wafer to be measured are
A second member having a vacuum chuck hole for fixing;
The first and second members are fixed via predetermined fixing means, respectively.
First and second fixing boards to be fixed, and the first fixing board
And the second fixed board are positioned so as to be freely adjustable.
Means for fixing the first and second members
Comprising tempered glass, said silicon tester wafer
And the heat for radiating the heat of the wafer to be measured.
It is characterized by having a hot hole .

[0009]

[Preferred Embodiment of the Present Invention] In a preferred embodiment of the present invention, an anisotropic conductive film of silicon resin for contacting a silicon tester wafer and a wafer to be measured, and the silicon tester wafer is fixed by a vacuum chuck. Tempered glass having a vacuum chuck hole and a heat radiating hole, tempered glass having a vacuum chuck hole and a heat radiating hole for fixing a wafer to be measured with a vacuum chuck, and tempered glass 1 having the vacuum chuck hole and a heat radiating hole as set screws. A fixing board 1 for fixing the tempered glass 2 having the vacuum chuck hole and the heat radiation hole with a set screw, and a fixing board 1 for fixing the fixing board 1 to the fixing board 2. A flexible stop bar having a moving function and a function of rotating the fixed board; a power supply for supplying the silicon tester wafer to the fixed board; And a socket or connector for viewing,
A cable for electrically connecting the fixed board and the silicon tester wafer.

[0010]

According to the present invention, since the function of the LSI tester is mounted on the silicon tester wafer, the number of effective chips on the wafer to be measured can be measured simultaneously and in the measurement time of one chip. The measurement time is particularly shortened, and it is possible to simultaneously measure all the effective chips on the wafer to be measured using, for example, a simple and inexpensive LSI tester having a small number of pins (the number of pin electronics cards).

Further, according to the measuring jig of the silicon tester of the present invention, the replacement work of the wafer is simplified, the replacement time is shortened, and the wafer testing process is made particularly efficient.

Further, according to the jig for measuring a silicon tester of the present invention, since the means for efficiently radiating heat generated in the silicon tester wafer and the wafer to be measured is provided, the difference between the wafer and the ambient temperature can be improved. , And the occurrence of a temperature difference between the inside and the outside of the wafer surface is suppressed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

[0014]

Embodiment 1 FIG. 1 is a diagram for explaining the configuration of an embodiment of the present invention. In the present embodiment, a multi-pin high-performance tester for performing parallel measurement is not required, and the memory tester transfers, for example, data for one I / O (input / output) to a silicon tester wafer. Only the judgment result of I / O corresponding to the number of the memory to be measured is output to silicon
What is necessary is just to input from a tester wafer, and therefore, a memory tester with a simple configuration is sufficient. Here, the data for one I / O (input / output) means the data of the I / O pin corresponding to the bit width of 8 if the bit width of the data of the memory chip is, for example, 8 bits.

FIG. 1 shows a configuration of wafer measurement by a jig for measuring a silicon tester wafer connected to the simplified memory tester.

As will be apparent from the following description, the use of the silicon tester wafer measurement jig of the present invention provides a much simpler and therefore less expensive memory tester than conventional memory testers. Combined with conventional memory
Measurement equal to or higher than that of a tester is possible.

Referring to FIG. 1, reference numeral 1 denotes a simplified memory tester, 2 denotes a first power supply / signal cable for electrically connecting the memory tester 1 and the memory tester board 3, and 4 denotes a memory tester. Connector mounted on tester board 3, 5
Is a socket for connection with the connector 4 attached to the first fixed board 10, and 6 is a silicon tester wafer.

Reference numeral 7 denotes a vacuum pump, 8 denotes a wafer to be measured such as a DRAM, 9 denotes a first tempered glass having a vacuum chuck hole for vacuum chucking and stably fixing the silicon tester wafer 6, and 9A denotes a wafer to be measured. This is a second tempered glass having a vacuum chuck hole for stably fixing the measurement wafer 8 by vacuum chucking. The first and second tempered glasses 9, 9A are:
Thermal expansion coefficient is almost equal to that of silicon wafer. The first and second tempered glasses 9 and 9A have a silicon tester.
Heat radiating holes for radiating heat generated from the wafer 6 and the wafer 8 to be measured are provided.

The silicon tester wafer 6 receives data for one I / O from the simple type memory tester 1 and receives data for the I / O corresponding to the number of memories to be measured on the wafer 8 to be measured. A plurality of input data are supplied to the wafer under test 8 and a plurality of output data corresponding to the number of memories under test are determined by the comparator. Preferably, only the determination result is output to the memory tester 1. More specifically, the silicon tester wafer 6 is preferably a wafer under test 8
A pad is provided at a position corresponding to the pad of the upper chip, and a signal to be applied to a plurality of chips on the wafer under test 8 is generated based on data for one I / O supplied from the memory tester 1, There is provided at least a circuit group for inputting and judging outputs from a plurality of chips on the wafer 8 to be measured.

10 and 10A are first and second tempered glasses 9, 9
First and second fixing boards for fixing A with set screws 11. Reference numeral 12 denotes a position for fixing the first and second fixing boards 10 and 10A, and aligning the respective bonding pads of the silicon tester wafer 6 and the wafer under test 8 via the anisotropic conductive film 13. Flexible stop bar for moving the first and second fixed boards 10, 10A vertically and horizontally and rotating each other. Anisotropic conductive film 13
Is made of silicon resin or the like and contains conductive particles and has conductivity in the direction of pressurization, and its ends correspond to the pads of the silicon tester wafer 6 and the corresponding pads of the wafer 8 to be measured, respectively. Touch

Reference numeral 14 denotes a second power / signal cable for connecting the first fixed board 10 and the silicon tester wafer 6;
Is a VBB cable for supplying a negative voltage (VBB, substrate potential) to the surface of the wafer to be measured when the wafer to be measured 8 is a DRAM, and 16 is a VBB cable for measuring the silicon tester wafer 6 and the wafer to be measured 8 It is a radiating fan for radiating heat.

Next, a method of assembling the measuring jig according to the present embodiment shown in FIG. 1 will be described.

First, the silicon tester wafer 6 is fixed to the first tempered glass 9 by vacuum chucking by operating the vacuum pump 7.

Next, the contact portion (one end portion) of the anisotropic conductive film 13 and the bonding pad of the silicon tester wafer 6 are aligned and fixed with an adhesive.

Next, the silicon tester wafer 6, the anisotropic conductive film 13, and the first tempered glass 9 are fixed to the first fixing board 10 with the set screw 11.

Thereafter, the wafer 8 to be measured is fixed to the second tempered glass 9A by vacuum chucking with the vacuum pump 7.

Then, the second tempered glass 9A and the wafer 8 to be measured are fixed to the second fixing board with set screws 11.

Finally, the first fixed board 10 and the second fixed board 10A are vertically moved by the flexible stopper bar 12,
By horizontal movement or rotation, the bonding pad of the wafer 8 to be measured and the contact portion (the other end) of the anisotropic conductive film 13 are aligned and fixed.

In the following, a description will be given of a measurement method in the present embodiment when the wafer 8 to be measured is a DRAM.

The data, address, clock, and power for one input / output are supplied from the simplified memory tester 1 to the first power / signal cable 2, the memory tester board 3, the connector 4, the socket 5, the second Is supplied to the silicon tester wafer 6 via the power / signal cable 14 of FIG.

In the silicon tester wafer 6, all I / Os corresponding to the number of all effective chips in the wafer 8 to be measured
O input data is generated, and the generated input data is supplied from the pad of the silicon tester wafer 6 to the anisotropic conductive film 13.
Is supplied to the corresponding bonding pad of the DRAM chip on the wafer 8 to be measured.

The heat generated by the simultaneous measurement of all the effective chips of the wafer 8 to be measured is radiated by the radiating fan 16 so as to have a uniform surface temperature in the wafer surface.

The output from the memory chip of the wafer 8 to be measured is transmitted to the silicon tester wafer 6 via the anisotropic conductive film 13. In the silicon tester wafer 6, the output of the memory chip from the wafer under test 8 and the expected output value already transmitted from the memory tester 1 are compared and determined by a comparator, and only the determination result is stored in the memory tester 1.
To send to. More specifically, the determination result from the silicon tester wafer 6 is based on the signal cable of the second power supply / signal cable 14, the first fixed board 10, the socket 5, the connector 4, the memory tester board 3, the first The signal is transmitted to the simplified memory tester 1 via the signal cable of the power supply / signal cable 2, and the memory tester 1 executes the processing of the determination result.

According to the present embodiment, the first fixing board 10 and the second fixing board are
Since 10A is fixed, the time required for replacing one wafer to be measured is shortened, for example, the replacement can be typically performed in about 5 minutes. If the number of effective chips is 200, the test time per chip is 2 minutes,
Measurement of all chips (200 pieces) by tester wafer 6
It is completed in about 7 minutes including the time for replacing the wafer.

On the other hand, in the conventional wafer measurement using a wafer prober, it takes about 50 minutes to measure all the effective chips (200 pieces) on the wafer at the time of parallel measurement of 8 chips, and it takes about 1 minute to replace the wafer. Even if it can be performed in about a few minutes, it takes about 51 minutes or more to measure all chips (200 pieces), including the time for replacing a wafer.

Therefore, according to the present embodiment, the measurement time per wafer is reduced to about 1/7 of the conventional wafer measurement.

According to the present embodiment, during simultaneous measurement of all chips, the temperature of the silicon tester wafer 6 and the wafer 8 to be measured is increased by, for example, 40 ° C. from the ambient temperature.
Even when the temperature rises, the surface temperature of both wafers is reduced with respect to the ambient temperature by radiating heat from the heat radiating holes of the first and second tempered glasses 9 and 9A whose inner radiating holes are enlarged by the radiating fan 16. For example, it can be maintained within 5 ° C. The heat of both wafers is radiated from the heat radiating fan 16 and the heat radiating holes of the first and second tempered glasses 9 and 9A, and the temperature difference between the outer circumference and the inner circumference of the silicon tester wafer 6 and the wafer 8 to be measured. (For example, 20 ° C.) can be suppressed within approximately 5 ° C., so that variations in the characteristics of the two wafers due to the temperature difference between the outer circumference and the inner circumference are reduced, and highly accurate measurement is enabled.

[0038]

Embodiment 2 FIG. 2 is a view for explaining a second embodiment of the present invention, and shows a state of wafer measurement in a BT (burn-in test) apparatus using a measurement jig of a silicon tester.

Referring to FIG. 2, a connector 34 is attached to a BT board 32 in a BT device 31, and a measuring jig 33 of a silicon tester is inserted and fixed. BT board 32
Is the memory tester board 3 described with reference to FIG.
And one I / O output from the BT device 31.
The data for O is supplied to the silicon tester wafer 6 via the BT board 32 and the silicon tester wafer 6
The data is input to the chip to be measured on the wafer to be measured 8 from, the output from the chip to be measured on the wafer to be measured 8 is judged by the judgment circuit of the silicon tester wafer 6, and only the judgment result is the BT device It is transmitted to 31. Since the configuration of the measuring jig 33 is the same as that of the first embodiment, description thereof will be omitted.

In this embodiment, a high temperature (for example, 125
C) for a long time (for example, 48 hours).

Further, according to the present embodiment, when simultaneously measuring all the chips on the wafer to be measured, the silicon tester
Even when the temperature of the wafer and the wafer to be measured rises due to heat generation, for example, by 40 ° C. from the ambient temperature, thermal runaway during a burn-in test at 125 ° C. can be prevented by increasing the size of the heat radiation holes on the inner circumference by the heat radiation fan. This can be avoided by radiating heat from the heat radiation holes of the tempered glass, and the surface temperature of both wafers can be maintained within 5 ° C. with respect to the ambient temperature. In addition, variations in the characteristics of the two wafers due to the temperature difference between the outer circumference and the inner circumference of the silicon tester wafer and the wafer to be measured, for example, 20 ° C., are measured by the heat dissipation fan and the heat dissipation holes of the first and second tempered glass. The heat generated by the wafers is radiated, and the temperature difference between the outer and inner circumferences of both wafers is reduced to 5 ° C. or less, thereby enabling highly accurate measurement.

[0042]

According to the present invention as described above,
By mounting part or all of the functions of the LSI tester on the silicon tester wafer, the number of effective chips on the wafer to be measured can be measured simultaneously and in the measurement time of one chip. The measurement time is reduced by, for example, about an order of magnitude, compared to wafer measurement using
For example, using a simple and inexpensive LSI tester with a small number of pins (the number of pin electronics cards), it is possible to simultaneously measure all effective chips on a wafer to be measured.

[0043] According to the measurement jig silicon tester of the present invention, to facilitate the work replacement wafer, to shorten the replacement time, and efficiency of the wafer test process in particular. According to the present invention, a member having a coefficient of thermal expansion comparable to the coefficient of thermal expansion of the wafer, preferably vacuum-chucked with tempered glass, is used to avoid warpage when the wafer is fixed or unnecessary stress or the like, High precision measurement is possible in the BT test.

Further, according to the jig for measuring a silicon tester of the present invention , since the means for efficiently radiating heat generated in the silicon tester wafer and the wafer to be measured is provided, the difference between the wafer and the ambient temperature is provided. , And the temperature difference between the inside and the outside of the wafer can be slightly suppressed, and all the effective chips on the wafer to be measured can be measured with high accuracy. According to the present invention, for example, at the time of high-temperature BT measurement at 125 ° C.,
Even when the silicon tester wafer and the wafer to be measured are heated by, for example, 40 ° C. above the ambient temperature due to the heat generated by the silicon tester wafer and the wafer to be measured, the surface temperature of both wafers is kept within 5 ° C. with respect to the ambient temperature by providing the heat radiating means. It can be maintained, and it is possible to avoid thermal runaway.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a second embodiment of the present invention.

FIG. 3 is a diagram illustrating wafer measurement by a conventional wafer prober.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Simplified memory tester 2 First power / signal cable 3 Memory tester board 4 Connector 5 Socket 6 Silicon tester wafer 7 Vacuum pump 8 Wafer under test 9, 9A First and second tempered glass 10, 10A First and second fixed boards 11 Set screw 12 Flexible stop rod 13 Anisotropic conductive film 14 Second power / signal cable 15 VBB cable 31 BT device 32 BT board

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-21544 (JP, A) JP-A-4-262551 (JP, A) JP-A-4-145538 (JP, A) JP-A-5-154 206227 (JP, A) JP-A-6-273466 (JP, A) JP-A-61-51700 (JP, A) JP-A-58-44845 (JP, U) JP-A-62-157146 (JP, U) 62-157145 (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/66 G01R 31/26

Claims (5)

(57) [Claims] 1. A silicon wafer comprising a circuit group for making at least a part of the function of an LSI tester function on a semiconductor wafer, wherein a plurality of chips on the wafer to be measured are arranged in parallel with each other and arranged opposite to the wafer to be measured.・ Tester wafer and
Means for electrically connecting the silicon tester wafer to the wafer to be measured; a first member having a vacuum chuck hole for fixing the silicon tester wafer with a vacuum chuck; A second member having a vacuum chuck hole fixed by a chuck, first and second fixing boards for fixing the first and second members via predetermined fixing means, respectively, and the first fixing Means for positioning and fixing the board and the second fixed board to each other so as to be adjustable in position. The first and second members include tempered glass, and the silicon tester wafer and the wafer to be measured are provided. A measuring jig for a silicon tester, characterized by having a heat radiating hole for radiating heat. 2. The apparatus of claim 1 , wherein said means for electrically connecting said silicon tester wafer to said wafer to be measured includes a pad for said silicon tester wafer and an anisotropic conductive film. 2. The jig for measuring a silicon tester according to claim 1, wherein the jig is electrically connected to a pad to be measured. 3. The method according to claim 1, wherein the first fixing board is provided with a silicon substrate.
Comprises a socket or connector for supplying power and signals to be supplied to the tester wafer, according to claim 1, characterized in that it comprises a first fixed board and the silicon tester wafer and cables for electrically connecting the Jig for silicon tester. And means for fixing said first fixed board and said second fixed board so as to be capable of adjusting the position of said first fixed board.
Of the fixed board and the second fixed boards to each other is movable in vertical and horizontal directions, and rotatably measuring jig silicon tester of claim 1, wherein the adjusting. (5) Heat dissipation hole of the tempered glass by heat dissipation fan
From the silicon tester wafer and the wafer to be measured
Characterized by further comprising a heat dissipating means for dissipating the heat generated by
The jig for measuring a silicon tester according to claim 1.