JP2815526B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a sequential arithmetic unit which is built in a digital audio device such as a mini disk and calculates and integrates digital data, and has a fixed data length DSP (Digital Signal Processor). And a digital signal processing device using the same.

[0002]

2. Description of the Related Art Conventionally, in a mini-disc for recording / reproducing an audio signal by a magneto-optical method, digital data which is a PCM signal obtained by digitizing an audio signal is stored in a mini disk.
Quadrature Mirror Filter:
Hereafter, the digital data is divided into digital data indicating audio signals of three bands using QMF, and the digital data is compressed and recorded.

[0003] In other words, digital data obtained by digitally converting an audio signal is converted into 0 Hz-
After the digital data of each band of 11kHz and 11kHz-22kHz is divided into two, the above digital data of the band of 0Hz-11kHz is converted to 0Hz-5.5kHz and 5.5kHz using the second stage QMF.
The signal is divided into two at -11 kHz, and is further divided into digital data representing audio signals in three bands together with the digital data in the band of 11 kHz to 22 kHz.

[0004] After that, in the mini disc, each digital data indicating the audio signals of the above three bands is converted into MDC data.
The signals are converted into spectral signals by using a T (Modified Discrete Cosine Transformer) or the like, compressed, and recorded on a magneto-optical disk.

[0005] In the reproduction of such a mini-disc, the recorded spectrum signal of each band is read out from the mini-disc and inversely converted to obtain digital data representing audio signals of three bands. After each digital data is input to the band signal synthesizing unit and band-integrated into a PCM signal indicating an audio signal,
The PCM signal is converted into an audio signal and reproduced as sound.

In the band signal synthesizing section, as shown in FIG. 2, bus lines 21 to which digital data representing audio signals of respective bands of 0-5.5 kHz, 5.5 kHz-11 kHz and 11 kHz-22 kHz are inputted. 22 and 23 are provided respectively. First, the signals of the respective bands input to the respective bus lines 21 and 22 are calculated and integrated by using the QMF 24 in the first stage, and the digital data of 0 to 11 kHz is output to the bus line 25.

After that, the signal of the bus line 25 and the signal of the bus line 23 are arithmetically integrated by using the QMF 26 in the second stage to obtain the original PCM signal 27. Then, although not shown, the PCM signal 27 Is converted to an audio signal and played.

In each of the QMFs 24 and 26, integrated digital data is obtained by performing an operation using a fixed-length DSP having a fixed data length of, for example, 24 bits, and the following (1) and (2) are obtained. The calculation is performed by the formula shown in ()).

[0009]

(Equation 1)

[0010]

(Equation 2)

Note that ADL indicates digital data corresponding to a low-band audio signal, ADH indicates digital data corresponding to a high-band audio signal,
The ADS indicates digital data obtained by integrating the ADL and ADH digital data. The a is a coefficient representing the characteristic of the QMF. In the above case, a total of 24 coefficients when j = 0 to 23 is used. Where q is 0, 1, 2, 3,...
And represents the temporal arrangement of the synthesized data.

[0012]

However, in the above-mentioned conventional configuration, there is a problem that the following calculation error occurs when digital data is calculated using a fixed-length DSP.

That is, in the above-mentioned minidisc, the numerical values of the data to be calculated are standardized so as to be distributed between -1 and 1, and the data length to be quantized is 24 bits or 16 bits. Has been adopted. However, in this specification, the description will be made with an 8-bit data length to simplify the description. Generally, an error may occur when a decimal number is represented by a finite length bit. For example, when a number of 0.2 is represented by 8 bits, it becomes 19 in hexadecimal notation (hereinafter referred to as hex). .

However, 19 (hex) is actually 0.195312
5, which means that an error of 0.0046875 has occurred. In the hexadecimal notation, the leading bit is used as a sign bit, sign bit 0 represents a positive number, sign bit 1 represents a negative number, and digital data a (0 ≦ a <1) is represented by 7 bits. , Its maximum value is displayed as 7F in hexadecimal notation.

Therefore, as an example, since 19 (hex) is 00011001 in 8 bits, 0 (hex) is obtained by excluding the first bit.
011001 represents 2 ⁻³ +2 ⁻⁴ +2 ⁻⁷ , and becomes a positive number from the first bit 0 and becomes 0.1953125.

When the addition of the data a and the data b is performed digitally using such numerical values, (a−e ₁ ) + (b−)
e ₂ ) = a + b−e ₁ −e ₂ , which is −e ₁ −e ₂ smaller than the true value. Note that a and b are true values,
e ₁ and e ₂ indicate errors.

Similarly, for multiplication, (a−e ₁ ) * (b−
e ₂ ) = ab−ae ₂ −be ₁ + e ₁ e ₂ . Where e ₁ e
_{Since 2} is a very small value with respect to ae ₂ and be ₁ and can be ignored, the error of the multiplication works in the direction of decreasing from the true value.

Here, in order to explain more clearly,
A calculation example using the above equations (1) and (2) will be described. First, it is assumed that j = 0 to 1 and the operation of the first-stage QMF 24 is performed with respect to an arbitrary q using the following values.

ADL (2 (q-0)) = 0.2 ADL (2 (q-1)) = 0.4 ADH (2 (q-0)) = 0.3 ADH (2 (q-1)) = 0.5 2a (0 ) = 0.3 2a (1) = 0.5 2a (2) = 0.5 2a (3) = 0.3 ADS (2q) = 0.3 (0.2−0.3) +0.5 (0.4−0.5) = −0.03 −0.05 = −0.08 ADS ( 2q + 1) = 0.5 (0.2 + 0.3) +0.3 (0.4 + 0.5) = 0.25 + 0.27 = 0.52 Further, when the operation of the second stage QMF 26 is executed based on the result of the first stage, It becomes as follows.

First, from the result of the first stage, ADL (2 (q−0)) = − 0.08 ADL (2 (q−1)) = 0.52 Further, 2a (j) is the same as that of the first stage, ADH Is set as follows, ADH (2 (q-0)) = 0.5 ADH (2 (q-1)) = 0.3 ADS (2q) = 0.3 (−0.08−0.5) +0.5 (0.52−0.3) = -0.174 + 0.11 = -0.064 ADS (2q + 1) = 0.5 (-0.08 + 0.5) +0.3 (0.52 + 0.3) = 0.21 + 0.246 = 0.456 This operation is performed using a fixed-length DSP. When the data is calculated digitally (hereafter, the data is shown in hexadecimal notation),

ADL (2 (q-0)) = 19 ADL (2 (q-1)) = 32 ADH (2 (q-0)) = 26 ADH (2 (q-1)) = 402a (0 ) = 26 2a (1) = 40 2a (2) = 40 2a (3) = 26 ADS (2q) = 26 (19−26) +40 (32−40) = FC + F9 = F5 ADS (2q + 1) = 40 ( 19 + 26) +26 (32 + 40) = 1F + 21 = 40 Further, the calculation of the QMF of the second stage based on the result of the first stage is as follows.

First, from the results of the first stage, ADL (2 (q−0)) = F5 ADL (2 (q−1)) = 40 Further, as in 2a (j), the ADH is ADH (2 (q-0)) = 40 ADH (2 (q-1)) = 26 ADS (2q) = 26 (F5-40) +40 (40-26) = EA + 0D = F7 ADS (2q + 1) = 40 (F5 + 40) +26 (40 + 26) = 1A + 1E = 38 Therefore, in the example where the fixed length DSP is used and the data length is calculated by 8 bits, ADS (2q) is calculated by F7 = −
0.0703125, the calculation error is (0.064
−0.0703125), the absolute value of
Since (2q + 1) is 38 = 0.4375, the calculation error is
The absolute value of (0.456−0.4375) is 0.0185.

As described above, in the digital calculation, a calculation error may occur, and it is understood that the calculation result is biased in a direction in which the calculated value becomes smaller than the true value.

In order to reduce the calculation error as described above, it is conceivable to use a DSP having a variable data length. However, a variable-length DSP is more expensive than a fixed-length DSP, and the cost is increased. There is a problem of inviting.

It is an object of the present invention to provide a digital signal processing apparatus capable of reducing operation errors by using a fixed-length DSP capable of reducing costs.

[0026]

In order to solve the above-mentioned problems, a digital signal processing apparatus according to the present invention receives digitized and standardized first and second digital data and fixes the data length. A first computing unit that computes the first and second digital data by integrating the first and second digital data and outputs the third digital data is provided.
Digital data and fourth digital data are input, and the third and fourth digital data are calculated by performing calculations with a fixed data length, and the second calculation is performed to integrate and output fifth digital data. A digital signal processing device provided with a first inverting means for inverting the signs of the third and fourth digital data and inputting the inverted signals to a second computing unit; And a second inverting means for inverting and outputting the sign of the fifth digital data output from the second digital data.

[0027]

According to the above arrangement, when the first and second digital data input to the first arithmetic unit are calculated and integrated, an error occurs in the calculation, and the first and second digital data are compared with the true value, for example. The sign of the third digital data and the fourth digital data generated in the decreasing direction from the first arithmetic unit is inverted by the first inverting means and input to the second arithmetic unit for calculation. .

As a result, the direction of the error with respect to the true value generated in the fifth digital data obtained by the second arithmetic unit is changed in the direction opposite to the direction of the error generated by the first arithmetic unit, that is, the true direction. The direction can be increased from the value. The sign of the fifth digital data can be restored by inverting the sign of the fifth digital data by the second inverting means.

Thus, in the above configuration, the direction in which the error generated in the first arithmetic unit increases and the direction in which the error generated in the second arithmetic unit increases can be reversed. At least one error occurring in each of the first and second computing units can be canceled. From this,
The error of the obtained operation result can be reduced, and the operation result closer to the true value than before can be obtained by using the first and second operation units having a fixed data length.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. The digital signal processing device is divided into band data, such as a mini-disc, for example.When reproducing each digital data recorded by compressing and recording each band data, when integrating the reproduced band data, Used.

In the digital signal processing apparatus, as shown in FIG. 1, each of the bus lines 1, 2, and 3 to which digital data indicating each band data is input is provided. Digital data indicating an audio signal in a 0 Hz-5.5 kHz band is input to the bus line 1, and 0 Hz to 1
Digital data indicating an audio signal in a 1 kHz band is input, and digital data indicating an audio signal in an 11 kHz to 22 kHz band is input to the bus line 3.

Each data value x of the digital data input to each of the bus lines 1, 2, and 3 is standardized and set in a range of -1 <x <1, and each data value x is
For example, it is displayed in 24 bits or 16 bits, and a two's complement display is used as a negative number. In addition, as a display of a negative number, a 1's complement display or a head bit can be used as a sign bit.

There is provided a QMF (first arithmetic unit) 4 which is a band integrating filter to which the digital data of each of the bus lines 1 and 2 is input, and the digital data is calculated and integrated by the QMF 4. . Band integrated 0
Digital data representing an audio signal in a band of 11 Hz to 11 kHz is output from the QMF 4 to the bus line 5. The digital data on the bus line 5 is inverted in sign by a sign inverter (first inversion means) 6 and output to the bus line 8.

On the other hand, 11 kHz-22 from the bus line 3
The digital data representing the audio signal in the kHz band is
The sign is inverted by the sign inverter (first inversion means) 7 and output to the bus line 9. The digital data of each of the bus lines 8 and 9 is input to a QMF (second arithmetic unit) 10.
In the QMF10, each of the digital data is 0Hz-22
The band is integrated with the digital data indicating the audio signal of kHz, and the band-integrated digital data is output to the bus line 11.

The digital data on the bus line 11 is
The sign is inverted again by the sign inverter (second inverting means) 12 and restored to the original sign, and becomes a PCM signal as digital data indicating an audio signal of 0 Hz to 22 kHz.

In each of these QMFs 4 and 10, a DSP (Degi-type) whose data length is set to a fixed length of, for example, 24 bits
tal Signal Processor). Also,
The QMF is an abbreviation for Quadrature Mirror Filter.

Next, a description will be given of a calculation example in each of the QMFs 4 and 10 as follows. In the following calculations, the data length of 24 bits or 16 bits is indicated by 8 bits in order to simplify the description notation and make it easier to see.
To simplify the notation of digital data, the digital data is shown in hexadecimal. In addition, the operations performed by the respective QMFs 4 and 10 are expressed by the following equations (1) and (2).

[0038]

(Equation 3)

[0039]

(Equation 4)

Note that ADL indicates digital data corresponding to a low-band audio signal, ADH indicates digital data corresponding to a high-band audio signal, and
ADS indicates digital data obtained by integrating the digital data of ADL and ADH. The above a is a coefficient representing the characteristic of QMF. In the above case, a total of 24 coefficients when j = 0 to 23 are obtained. The above q is 0, 1, 2, 3,..., And represents the temporal arrangement of the synthesized data.

First, a calculation example in the QMF 4 is as follows. ADL (2 (q-0)) = 19 ADL (2 (q-1)) = 32 ADH (2 (q-0)) = 26 ADH (2 (q-1)) = 40 2a (0) = 26 2a (1) = 40 2a (2) = 40 2a (3) = 26 ADS (2q) = 26 (19−26) +40 (32−40) = FC + F9 = F5 ADS (2q + 1) = 40 (19 + 26) +26 (32 + 40) = 1F + 21 = 40 ADS (2q) = 0B ADS (2q + 1) = B1 when the sign of each operation result is inverted by the sign inverter 6.

Further, based on the digital data of the operation result of the QMF 4 at the first stage and the digital data of the bus line 9 obtained by inverting the digital data from the bus line 3 by the sign inverter 7, The calculation for band integration performed by the QMF 10 is as follows.

First, from the result of the first stage, ADL (2 (q-0)) = 0B ADL (2 (q-1)) = B1 Further, 2a (j) is the same as the first stage, and ADH is With the following settings, ADH (2 (q-0)) = 40 ADH (2 (q-1)) = 26. Further, when the above set values are inverted by the sign inverter 7, ADH (2 (q-0)) = 40 2 (q-0)) = B1 ADH (2 (q-1)) = DA.

Thus, the calculation in the second stage QMF 10 is as follows. ADS (2q) = 26 (0B−B1) +40 (B1−DA) = 16 + F3 = 09 ADS (2q + 1) = 40 (0B + C0) +26 (C0 + DA) = E5 + E1 = C6 The operation thus obtained by QMF10 When the sign of the result is inverted by the sign inverter 12, ADS (2q) = F7 ADS (2q + 1) = 3A.

Therefore, when the arithmetic operation is performed with 8 bits using a fixed-length DSP, the ADS (2q) is calculated as follows: F7 = −0.07
03125, the calculation error is the absolute value of (0.064-0.0703125) 0.0063125, while for ADS (2q + 1),
3A = 0.453125, and the calculation error is (0.456-0.45312
The absolute value of 5) is 0.002875.

By the way, conventionally, when the same operation is performed, the error in ADS (2q) becomes 0.0063125, and ADS (2q)
The error at q + 1) was 0.0185. Therefore, the above configuration can reduce the calculation error as compared with the related art.

As described above, in the above configuration, the fixed-length DSP
However, by providing each of the inversion encoders 6, 7, and 12, the direction in which the calculation error in each of the QMFs 4 and 10 increases can be reversed in the direction of increasing and decreasing. One of the calculation errors can be canceled.

As a result, the above-mentioned configuration is a fixed-length DSP
Can be used for a plurality of stages and series to reduce the error of the operation result as compared with the prior art. Therefore, it is possible to avoid the cost increase caused by using the variable length DSP to reduce the operation error. it can.

[0049]

As described above, the digital signal processing apparatus of the present invention receives the first and second digital data and calculates the first and second digital data by fixing the data length. A first computing unit that computes and integrates and outputs the third digital data;
The third digital data and the fourth digital data are input from the arithmetic unit, and the third and fourth digital data are calculated by performing calculations with a fixed data length. Is provided, further provided are first inverting means for inverting the signs of the third and fourth digital data, respectively, and the fifth digital output from the second arithmetic unit is provided. This configuration is provided with a second inverting unit that inverts the sign of the data and outputs the inverted data.

Therefore, in the above configuration, the direction of the error generated in the first arithmetic unit and the direction of the error generated in the second arithmetic unit can be opposite to each other, so that the data length is fixed. Since the first and second arithmetic units can be used in series to reduce the obtained arithmetic error, it is possible to avoid an increase in cost due to using a variable-length arithmetic unit to reduce the arithmetic error. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processing device of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional digital signal processing device.

[Explanation of symbols]

 Reference Signs List 4 QMF (first computing unit) 6 Sign inverter (first inversion unit) 7 Sign inverter (first inversion unit) 10 QMF (second computing unit) 12 Sign inverter (second inversion unit)

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-304029 (JP, A) JP-A-4-104606 (JP, A) Sharp Technical Report No. 57 (1993-11-10) PP. 57-60 Sharp Technical Report No. 55 (1993-3-10) PP. 43-46 (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 17/10 H03H 17/02 613 H03H 17/02 615 H03H 17/02 641 H03H 17/02 661 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A digitalized and standardized first and second digital data is inputted, and the first and second digital data are calculated by integrating the first and second digital data, and the data length is fixed. First to output 3 digital data
The third digital data and the fourth digital data are input, and the third and fourth digital data are calculated by integrating the third digital data and the fourth digital data. In a digital signal processing device provided with a second arithmetic unit for outputting digital data, first inverting means for inverting the signs of the third and fourth digital data and inputting the inverted signals to the second arithmetic unit are provided. And a second inverting means for inverting the sign of the fifth digital data output from the second arithmetic unit and outputting the inverted signal.