JP2801672B2 - Method for manufacturing semiconductor wafer - Google Patents

Method for manufacturing semiconductor wafer

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Publication number
JP2801672B2
JP2801672B2 JP23495389A JP23495389A JP2801672B2 JP 2801672 B2 JP2801672 B2 JP 2801672B2 JP 23495389 A JP23495389 A JP 23495389A JP 23495389 A JP23495389 A JP 23495389A JP 2801672 B2 JP2801672 B2 JP 2801672B2
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JP
Japan
Prior art keywords
substrate
substrates
heat treatment
wafer
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP23495389A
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Japanese (ja)
Other versions
JPH0397215A (en
Inventor
潔 福田
和由 古川
勝二郎 丹沢
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Toshiba Corp
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Toshiba Corp
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Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、二枚の基板を接着剤を用いることなく直接
接着して一枚の半導体ウェハを製造する方法に関する。
The present invention relates to a method of manufacturing a single semiconductor wafer by directly bonding two substrates without using an adhesive.

(従来の技術) 鏡面に研磨されたシリコン等の基板を洗浄活性化し、
その研磨面同士を室温で接触させると両者は自らの力で
密着する。さらにこの密着した基板を熱処理することに
より接着強度が増加し、強固な接合体ウェハが得られ
る。室温での密着は基板表面に形成されたOH基の相互作
用によるものであり、その後の熱処理による強度増加は
脱水縮合反応等によってOH基同士の結合がSi−O−Si結
合からSi−Si結合に変わるためと考えられている。熱処
理による強度増加は、200℃以上の温度で観測される。
(Prior art) Activate cleaning of a substrate such as silicon polished to a mirror surface,
When the polished surfaces are brought into contact at room temperature, they come into close contact with each other by their own force. Further, by heat-treating the adhered substrate, the adhesive strength is increased, and a strong bonded wafer is obtained. The adhesion at room temperature is due to the interaction of OH groups formed on the substrate surface, and the subsequent increase in strength due to heat treatment is due to the dehydration condensation reaction, etc., where the bonds between the OH groups are changed from Si-O-Si bonds to Si-Si bonds. It is thought to change to. An increase in strength due to heat treatment is observed at temperatures above 200 ° C.

この直接接着技術は、界面に接着剤等の異物が介在し
ないので得られたウェハは熱的にも化学的にも安定であ
り、またpn接合や誘電体埋込みが簡単にできるので、各
種半導体素子に応用されている。またシリコン等の半導
体基板と石英やガラス等の誘電体基板、シリコン基板と
GaAs基板等のように材料が異なる基板を接着すること
で、SOI基板やGaAs on Siウェハを容易に得ることがで
きる。
With this direct bonding technology, the resulting wafer is thermally and chemically stable because there is no foreign matter such as adhesive at the interface, and pn junctions and dielectric embedding can be easily performed. Has been applied to In addition, semiconductor substrates such as silicon, dielectric substrates such as quartz and glass, and silicon substrates
By bonding substrates made of different materials such as a GaAs substrate, an SOI substrate or a GaAs on Si wafer can be easily obtained.

しかしながら、従来の直接接着技術には、次のような
問題があった。
However, the conventional direct bonding technique has the following problems.

第1に、材料が異なる基板同士を直接接着技術により
接着した場合、熱処理の際に基板が剥がれたり破壊され
る、ということがあった。これは、両基板の熱膨張係数
が異なるために熱処理中に応力が発生する結果である。
発生する応力を小さくするために熱処理温度を下げる
と、接合強度が十分に得られない。
First, when substrates made of different materials are directly bonded to each other by a bonding technique, the substrates may be peeled or broken during the heat treatment. This is a result of the occurrence of stress during the heat treatment due to the different thermal expansion coefficients of the two substrates.
If the heat treatment temperature is lowered in order to reduce the generated stress, sufficient bonding strength cannot be obtained.

第2に、二枚の基板を洗浄処理等の前処理を行った
後、基板同士を貼り合わせたときに、前処理条件によっ
ては接着基板の界面にボイド(未接着部分)が発生する
ことがある。また貼り合わせ時にはボイドがなくても、
その後熱処理を行ったときに熱処理条件によってボイド
が発生することがある。このボイドの発生は異なる材料
の基板同士の接着においても、同じ材料の基板同士の接
着においても認められる。このボイドは、接合体ウェハ
を用いて構成される半導体素子の電気的特性や歩留まり
に大きい影響を与えるばかりでなく、素子作製プロセス
の弊害にもなる。特に異なる材料の基板同士の接着の場
合には、このボイドが基板の剥れや割れを招きやすい。
Second, voids (unbonded portions) may occur at the interface of the bonded substrate depending on the preprocessing conditions when the substrates are bonded to each other after performing preprocessing such as cleaning processing on the two substrates. is there. Also, even if there is no void when bonding,
Thereafter, when heat treatment is performed, voids may be generated depending on the heat treatment conditions. The generation of voids is observed both in bonding substrates of different materials and bonding substrates of the same material. These voids not only have a significant effect on the electrical characteristics and yield of the semiconductor device formed using the bonded wafer, but also adversely affect the device manufacturing process. Particularly, in the case of bonding between substrates made of different materials, these voids tend to cause peeling or cracking of the substrate.

(発明が解決しようとする課題) 以上のように従来の直接接着技術には、二枚の基板が
異種材料の場合に接合強度が十分なウェハを得ることが
難しい、前処理や熱処理条件によって界面にボイドが発
生する、といった問題があった。
(Problems to be Solved by the Invention) As described above, in the conventional direct bonding technology, it is difficult to obtain a wafer having a sufficient bonding strength when two substrates are made of different materials, and the interface is determined by pretreatment and heat treatment conditions. There is a problem that voids are generated in the glass.

本発明の目的は、熱膨張係数が異なる基板同士を十分
な接合強度をもって信頼性良く接着する半導体ウェハの
製造方法を提供することを目的とする。
An object of the present invention is to provide a method for manufacturing a semiconductor wafer in which substrates having different coefficients of thermal expansion are reliably bonded with sufficient bonding strength.

本発明の他の目的は、接着界面にボイドの発生のない
優れた半導体ウェハの製造方法を提供することを目的と
する。
Another object of the present invention is to provide an excellent method for manufacturing a semiconductor wafer having no voids at the bonding interface.

[発明の構成] (課題を解決するための手段) 本発明の第1の方法は、熱膨張係数が異なる基板を直
接接着する際に、二枚の基板を室温で貼り合わせて密着
された後に中間温度で第1の熱処理を行い、その後一方
の基板の厚みを減らした後、再度高温で第2の熱処理を
行うことを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) In the first method of the present invention, when two substrates having different coefficients of thermal expansion are directly bonded to each other, the two substrates are bonded together at room temperature and then adhered to each other. The first heat treatment is performed at an intermediate temperature, the thickness of one substrate is reduced, and then the second heat treatment is performed again at a high temperature.

本発明の第2の方法は、基板接着に先立つ基板の洗
浄,乾燥等の前処理工程の最後に、少なくとも一方の基
板を80℃以上の純水中に浸漬する処理を行うことを特徴
とする。
A second method of the present invention is characterized in that at least one of the substrates is immersed in pure water at 80 ° C. or higher at the end of a pretreatment step such as cleaning and drying of the substrates prior to the substrate bonding. .

(作用) 第1の方法において、第1の熱処理工程での中間温度
は、基板が割れたり剥がれたりする温度以下であって、
次の厚みを減らす工程に耐えられる接着強度が得られる
温度であればよい。この第1の処理は、室温での接着強
度が上の条件を満たすならば省略することができる。厚
みを減らす工程は、研磨やエッチングなどで行うことが
できる。機械的な加工をする場合はある程度の接着強度
が必要であるので、第1の熱処理温度を比較的高いもの
とする。エッチングの場合は接着強度は低くてもよく、
第1の熱処理温度を低くすることができる。第2の熱処
理工程は、両基板を強固に結合させるために、第1の熱
処理より高い温度とする。適切な温度は基板材料によっ
て異なるが、熱によって基板の溶融,変形,結晶欠陥の
発生等が起こらない範囲とする。
(Action) In the first method, the intermediate temperature in the first heat treatment step is equal to or lower than a temperature at which the substrate is cracked or peeled,
Any temperature may be used as long as an adhesive strength that can withstand the next step of reducing the thickness is obtained. This first treatment can be omitted if the adhesive strength at room temperature satisfies the above conditions. The step of reducing the thickness can be performed by polishing, etching, or the like. Since a certain degree of adhesive strength is required for mechanical processing, the first heat treatment temperature is set to be relatively high. In the case of etching, the adhesive strength may be low,
The first heat treatment temperature can be lowered. The temperature of the second heat treatment is higher than that of the first heat treatment in order to firmly bond the two substrates. The appropriate temperature varies depending on the substrate material, but is set within a range in which heat does not cause melting, deformation, crystal defects, or the like of the substrate.

この第1の方法によって、基板に割れ等が生じないの
で強固な接合体ウェハが得られる理由を、第1図を参照
して以下に詳細に説明する。第1図(a)は、熱膨張係
数の異なる第1の基板11と第2の基板12を室温で貼り合
わせた状態である。ここで、第1の基板11のほうが第2
の基板12より熱膨張係数が大きいものとする。貼り合わ
せた基板の熱処理のための昇温すると、熱膨張係数の大
きい第1の基板11は第2の基板12より伸びようとする。
しかし両基板は密着一体化しているので、第1の基板11
は第2の基板12によって伸びが抑えられ、第1の基板11
には圧縮応力が生じる。第2の基板12には逆に引張り応
力が生じる。これらの応力は、熱処理温度が高くなるほ
ど、それに比例して大きくなる。これが、熱膨張係数の
異なる密着基板を高温で熱処理したときに剥れや割れが
生じる原因である。一般に半導体ウェハとして用いられ
る固体材料は、圧縮応力には強いが、引張り応力に弱
く、従って今の場合第2の基板12に発生する引張り応力
が問題になる。
The reason why a strong bonded wafer can be obtained because the substrate does not crack or the like by the first method will be described in detail below with reference to FIG. FIG. 1A shows a state in which a first substrate 11 and a second substrate 12 having different coefficients of thermal expansion are bonded at room temperature. Here, the first substrate 11 is the second substrate.
It is assumed that the thermal expansion coefficient is larger than that of the substrate 12. When the temperature of the bonded substrates is raised for heat treatment, the first substrate 11 having a large thermal expansion coefficient tends to extend from the second substrate 12.
However, since both substrates are tightly integrated, the first substrate 11
Is prevented from being stretched by the second substrate 12 and the first substrate 11
Generates a compressive stress. Conversely, tensile stress is generated in the second substrate 12. These stresses increase in proportion to the heat treatment temperature. This is the cause of peeling or cracking when heat treatment is performed on the close contact substrates having different coefficients of thermal expansion at a high temperature. In general, a solid material used as a semiconductor wafer is strong against a compressive stress but weak against a tensile stress. Therefore, in this case, the tensile stress generated in the second substrate 12 becomes a problem.

一方これらの応力は、温度以外に基板の厚さに関係す
る。例えば第1図(b)のように第1の基板11が第2の
基板12に比べて相対的に薄い場合には、第1の基板11に
発生する応力が大きくなる。また、第1の基板11が薄い
と、これが第2の基板12に与える力がそれだけ小さくな
るので第2の基板12に発生する応力は第1図(a)の場
合より小さくなる。すなわち第1図(b)のように第1
の基板11を薄くすると、第1の基板11に発生する圧縮応
力は大きくなり、第2の基板12に発生する引張り応力は
小さくなる。既に述べたように第2の基板12に発生する
引張り応力が剥れ等の原因であるから、第1の基板11を
第2の基板12より薄くすれば、剥れ等を生じることなく
高温での熱処理が可能になる。
On the other hand, these stresses are related to the thickness of the substrate other than the temperature. For example, when the first substrate 11 is relatively thinner than the second substrate 12 as shown in FIG. 1B, the stress generated in the first substrate 11 increases. Further, when the first substrate 11 is thin, the force applied to the second substrate 12 becomes smaller, so that the stress generated in the second substrate 12 becomes smaller than that in the case of FIG. That is, as shown in FIG.
When the substrate 11 is made thinner, the compressive stress generated on the first substrate 11 increases, and the tensile stress generated on the second substrate 12 decreases. As described above, since the tensile stress generated in the second substrate 12 is a cause of peeling or the like, if the first substrate 11 is made thinner than the second substrate 12, the peeling does not occur at a high temperature. Heat treatment becomes possible.

第1の基板11をどの程度薄くすればよいかは、第1の
基板11と第2の基板12の材料,もともとの厚さ,必要と
される強度を得るための熱処理温度等によって異なり、
一概に言えない。本発明者等の実験によれば、GaAs,シ
リコン,石英,ガラス等のよく用いられる基板を強固に
接着するために必要な数百℃以上の熱処理をするために
は、第1の基板11を第2の基板12の1/5以下の厚さとす
れば十分であった。
How thin the first substrate 11 should be depends on the materials of the first substrate 11 and the second substrate 12, the original thickness, the heat treatment temperature for obtaining the required strength, and the like.
I can't say it. According to the experiments performed by the present inventors, the first substrate 11 needs to be heat-treated at a temperature of several hundred degrees Celsius or more, which is necessary for firmly bonding commonly used substrates such as GaAs, silicon, quartz, and glass. It is sufficient if the thickness of the second substrate 12 is 1/5 or less.

また一方または両方の基板の接着する表面に酸化膜等
の膜があっても、それが10μm程度以下であって第2の
基板より十分薄ければ、問題ない。
In addition, even if there is a film such as an oxide film on the surface to which one or both substrates are bonded, there is no problem if it is about 10 μm or less and sufficiently thinner than the second substrate.

第1の基板11の厚さを初めから第2の基板12の1/5程
度にしておけば、高温で熱処理しても問題ない。しかし
基板の厚さは通常数百μmであり、この1/5の厚さでは
薄すぎて基板の取扱いが困難である。また逆に、薄い方
が数百μmであってももう一方がその5倍の厚さとする
と、直接接着により得られるウェハは厚くなり過ぎて、
その後の工程に支障を来たす。またコストも高くなる。
If the thickness of the first substrate 11 is set to about 1/5 of the thickness of the second substrate 12 from the beginning, there is no problem even if the heat treatment is performed at a high temperature. However, the thickness of the substrate is usually several hundred μm, and a thickness of 1/5 is too thin to handle the substrate. Conversely, if the thinner is several hundred μm and the other is five times as thick, the wafer obtained by direct bonding is too thick,
It interferes with the subsequent steps. Also, the cost is increased.

したがって本発明のように、密着基板を剥れ等が生じ
ない中間温度で熱処理して、その後基板の一方の厚みを
減らしてから、再度高温で熱処理する、と言う工程を取
ることが有用になる。
Therefore, as in the present invention, it is useful to take a step of performing a heat treatment at an intermediate temperature at which peeling or the like does not occur on the contact substrate, then reducing the thickness of one of the substrates, and then performing a heat treatment again at a high temperature. .

次に、前処理の最後に高温純水に浸漬する本発明の第
2の方法によれば、得られる接合体ウェハの界面のボイ
ド発生が効果的に抑制される。この事は、実験的に確認
された。なお接合体ウェハの界面のボイドの観察は、走
査型放射温度計(例えば、AGA社製,サーモビジョン68
0)により行った。
Next, according to the second method of the present invention in which the substrate is immersed in high-temperature pure water at the end of the pretreatment, generation of voids at the interface of the obtained bonded wafer is effectively suppressed. This has been confirmed experimentally. Observation of voids at the interface of the bonded wafer is performed using a scanning radiation thermometer (for example, Thermovision 68 manufactured by AGA).
0).

この第2の方法により、ボイドレス接合体ウェハが得
られる理由は、高温の純水浸漬処理によって基板表面の
過剰な水分子が蒸発または気化して除去され、ボイドレ
ス接着に必要な適量の水分子が吸着された状態が得られ
るためと考えられる。従ってこのことから、この第2の
方法によれば、過剰な水分による接着界面の変質が避け
られ、界面の電気的特性が改善されて、半導体素子の特
性向上が図られる。
The reason why the voidless bonded wafer is obtained by the second method is that excessive water molecules on the substrate surface are evaporated or vaporized and removed by high-temperature pure water immersion treatment, and an appropriate amount of water molecules necessary for the voidless bonding are removed. It is considered that an adsorbed state was obtained. Therefore, from this, according to the second method, deterioration of the bonding interface due to excessive moisture is avoided, the electrical characteristics of the interface are improved, and the characteristics of the semiconductor element are improved.

(実施例) 実施例1 鏡面研磨されたシリコン基板と石英基板を用意した。
シリコン基板,石英基板ともに、直径100mm,厚さ500μ
mである。まず両基板を洗浄した。洗浄は両基板とも、
硫酸と過酸化水素の混合液処理→塩酸と過酸化水素の混
合液処理→水洗である。シリコン基板は最後に希弗酸で
処理して水洗した。洗浄後、両基板を約90℃の純水に浸
漬してスピンナーで乾燥し、鏡面同士を清浄な雰囲気下
で接触させて密着させた。次に第1の熱処理を行った。
温度は300℃,雰囲気は窒素,時間は1時間である。次
いで研磨によってシリコン基板の厚さを薄くした。次に
第2の熱処理を窒素雰囲気中で1100℃,1時間行った。
(Example) Example 1 A mirror-polished silicon substrate and a quartz substrate were prepared.
Both silicon and quartz substrates are 100mm in diameter and 500μ in thickness
m. First, both substrates were cleaned. Cleaning is performed on both substrates.
Processing of a mixture of sulfuric acid and hydrogen peroxide → processing of a mixture of hydrochloric acid and hydrogen peroxide → washing with water. Finally, the silicon substrate was treated with dilute hydrofluoric acid and washed with water. After washing, both substrates were immersed in pure water at about 90 ° C., dried with a spinner, and brought into close contact by bringing mirror surfaces into contact with each other in a clean atmosphere. Next, a first heat treatment was performed.
The temperature is 300 ° C., the atmosphere is nitrogen, and the time is 1 hour. Next, the thickness of the silicon substrate was reduced by polishing. Next, a second heat treatment was performed at 1100 ° C. for 1 hour in a nitrogen atmosphere.

シリコン基板を100μm以下に薄くした試料ウェハ
は、その後の第2の熱処理工程で剥がれ等がまったく認
められなかった。またその後のデバイス工程にも耐えら
れた。両基板の接着状態は石英基板を通して目視で観察
することができるが、ボイドの発生は認められなかっ
た。
In the sample wafer in which the silicon substrate was thinned to 100 μm or less, no peeling or the like was observed at all in the subsequent second heat treatment step. In addition, it withstood the subsequent device processes. The bonded state of the two substrates can be visually observed through the quartz substrate, but no void was observed.

シリコン基板の研磨が少なく、その厚さが120μm以
上の試料では、1100℃の第2の熱処理工程で破壊され
た。
In the case of a sample whose silicon substrate was less polished and whose thickness was 120 μm or more, it was destroyed in the second heat treatment step at 1100 ° C.

第2図(a)〜は(f)は、具体的にこの実施例の方
法を適用した高耐圧ダイオード用ウェハの製造工程であ
る。シリコン基板21と石英基板22を上述のように洗浄処
理し、シリコン基板21には接着前にその接着する面にn-
型層24と0.5μmの熱酸化膜23を形成した((a))。
これらを、室温で貼り合わせた後、第1の熱処理を行っ
た((b))。その後シリコン基板21側を研磨してその
厚みを30μmにした((c))。
2 (a) to 2 (f) show the steps of manufacturing a high breakdown voltage diode wafer to which the method of this embodiment is specifically applied. The silicon substrate 21 and the quartz substrate 22 are subjected to the cleaning treatment as described above, and the silicon substrate 21 has n
A mold layer 24 and a 0.5 μm thermal oxide film 23 were formed ((a)).
After bonding them at room temperature, a first heat treatment was performed ((b)). Thereafter, the silicon substrate 21 was polished to a thickness of 30 μm ((c)).

次にシリコン基板21を選択エッチングして溝25を掘
り、露出したシリコン層の側面にp+型層26を拡散形成し
た((d))。この拡散は1100℃で行った。これが第2
の熱処理工程を兼ねている。そして側面に熱酸化膜28を
形成した後、全面に多結晶シリコン膜26を堆積した
((e))。最後に、表面の平坦化のためにシリコン層
21の厚みが21μmになるように研磨を行って、誘導体分
離ウェハを得た((f))。
Next, a groove 25 was dug by selectively etching the silicon substrate 21, and ap + type layer 26 was formed by diffusion on the side surface of the exposed silicon layer ((d)). This diffusion was performed at 1100 ° C. This is the second
Heat treatment step. Then, after forming a thermal oxide film 28 on the side surface, a polycrystalline silicon film 26 was deposited on the entire surface ((e)). Finally, use a silicon layer to planarize the surface.
Polishing was performed so that the thickness of 21 became 21 μm, and a derivative-separated wafer was obtained ((f)).

第3図は、こうして得られたウェハに通常のプロセス
によって形成した高耐圧ダイオードを示している。
FIG. 3 shows a high voltage diode formed on the wafer thus obtained by a normal process.

第4図は類似の応用例で、Si基盤41と石英基盤42を接
着し、反応性イオンエッチング法で垂直側壁を持つ分離
溝43を形成したウェハを示している。
FIG. 4 shows a similar application example, in which a Si substrate 41 and a quartz substrate 42 are bonded to form a separation groove 43 having vertical side walls by a reactive ion etching method.

実施例2 鏡面研磨されたシリコン基板とGaAs基板を用意した。
シリコン基板は直径76mm,厚さ400μmであり、GaAs基板
は直径76mm,厚さ450μmである。
Example 2 A mirror-polished silicon substrate and GaAs substrate were prepared.
The silicon substrate has a diameter of 76 mm and a thickness of 400 μm, and the GaAs substrate has a diameter of 76 mm and a thickness of 450 μm.

まず両基板を洗浄した。GaAs基板の洗浄は、メタクレ
ンによるボイル→アセトン置換→エタノール置換→水洗
→塩酸ボイル→水洗である。シリコン基板の洗浄は実施
例1と同じである。
First, both substrates were cleaned. The cleaning of the GaAs substrate is boiled with methacrene → substitution with acetone → substitution with ethanol → rinsing with water → boiling with hydrochloric acid → rinsing with water. The cleaning of the silicon substrate is the same as in the first embodiment.

洗浄後、両基板をスピンナーで乾燥し、鏡面同士を清
浄な雰囲気下で接触させて密着させた。次に第1の熱処
理を行った。温度は400℃,雰囲気はアルゴン,時間は
1時間である。エッチングによりGaAs基板の厚みを20μ
mに減らし、次いで第2の熱処理を、アルゴン雰囲気中
で600℃,1時間行った。
After the cleaning, both substrates were dried with a spinner, and the mirror surfaces were brought into close contact with each other in a clean atmosphere. Next, a first heat treatment was performed. The temperature was 400 ° C., the atmosphere was argon, and the time was 1 hour. GaAs substrate thickness 20μ by etching
m and then a second heat treatment was performed at 600 ° C. for 1 hour in an argon atmosphere.

この結果、基板に剥がれや破壊はなく、接合強度も十
分であり、その後のデバイス工程にも絶えられた。
As a result, there was no peeling or destruction of the substrate, the bonding strength was sufficient, and the subsequent device process was stopped.

実施例3 片面を鏡面研磨した多数のシリコン基板を用意した。
いずれも面方位(100),比抵抗10Ω・cmのp型,直径7
6mm,厚さ450μmである。これらの基板をまず洗浄処理
した。洗浄処理は、過酸化水素水と硫酸の混合液処理
と、王水処理である。
Example 3 A number of silicon substrates having one surface mirror-polished were prepared.
All have plane orientation (100), p-type with specific resistance of 10Ωcm, diameter 7
6 mm, thickness 450 μm. These substrates were first cleaned. The cleaning treatment is a mixture treatment of a hydrogen peroxide solution and sulfuric acid and an aqua regia treatment.

洗浄処理した基板のうち30枚は、沸騰している純水中
に浸漬して清浄雰囲気に取り出して、鏡面同士を接触さ
せて接着ウェハを得た(Aタイプ)。他の30枚の基板
は、80℃の純水中に浸漬して清浄雰囲気中に取り出し、
同様に鏡面同士を接触させて接着ウェハ得た(Bタイ
プ)。
30 of the cleaned substrates were immersed in boiling pure water and taken out to a clean atmosphere, and mirror surfaces were brought into contact to obtain an adhesive wafer (A type). The other 30 substrates were immersed in pure water at 80 ° C and taken out in a clean atmosphere.
Similarly, the mirror surfaces were brought into contact with each other to obtain a bonded wafer (B type).

Aタイプのウェハ15枚と、Bタイプのウェハ15枚の計
30枚について、界面のボイドの有無をInSb検出器とする
走査型放射温度計により調べた。いずれにも、ボイドは
認められなかった。
A total of 15 A type wafers and 15 B type wafers
For 30 sheets, the presence or absence of voids at the interface was examined with a scanning radiation thermometer using an InSb detector. No voids were observed in any of them.

更に以上の接着ウェハに対して窒素雰囲気中で1000
℃,1時間の熱処理を行った。そして再度走査型放射温度
計によりボイド検査を行ったところ、どのウェハでもボ
イドは検出されなかった。
In addition, 1000 wafers in a nitrogen atmosphere
Heat treatment was performed at ℃ for 1 hour. When void inspection was performed again by the scanning radiation thermometer, no void was detected in any of the wafers.

比較のため、純水処理の温度を低くした他、同様の条
件で接着シリコンウェハを作成した。そのうち一組は、
23℃の純水処理を行ったもの(Cタイプ)であり、他の
一組は70℃の純粋処理を行ったもの(Dタイプ)であ
る。これらCタイプ,Dタイプの接着ウェハでも、熱処理
前はボイドは検出されなかった。しかし窒素雰囲気中,1
000℃,1時間の熱処理を行ったところ、Cタイプでは20
枚中10枚(50%)にボイドが発生し、Dタイプでは15枚
中7枚(47%)にボイドが発生した。
For comparison, a bonded silicon wafer was prepared under the same conditions except that the temperature of the pure water treatment was lowered. One of them is
This is a type subjected to pure water treatment at 23 ° C. (C type), and the other set is a type subjected to pure treatment at 70 ° C. (D type). No voids were detected in these C-type and D-type bonded wafers before the heat treatment. However, in a nitrogen atmosphere, 1
After heat treatment at 000 ° C for 1 hour, C type
Voids occurred in 10 out of 50 sheets (50%), and voids occurred in 7 out of 15 sheets (47%) in the D type.

実施例4 実施例3と同じシリコン基板を40枚用意し、そのうち
10枚の基板には表面にシリコン酸化膜(0.7μm)を形
成し、他の10枚の基板には表面にシリコン窒化膜(0.4
μm)を形成した。そして全ての基板を実施例3と同様
の方法で洗浄処理し、更に沸騰している純水中に浸した
後、清浄雰囲気に取り出し、酸化膜を形成した基板と膜
形成をしていない基板を鏡面同士接着させて10枚の接着
ウェハを作成し(Eタイプ)、同様に窒化膜を形成した
基板と膜形成していない基板を鏡面同士接触させて10枚
の接着ウェハを作成した(Fタイプ)。
Example 4 The same 40 silicon substrates as in Example 3 were prepared.
A silicon oxide film (0.7 μm) is formed on the surface of ten substrates, and a silicon nitride film (0.4 μm) is formed on the other ten substrates.
μm). Then, all the substrates were subjected to a cleaning treatment in the same manner as in Example 3, further immersed in boiling pure water, taken out in a clean atmosphere, and the substrate on which the oxide film was formed and the substrate on which no film was formed were removed. Mirror surfaces were bonded together to make ten bonded wafers (E type), and similarly, a substrate on which a nitride film was formed and a substrate on which no film was formed were brought into mirror contact with each other to make ten bonded wafers (F type). ).

これらのウェハについて実施例3と同様にボイドの検
査をしたが、ボイドはいずれのウェハにも認められなか
った。またこれらのウェハに、実施例3と同様の高温熱
処理を行った後も、ボイドの発生は認められなかった。
These wafers were inspected for voids in the same manner as in Example 3, but no voids were found on any of the wafers. Further, even after performing the same high-temperature heat treatment as in Example 3 on these wafers, generation of voids was not recognized.

実施例5 片面が鏡面研磨されたGaAs基板を用意し、これを洗浄
処理した。洗浄処理は、トリクレンとアセトンによる煮
沸処理と、酸処理である。その後、沸騰している純水中
に基板を浸して清浄雰囲気中に取り出し、二枚ずつ鏡面
同士を貼り合わせて接着ウェハを得た。
Example 5 A GaAs substrate having one surface mirror-polished was prepared, and this was subjected to a cleaning treatment. The cleaning treatment is a boiling treatment with tricrene and acetone and an acid treatment. Thereafter, the substrate was immersed in boiling pure water and taken out in a clean atmosphere, and two mirror surfaces were bonded together to obtain an adhesive wafer.

得られた接着ウェハを実施例3と同様にボイド検査し
たが、ボイドは検出されなかった。
The resulting bonded wafer was inspected for voids as in Example 3, but no voids were detected.

更に得られたウェハを窒素雰囲気中で500℃,1時間の
熱処理をした。この熱処理をしたウェハにもボイドは検
出されなかった。
Further, the obtained wafer was subjected to a heat treatment at 500 ° C. for 1 hour in a nitrogen atmosphere. No voids were detected in the heat-treated wafer.

実施例6 片面が鏡面研磨されたInP基板を用意し、これを実施
例5と同様の条件で洗浄処理した。その後、90℃の純水
中に基板を浸して清浄雰囲気中に取り出し、二枚ずつ鏡
面同士を貼り合わせて接着ウェハを得た。
Example 6 An InP substrate having one surface mirror-polished was prepared, and was subjected to a cleaning treatment under the same conditions as in Example 5. Thereafter, the substrate was immersed in pure water at 90 ° C., taken out in a clean atmosphere, and two mirror surfaces were stuck together to obtain an adhesive wafer.

得られた接着ウェハを実施例3と同様にボイド検査し
たが、ボイドは検出されなかった。
The resulting bonded wafer was inspected for voids as in Example 3, but no voids were detected.

更に得られたウェハを実施例5と同様の条件で熱処理
をした。この熱処理をしたウェハにもボイドは検出され
なかった。
Further, the obtained wafer was heat-treated under the same conditions as in Example 5. No voids were detected in the heat-treated wafer.

実施例7 片面が鏡面研磨されたGaP基板を用意し、これを実施
例5と同様の条件で洗浄処理した。その後、沸騰してい
る純水中に基板を浸して清浄雰囲気中に取り出し、二枚
ずつ鏡面同士を貼り合わせて接着ウェハを得た。
Example 7 A GaP substrate having one surface mirror-polished was prepared, and was subjected to a cleaning treatment under the same conditions as in Example 5. Thereafter, the substrate was immersed in boiling pure water and taken out in a clean atmosphere, and two mirror surfaces were bonded together to obtain an adhesive wafer.

得られた接着ウェハを実施例3と同様にボイド検査し
たが、ボイドは検出されなかった。
The resulting bonded wafer was inspected for voids as in Example 3, but no voids were detected.

更に得られたウェハを実施例5と同様の条件で熱処理
をした。この熱処理をしたウェハにもボイドは検出され
なかった。
Further, the obtained wafer was heat-treated under the same conditions as in Example 5. No voids were detected in the heat-treated wafer.

[発明の効果] 以上述べたように本発明によれば、熱膨張係数が異な
る基板を強固に直接接着した半導体ウェハを得ることが
できる。また本発明によれば、接着界面にボイドが発生
しない優れた半導体ウェハを得ることができる。
[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a semiconductor wafer in which substrates having different coefficients of thermal expansion are firmly and directly bonded. Further, according to the present invention, it is possible to obtain an excellent semiconductor wafer in which no void is generated at the bonding interface.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)(b)は、本発明の作用を説明するための
図、 第2図(a)〜(f)は、具体的な実施例の誘電体分離
ウェハの製造工程を示す図、 第3図は得られたウェハを用いた高耐圧ダイオードの構
造を示す図、 第4図は他の誘電体分離ウェハの断面図である。 11……第1の基板、12……第2の基板、21,41……シリ
コン基板、22,42……石英基板、23……酸化膜、24……n
-型層、25,43……溝、26……p+型層、27……多結晶シリ
コン膜、28……酸化膜。
FIGS. 1 (a) and 1 (b) are diagrams for explaining the operation of the present invention, and FIGS. 2 (a) to 2 (f) are diagrams showing a manufacturing process of a dielectric isolation wafer of a specific embodiment. FIG. 3 is a view showing the structure of a high voltage diode using the obtained wafer, and FIG. 4 is a sectional view of another dielectric isolation wafer. 11 first substrate, 12 second substrate, 21, 41 silicon substrate, 22, 42 quartz substrate, 23 oxide film, 24 n
- -type layer, 25, 43 ...... groove, 26 ...... p + -type layer, 27 ...... polycrystalline silicon film, 28 ...... oxide film.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/02 H01L 27/12──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/02 H01L 27/12

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】少なくとも一方が半導体であって、それぞ
れの少なくとも片面が鏡面研磨された熱膨張係数の異な
る二枚の基板の研磨面同士を直接接着して半導体ウェハ
を製造するに際し、二枚の基板を室温で貼り合わせた
後、中間温度で第1の熱処理を行い、次いで一方の基板
の厚みを減らした後、高温で第2の熱処理を行うことを
特徴とする半導体ウェハの製造方法。
A semiconductor wafer is manufactured by directly bonding polished surfaces of two substrates having different coefficients of thermal expansion, at least one of which is a semiconductor, and at least one surface of which is mirror-polished, when manufacturing a semiconductor wafer. A method for manufacturing a semiconductor wafer, comprising: bonding a substrate at room temperature, performing a first heat treatment at an intermediate temperature, reducing the thickness of one substrate, and then performing a second heat treatment at a high temperature.
【請求項2】少なくとも一方が半導体であって、それぞ
れの少なくとも片面が鏡面研磨された二枚の基板の研磨
面同士を直接接着して半導体ウェハを製造するに際し、
二枚の基板を洗浄処理した後、80℃以上の純水中に浸漬
して取り出し、その後二枚の基板を貼り合わせて熱処理
することを特徴とする半導体ウェハの製造方法。
2. A method for producing a semiconductor wafer, wherein at least one of the substrates is a semiconductor, and at least one side of each of the substrates is mirror-polished, and the polished surfaces of the two substrates are directly bonded to each other to produce a semiconductor wafer
A method for manufacturing a semiconductor wafer, comprising cleaning two substrates, immersing the substrates in pure water at a temperature of 80 ° C. or higher, taking out the substrates, and bonding and heat-treating the two substrates.
JP23495389A 1989-09-11 1989-09-11 Method for manufacturing semiconductor wafer Expired - Lifetime JP2801672B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23495389A JP2801672B2 (en) 1989-09-11 1989-09-11 Method for manufacturing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23495389A JP2801672B2 (en) 1989-09-11 1989-09-11 Method for manufacturing semiconductor wafer

Publications (2)

Publication Number Publication Date
JPH0397215A JPH0397215A (en) 1991-04-23
JP2801672B2 true JP2801672B2 (en) 1998-09-21

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ID=16978848

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Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP2801672B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2609198B2 (en) * 1992-08-07 1997-05-14 信越半導体株式会社 Semiconductor substrate manufacturing method
JPH07169659A (en) * 1994-10-25 1995-07-04 Toshiba Corp Method of joining semiconductor wafer
JP4750065B2 (en) * 1995-04-06 2011-08-17 Sumco Techxiv株式会社 Manufacturing method of bonded semiconductor wafer
JP4628580B2 (en) * 2001-04-18 2011-02-09 信越半導体株式会社 Manufacturing method of bonded substrate
JP4655797B2 (en) * 2005-07-19 2011-03-23 信越半導体株式会社 Manufacturing method of directly bonded wafer

Also Published As

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