JP2758702B2 - Integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device including a means for avoiding an internal signal propagation delay neck of a one-chip LSI.

[Conventional technology]

Conventionally, due to recent CAD developments, the internal signal propagation bottleneck for this kind of one-chip LSI has been able to be predicted to some extent before a product is completed. But now
Large-scale and multifunctional LSIs are progressing at an extremely high speed. Therefore, even if the internal signal propagation bottleneck is found in advance, a great effort is required for re-circuit design.

It is also possible to solve the problem from the characteristics of LSI,
Depending on the magnitude of the propagation delay, the area of the LSI may be greatly changed.

In addition, most of the circuits currently use a synchronous system, but the frequency is moving from 20MHz to over 30MHz. In this case, as shown in FIGS. 5 and 6, a two-phase clock from two clock drivers 2 is used in many cases.
At MHz, only a delay time of about 25 nsec. Was allowed.

As described above, since the operation is conventionally limited to one type of limited operation, a method for coping with the delay bottleneck even if it is predicted in advance is limited.

[Problems to be solved by the invention]

In the above-described conventional method of avoiding signal propagation delay, the internal clock frequency is always the same, and the operation of the microprogram and the user ROM that control the internal cannot be changed in terms of timing with respect to the internal delay. ing.

Therefore, even if it is known in advance that a signal delay will occur, not only a great deal of effort or effort is required to deal with the delay, but it may not be possible to correct it.

An object of the present invention is to provide an integrated circuit device capable of eliminating a delay bottleneck only by internal processing.

[Means for solving the problem]

The integrated circuit device according to the present invention includes a frequency divider that temporarily changes the frequency of the clock signal to a low frequency for a predetermined period in order to avoid a propagation delay generated when the clock signal input from the clock driver is distributed to a predetermined internal circuit. As control means, frequency dividing means for dividing the clock signal to the low frequency, frequency dividing ratio controlling means for controlling the dividing start timing and frequency dividing period of the frequency dividing means, and output of the frequency dividing ratio controlling means And selecting means for inserting the low frequency into the clock signal for the predetermined period in response to the frequency division ratio signal.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a waveform chart for explaining the operation of the figure.

First, a clock input 1 is input from outside the LSI and supplied to a plurality of clock drivers 2 inside the LSI. This clock driver 2 normally plays the role of a buffer. Therefore, as shown in FIG. 2, the waveform is the same as the waveform of the clock input. The output of the clock driver 2 is supplied to a plurality of frequency dividing circuits 3 inside, and a frequency dividing ratio control circuit input 4 controls this circuit.

That is, as the input of the frequency division ratio control circuit 4 becomes high level, the timing at which the output of the frequency division circuit 3 becomes a bottleneck of the internal signal propagation delay occurs as shown in FIG. 2A.

In this way, by extending only this portion for a predetermined period, the LSI operates as if operating at a half frequency while operating at the same frequency from the outside of the LSI. In other words, there is actually a delay, but the bottleneck has been eliminated.

FIGS. 3 and 4 show an example of a specific circuit logic of the frequency dividing circuit and the frequency dividing ratio control circuit. In the present embodiment, the frequency division ratio is shown as 1/2. The frequency dividing circuit shown in FIG. 3 includes one F / F and a switching circuit. The frequency division ratio control circuit shown in FIG. 4 includes a shifter and an OR circuit.

In the present invention, these circuit configurations are possible in other various types.

The input to the frequency division ratio control circuit uses a signal that has been known in advance as an input.

〔The invention's effect〕

As described above, according to the present invention, by knowing in advance the control signal where the signal propagation delay is large, it is possible to lower the frequency at the bottleneck.

As a result, a substantially large delay time can be contained internally. Also, by extending the output of the ROM area,
In the case of the static configuration, the frequency is actually reduced, and the delay time is absorbed.

In this way, it is possible to expect a movement as if the delay bottleneck was eliminated without lowering the apparent frequency only by the internal processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 3 is a circuit diagram of the frequency dividing circuit shown in FIG. 1, and FIG. FIG. 5 is a circuit diagram of a frequency division ratio control circuit shown in FIG. 5, FIG. 5 is a block diagram showing a conventional example, and FIG.
It is an operation waveform diagram of the figure. DESCRIPTION OF SYMBOLS 1 ... Clock input, 2 ... Clock driver, 3 ... Division circuit, 4 ... Division ratio control circuit, 5 ... Output control circuit, 6 ...
ROM area.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 1/10 H01L 27/04 H01L 21/82

Claims (1)

(57) [Claims] A frequency dividing control means for temporarily changing a frequency of a clock signal to a low frequency for a predetermined period in order to avoid a propagation delay caused when a clock signal input from a clock driver is distributed to a predetermined internal circuit. Frequency dividing means for dividing the clock signal to the low frequency, frequency dividing start timing of the frequency dividing means and frequency dividing ratio controlling means for controlling the frequency of the dividing cycle, and frequency dividing outputted by the frequency dividing ratio controlling means Selecting means for inserting the low frequency into the clock signal for the predetermined period in response to the ratio signal.