JP2752388B2 - Ｒｄｓ受信機におけるデータ復調回路 - Google Patents

Ｒｄｓ受信機におけるデータ復調回路

Info

Publication number
JP2752388B2
JP2752388B2 JP63256432A JP25643288A JP2752388B2 JP 2752388 B2 JP2752388 B2 JP 2752388B2 JP 63256432 A JP63256432 A JP 63256432A JP 25643288 A JP25643288 A JP 25643288A JP 2752388 B2 JP2752388 B2 JP 2752388B2
Authority
JP
Japan
Prior art keywords
circuit
lock
pll circuit
pll
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63256432A
Other languages
English (en)
Japanese (ja)
Other versions
JPH02104041A (ja
Inventor
俊人 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PAIONIA KK
Original Assignee
PAIONIA KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PAIONIA KK filed Critical PAIONIA KK
Priority to JP63256432A priority Critical patent/JP2752388B2/ja
Priority to DE3920330A priority patent/DE3920330A1/de
Publication of JPH02104041A publication Critical patent/JPH02104041A/ja
Application granted granted Critical
Publication of JP2752388B2 publication Critical patent/JP2752388B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/28—Arrangements for simultaneous broadcast of plural pieces of information
    • H04H20/33—Arrangements for simultaneous broadcast of plural pieces of information by plural channels
    • H04H20/34—Arrangements for simultaneous broadcast of plural pieces of information by plural channels using an out-of-band subcarrier signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H2201/00—Aspects of broadcast communication
    • H04H2201/10—Aspects of broadcast communication characterised by the type of broadcast system
    • H04H2201/13—Aspects of broadcast communication characterised by the type of broadcast system radio data system/radio broadcast data system [RDS/RBDS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Circuits Of Receivers In General (AREA)
JP63256432A 1988-10-12 1988-10-12 Ｒｄｓ受信機におけるデータ復調回路 Expired - Fee Related JP2752388B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63256432A JP2752388B2 (ja) 1988-10-12 1988-10-12 Ｒｄｓ受信機におけるデータ復調回路
DE3920330A DE3920330A1 (de) 1988-10-12 1989-06-21 Datendemodulatorschaltung fuer einen radiodatensystemempfaenger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63256432A JP2752388B2 (ja) 1988-10-12 1988-10-12 Ｒｄｓ受信機におけるデータ復調回路

Publications (2)

Publication Number Publication Date
JPH02104041A JPH02104041A (ja) 1990-04-17
JP2752388B2 true JP2752388B2 (ja) 1998-05-18

Family

ID=17292579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63256432A Expired - Fee Related JP2752388B2 (ja) 1988-10-12 1988-10-12 Ｒｄｓ受信機におけるデータ復調回路

Country Status (2)

Country Link
JP (1) JP2752388B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3920330A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2677195B1 (fr) * 1991-06-03 1994-10-07 Telediffusion Fse Procede de demodulation de signaux rds par voie numerique, et demodulateur mettant en óoeuvre ce procede.
DE4205014C2 (de) * 1992-02-19 1995-04-13 Blaupunkt Werke Gmbh Demodulator für Radio-Daten-Signale
EP1158706A1 (en) * 2000-05-23 2001-11-28 Sony International (Europe) GmbH RDS decoder for reducing the influence of noise peaks using a noise blanker

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2197554B (en) * 1986-09-30 1991-06-05 Pioneer Electronic Corp Fm multiplex broadcast receiver
JPS6387836A (ja) * 1986-09-30 1988-04-19 Pioneer Electronic Corp Ｆｍ多重放送受信機におけるデ−タ復調回路
JPS6387039A (ja) * 1986-09-30 1988-04-18 Pioneer Electronic Corp デイジタルｐｌｌ回路のロツク検出回路

Also Published As

Publication number Publication date
JPH02104041A (ja) 1990-04-17
DE3920330A1 (de) 1990-04-19
DE3920330C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-03-11

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Legal Events

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LAPS Cancellation because of no payment of annual fees