JP2744378B2 - Driving method of charge-coupled device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transversal filter (delay line filter) using a floating gate amplifier (FGA) type charge-coupled device (hereinafter referred to as a CCD), a solid-state imaging device, and the like. The present invention relates to a method for driving the CCD.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in Japanese Utility Model Laid-Open No. 60-137455 (Document 1). As one of signal detection methods in CCD, FG described in the above-mentioned document 1 is used.
There is A method. The FGA method uses a floating MOS
This method detects the potential change of the MOS gate that occurs when a signal charge is injected into a capacitor under the gate. Since the signal charge can be read nondestructively, the signal once detected can be used again. Have. One configuration example is shown in FIGS. FIG.
FIG. 1C is an explanatory view of a conventional FGA type CCD described in the above-mentioned Document 1, and FIG. This CCD is a buried channel type CC
D. A shield gate (SG) 4 to which a DC gate voltage V _SG is applied via a gate insulating film 3 on an N-type impurity layer 2 formed on the P-type semiconductor substrate 1;
The signal charges e ^- a floating gate for detecting a (F
G) 5 and signal charges e from the floating gate 5
^- first transferring the clock pulses phi _P 1, a second transfer gate (TG) 6, 7, and a shield gate (SG) 8 to the gate voltage V _SG is applied, the signal charges e ^- transfer direction (From left to right in FIG. 2A). The gate voltage V _SG is usually constant.

The floating gate 5 and the second transfer gate 7 are composed of a first-layer MOS gate electrode, and the shield gates 4 and 8 and the first transfer gate 6 are formed of a second-layer MOS gate electrode.
The first and second layers are composed of OS electrode gates, and the first and second layers overlap each other to form a gate structure. The floating gate 5, on the reset pulse phi _R, via a reset transistor 10 consisting of MOS transistors for turning off operation with a reference potential V _R is connected, an output signal OUT by amplifying the output of the floating gate 5 The output amplifier 11 is connected. FIG. 2 (b)
FIG. 3 is a diagram showing a channel potential state under each gate in FIG. The solid line in the figure is a potential state indicating the transfer state of the signal charge e ⁻ below the floating gate 5 at time t ₁ . The broken line in the drawing is a potential state indicating the injection and transfer of the signal charge e ⁻ below the floating gate 5 at time t ₂ . FIG. 2C shows the reset pulse φ _R and the clock pulse φ.
FIG. 6 is a drive timing chart of _P. The driving method of the CCD will be described with reference to these drawings. Time t in FIG. 2 (c)
In _1, when the clock pulse phi _P is "H" level, the reset pulse phi _R "L" level, first, the second transfer gate 6, a floating gate 5 under the signal charges e ^- signal charge Transfer direction (right direction in FIG. 2A)
Sent to Then, when the reset pulse phi _R becomes "H" level, the reset transistor 10 is turned on, the reference voltage V _R is applied to the floating gate 5. As a result, the DC level of floating gate 5 is maintained at a constant reset potential. Then, reset pulse φ _R
Becomes "L" level, the reset transistor 10 turns off, and the floating gate 5 enters a floating state.

At time t ₂ in FIG. 2C, when the clock pulse φ _P shifts to the “L” level, the transfer charge e ⁻ sent from the left in FIG. The data is transferred below the floating gate 5. Here, since the DC gate voltage V _SG is applied to the shield gate 4, a potential barrier is formed below the shield gate 4, and the backflow of the signal charge e ⁻ transferred below the floating gate 5 is prevented. You. When the signal charge e ⁻ is transferred below the floating gate 5, the MOS capacitance between the floating gate 5 and the N-type impurity layer 2 changes, and the potential of the floating gate 5 changes.
This potential variation is amplified by the amplifier 11 and output signal O
Output in the form of UT. The signal detector of this type of CCD, before the charge detection by the floating gate 5, the reference potential V _R is reset is applied to the floating gate 5 through the reset transistor 10. Therefore, the DC level of the floating gate 5 is kept constant, and the signal charge e ⁻ can be detected.

[0005]

However, the conventional driving method has the following problems. In FIG. 2C, the clock pulse φ _P changes from “H” level to “L”.
When the level shifts to the level, since the reset transistor 10 is off, the floating gate 15 is in a high impedance state. Therefore, the first layer MOS
Due to the capacitive coupling between the floating gate 5 composed of the gate electrode and the first transfer gate 6 composed of the second-layer MOS gate electrode, the reset potential of the floating gate 5 is reduced by the influence of pulse noise from the transfer gate 6. it may change from the reference potential V _R to another potential.
When shaking of such potential occurs, the floating gate 5 variation in the channel potential under occurs, the signal charges e ^- detection and create an obstacle to the transfer of the, there is a problem that malfunction.

In order to solve such a problem, in the conventional method, a control gate is provided on both sides of the floating gate 5 so as to partially overlap the floating gate 5, and during the signal charge transfer,
A control signal is supplied to the control gate to induce charges of the same amount and different sign in the floating gate 5. However, in such a method, the timing of supplying signals to the control gate is complicated, and a simple driving method is used.
It has been difficult to accurately prevent the adverse effects of pulse noise due to capacitive coupling. An object of the present invention is to solve the problem of the prior art, which is a problem in that it is difficult to detect signal charges and prevent deterioration of transfer accuracy due to the influence of pulse noise with relatively simple gate control. It provides a method.

[0007]

According to the present invention, a floating gate, a first transfer gate adjacent to the floating gate, and a first transfer gate adjacent to the floating gate are provided on a surface of a semiconductor substrate via a gate insulating film. In the FGA type CCD in which a second transfer gate adjacent to the first transfer gate is formed, and a potential change caused by a signal charge transferred under the floating gate is detected by the floating, the following means are taken. . That is, while the first clock pulse of “H” level is applied to the first transfer gate and the second clock pulse of “H” level is applied to the second transfer gate, the reset pulse causes After resetting the floating gate to a constant potential, the first clock pulse falls from "H" level to "L" level. Then, after the reset pulse is turned off, the second clock pulse is set to “H”.
It falls from the level to the “L” level.

[0008]

According to the present invention, the CCD driving method is configured as described above. When the floating gate is reset to a constant potential by a reset pulse, the floating gate has a low (low) impedance. Therefore, when the first transfer gate adjacent to the floating gate falls from the “H” level to the “L” level during this reset period, the first transfer gate is coupled via the capacitive coupling between the floating gate and the first transfer gate. Leakage of charge from the first transfer gate to the floating gate is prevented.

Next, after the reset pulse is turned off and the reset is completed, the second clock pulse falls from the "H" level to the "L" level, and at this time, the first clock pulse is already at the "L" level. Since the level is at the level, the influence of pulse noise via capacitive coupling from the first and second transfer gates to the floating gate is cut off. Therefore, the above problem can be solved.

[0010]

1A to 1C are views for explaining an FGA type CCD showing an embodiment of the present invention, and FIG.
Elements common to those in the middle are denoted by common reference numerals.
FIG. 1A is a cross-sectional view of a signal detection unit of a CCD. This CCD has the same structure as that of the conventional CCD shown in FIG. 2A. A first clock pulse φ _1P is applied to a first transfer gate 6 and a second clock pulse is applied to a second transfer gate 7. The only difference is that _φ2P is applied. FIG. 1B is a diagram showing a state of a channel potential formed below each gate in FIG. 1A. The solid line in FIG. 1 (b) shows the state of the potential distribution at time t _11,
Furthermore a broken line indicates the state of the potential distribution at time t ₁₂ after time t _11. FIG. 1C is an operation timing chart of the reset pulse φ _R and the first and second clock pulses φ _1P and φ _2P . In the figure, t _a is the falling time of the first clock pulse φ _1P , and t _b is the reset pulse φ
The falling time of _R , t _c is the first clock pulse φ _1P
Is the rising time. T1 is a reset period,
T2 is a signal detection period. Referring to these figures,
A CCD driving method according to the present embodiment will be described. FIG.
At time t ₁₁ of (c), the reset pulse phi _R is "L" level, and the first and second clock pulses phi _1P, phi because _2P is at the "H" level, the floating gate 5 under the signal charges e ^- Is transferred below the first and second transfer gates 6 and 7. When the reset pulse phi _R becomes "H" level, the reset period T1, and the reset transistor 10 is turned on, the reference voltage V _R is applied to the floating gate 5, the floating gate 5 is set to a constant reset potential.

[0011] At time t _a, and falls to the "L" level from the first clock pulse φ _1P is at the "H" level,
The signal charge e ⁻ under the first transfer gate 6 is transferred to the second transfer gate 7. At this time, the reset transistor 1
0 has a reset period T1 in the ON state, since the floating gate 5 is low impedance, the floating gate 5 is not affected by the pulse noise from the first transfer gate phi _1P adjacent. Then, at time t _b
When the reset pulse phi _R becomes "L" level in,
The reset transistor 10 is turned off and the reset period T1
End, and the floating gate 5 enters a floating state. At time t ₁₂ of FIG. 1 (c), becomes a second clock pulses phi _2P is fallen to "L" level from "H" level signal detection period T2, shielded gate 4
The signal charge e ⁻ on the side is transferred to below the floating gate 5. Then, the MOS capacitance between floating gate 5 and N-type impurity layer 2 changes, and the potential of floating gate 5 fluctuates.
The signal is amplified by 1 and output as an output signal OUT. In the fall time of the second clock pulses phi _2P time t _12, since the first clock pulse phi _1P is already a "L" level, the floating gate 5, a first transfer gate adjacent thereto 6 And the influence of pulse noise from the second transfer gate 7.

At time t _c , when the first clock pulse φ _1P rises to the “H” level, the signal charge e ⁻ under the floating gate 5 is transferred to below the first transfer gate 6. Then, when the second clock pulse φ _2P rises to “H” level, the signal charge e under the first transfer gate 6
^- is transferred to the second transfer gate 7 below, "H" gate voltage V _SG of the levels are transferred via the lower shield gate 8 applied to the next stage.

As described above, in this embodiment, the first clock pulse φ _1P falls from “H” level to “L” level during the reset period T1 of the floating gate 5, so that the floating gate 5 is low. It is impedance and is not affected by pulse noise from the first transfer gate 6. After the reset period T1, the second clock pulse φ _2P is changed from “H” level to “L”.
Fall to the level. At this time, since the first clock pulse φ _1P is already at the “L” level, the floating gate 5 is not affected by pulse noise from the first transfer gate 6 and the second transfer gate 7.

Therefore, the reset potential of the floating gate 5 does not change from the reference potential V _R to another potential, and the fluctuation of the channel potential below the floating gate 5 can be suppressed, thereby detecting the signal charge e ⁻ and Transfer accuracy can be improved. Moreover, in this embodiment, since the first and second clock pulses φ _1P and φ _2P are only applied to the first and second transfer gates 6 and 7 with their timings shifted, the gate control of these gates is simplified. Can be done. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, the N-type impurity layer 2 under each gate
If an N ⁻ -type impurity layer having a concentration lower than that of the N-type impurity layer 2 is formed therein, the N ⁻ -type impurity layer forms a potential barrier that determines the transfer direction of the signal charge e ⁻ , and is formed by a small number of clock pulses. signal charges e ^- can be performed in the transfer. further,
The P-type semiconductor substrate 1 and the N-type impurity layer 2 may be changed to another material or structure.

[0015]

As described above in detail, according to the present invention, the first clock pulse falls to the "L" level after the floating gate is reset to a constant potential by the reset pulse. The floating gate is not affected by pulse noise from the first transfer gate because of the low impedance. Further, after the reset pulse is turned off, the second clock pulse is caused to fall to the "L" level. At this time, the first clock pulse is at the "L" level. It is not affected by pulse noise from the second transfer gate. Therefore, the reset potential of the floating gate does not change, and the fluctuation of the channel potential below the floating gate can be suppressed. Therefore, the first and second gates can be controlled by relatively simple gate control.
The effect of pulse noise from the transfer gate to the floating gate can be prevented, and the detection and transfer accuracy of signal charges can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an FGA type CCD showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a conventional FGA type CCD.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 N-type impurity layer 3 Gate insulating film 4, 8 Shield gate 5 Floating gate 6, 7 First and second transfer gate 10 Reset transistor 11 Amplifier V _SG gate voltage φ _1P , φ _2P First, Second clock pulse φ _R reset pulse

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/30-5/335 H01L 29/76

Claims (1)

(57) [Claims] A floating gate, a first transfer gate adjacent to the floating gate, and a second transfer gate adjacent to the first transfer gate formed on a surface of the semiconductor substrate via a gate insulating film; In a floating gate detection type charge-coupled device for detecting a potential change caused by a signal charge transferred under a floating gate by floating, a first clock pulse of "H" level is applied to the first transfer gate. With the second clock pulse of “H” level applied to the second transfer gate, the first clock pulse is changed from “H” level to “L” after resetting the floating gate to a constant potential by a reset pulse. Level, and after the reset pulse is turned off, the second clock The driving method of the charge-coupled device, characterized in that fall to the "L" level pulse from the "H" level.