JP2697647B2 - Recording signal compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is applied to a circuit for supplying binary recording data to a magnetic recording medium or other recording medium. The present invention is used as a circuit for compensating and adjusting the peak shift of the recording data waveform. The present invention relates to a compensation circuit having a simple circuit configuration capable of adjusting and setting a peak shift compensation value in accordance with the properties of incoming recording data and the properties of a recording device connected to an output.

[0002]

2. Description of the Related Art When binary recording data is recorded on a moving magnetic recording medium using a fixed magnetic head, the binary recording data supplied to the magnetic head and the recording data read from the recording medium are read out. It is known that there is a shift in the signal waveform between the binary read data and the binary read data. Conventionally, to prevent an information error from occurring between the recording data and the reading data due to the deviation of the signal waveform,
Various circuits for compensating a signal waveform of recording data during recording have been used. This became more severe as the recording density of the magnetic recording medium increased, and the compensation circuit became complicated and sophisticated.

Generally, when performing high-density recording in a magnetic disk device or the like, a phenomenon occurs in which the immediately following edge position shifts due to a demagnetizing field from a mark recorded on the medium immediately before. That is, as shown in FIG. 8, the magnetic head 9 moves from left to right on the medium 10 while generating a magnetic field Hc proportional to the recording current. In a region where the magnetic field applied to the medium is sufficiently strong, the magnetization on the medium is saturated, and the residual magnetization Ms remains even after the magnetic field from the magnetic head 9 disappears. However, in the magnetization transition region, the magnetic field generated by the magnetic head 9 temporarily becomes weak while the recording current is reversed.
On the medium, in addition to the current magnetic field Hc generated from the magnetic head 9, a Coulomb magnetic field Hm generated by the magnetic charge -Q in the previously recorded area is also applied. As the previously recorded magnetization transition is closer, the magnetic field intensity near the magnetic head 9 is weakened, so that the next magnetization transition appears earlier.

[0004]

Due to this effect, the peak position of the reproduced signal deviates from an ideal point. Other peak position shifts may occur due to intersymbol interference due to the proximity of isolated reproduction pulses. The peak shift caused by such a linear action of superposition can be easily reduced by using an equalizer. On the other hand, the shift of the magnetization transition region caused by the influence of the demagnetizing field is difficult to compensate for by linear equalization during reproduction because of the nonlinear peak shift that occurs during the saturation recording process.

To compensate for this effect, a method of shifting the edge position of the recording current in a direction opposite to the nonlinear shift direction expected in advance is used. Conventionally, as shown in FIG. 7, an edge position of a recording signal is controlled by giving a delay amount set based on data recorded immediately before to a programmable delay line. The shift register 6 shown in FIG. 7 holds three bits of data recorded immediately before. The delay amount decoder 7 outputs a delay amount determined according to a 3-bit pattern as a delay amount control signal. In the programmable delay line 8, the recording data is delayed and output by the delay amount given by the control signal.

Such a circuit configuration has a high degree of freedom regarding the set value of the delay amount, but has a disadvantage that the programmable delay line is expensive and the circuit scale becomes large.

The present invention has been made in view of such a background, and an object of the present invention is to provide a circuit configuration capable of effectively reducing a nonlinear peak shift with an inexpensive and simple configuration. SUMMARY OF THE INVENTION It is an object of the present invention to provide a recording signal compensating circuit capable of adjusting and setting a peak shift compensation value in accordance with the characteristics of incoming recording data and the characteristics of a recording device connected to an output.

[0008]

According to the present invention, a binary signal given as recording data is given a different slew rate,
An edge of the recording signal is generated by comparing the magnitude of the output.

That is, according to the present invention, there is provided a recording signal compensating circuit for compensating and adjusting a peak shift of a binary recording data waveform supplied to a recording medium, wherein two characteristics of a binary signal given as recording data to the recording medium pass. And a comparison circuit for comparing the outputs of the two waveform shaping circuits. It is preferable that the inputs of the two waveform shaping circuits are branched and connected to a signal path of the recording data. The two waveform shaping circuits may be connected in cascade to the signal path of the recording data, and the comparison circuit may be connected to each output of the two waveform shaping circuits. It is preferable to include a bias circuit configured by a CR circuit having a configuration and to supply a bias voltage to the two waveform shaping circuits. Further, the CR circuit includes a resistor divider circuit and a part of the resistor divider circuit. A configuration in which a capacitor is connected in parallel to a resistor, wherein at least a part of the capacitor of the CR circuit is a variable capacitance diode, including a circuit that supplies a control voltage to the variable capacitance diode, adjusts the control voltage It is desirable to include a circuit.

[0010]

The waveform shaping circuit, which is branched or cascade-connected to the signal path and gives two different slew rates with different characteristics, passes the binary signal given as the recording data to the recording medium, and the comparison circuit compares the two outputs. The edge of the recording signal is generated by comparison.

That is, by slightly changing the slew rate of the two waveform shaping circuits, that is, the time constant or the amplitude constant, the edge of the signal waveform appearing in the comparison circuit for comparing the outputs of the two waveform shaping circuits is obtained. It can be shifted forward or backward. Since this configuration can be realized by an extremely small number of elements using an analog circuit, the circuit configuration is simplified as compared with a conventional configuration using a delay decoder and other digital circuits.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the basic circuit configuration of the embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the basic circuit in the embodiment of the present invention.

The basic circuit of the embodiment of the present invention includes a buffer 1 for temporarily holding recording data, a waveform shaping circuit 2 having two characteristics, each of which passes a binary signal given as recording data to a recording medium. Two waveform shaping circuits 2
And a comparison circuit 3 for comparing outputs of the two waveform shaping circuits 2. Inputs of the two waveform shaping circuits 2 are branched and connected to a signal path of the recording data.

Binary data is input to the buffer 1 at equal bit intervals tb as recording data. The output signal V ₀ of the buffer 1 is input to the waveform shaping circuits 2 having different slew rates SR ₁ and SR ₂ and output as V ₁ and V ₂ . The relationship between V ₀ , V ₁ , and V ₂ is as shown in FIG.
The slew rate (SR ₁ ) of V ₁ is set so that the rise time is shorter than the bit interval tb,
The voltage always swings to the maximum amplitude. On the other hand, V ₂ of the slew rate (SR _2), because they are smaller than that of V _1, in particular where a short code inversion interval before the amplitude reaches the maximum value, starts changing in the opposite direction .

The comparison circuit 3 outputs a binary recording signal V _R according to the difference between V ₁ and V ₂ . Output recording signal V
_R takes a binary value according to the sign of V ₁ −V ₂ . V ₁
When the amplitude is set larger than the amplitude of V _2, the sign inversion interval is long area, V _R takes almost the same value as V _0. However, when the sign inversion interval is short, the effect of V ₂ varies in the opposite direction before taking a maximum amplitude, so that the edge of the recording signal is shifted to the rear. Since the shift amount td changes depending on the slew rate and the amplitudes of V ₁ and V ₂ ,
By setting these appropriately, it can be used for recording compensation.

The recording data is given by rectangular waves having equal bit intervals. Output V _{1 of one} waveform shaping circuit 2
Has a slightly shorter rise time than the bit interval,
A trapezoidal voltage change is performed. If the rise time of the output V ₂ of the other of the waveform shaping circuit 2 is set to be longer than the bit interval, in code inversion interval is short region, V ₂
Begins to change in the opposite direction before reaches the maximum amplitude. Therefore, if the sign change appears in succession, the threshold V ₂ Gazure for V _1, the edge of the recording signal is shifted to the rear.

That is, in the circuit configuration of the present invention, the polarity of the recording signal is switched according to the magnitude of the outputs V ₁ and V ₂ of the two waveform shaping circuits 2. The rise time of V _1,
If you choose shorter fall time for the bit interval tb of recording data, V ₁ is not affected so much in the past recorded data pattern, it varies substantially with a constant voltage amplitude.

On the other hand, when the slew rate of V ₂ is selected to be relatively small, the potential is affected by the previous recording data pattern. For example, if there is a falling immediately before, V ₂ will be starts to rise before the swing completely negative. The amplitude of V ₂ is set to be smaller than that of V _1, when considered as a threshold for V _1, it will act as raised the threshold voltage V ₂ to the influence of the falling edge of the immediately preceding. The edge of the recording signal is V
Delay by the time determined by the slew rate of ₁ . As a result, a binary voltage signal given as recording data is input to the two waveform shaping circuits 2 giving different slew rates, and the magnitudes of the outputs of the two are compared to generate an edge of the recording signal. The non-linear peak shift of the recording data can be effectively adjusted by an inexpensive and simple configuration.

(First Embodiment) FIG. 3 is a diagram showing a circuit configuration of a first embodiment of the present invention, and FIG. 4 is a diagram for explaining an operation in the first embodiment of the present invention.

In the first embodiment of the present invention, the waveform shaping circuit has R,
A first waveform shaping circuit 11 and a second waveform shaping circuit 12, which are realized by a C network and have the same configuration but different circuit time constants, and a bias is applied to the two waveform shaping circuits 11 and 12. The CR circuit includes a bias circuit 4 that supplies a voltage. The CR circuit includes a resistor voltage divider circuit and a capacitor connected to a part of the resistors of the resistor voltage divider circuit.

The bias circuit 4 outputs a constant potential V _BB which corresponds to the midpoint of the amplitude of the recorded data. The output potentials V ₁ and V ₂ of the slew rate limiting circuit are

[0022]

(Equation 1) It is expressed as Here, the amplitudes A1 and A2 of V ₁ and V ₂ are

[0023]

(Equation 2) The time constants τ1 and τ2 are

[0024]

(Equation 3) Given by Since the amplitudes A1 and A2 are determined by the ratio of the resistances, and the time constants τ1 and τ2 are proportional to the parallel resistance, they can be arbitrarily selected. FIG. 4 shows an output example corresponding to the change of V ₀ . If there is an edge immediately before, it is understood that the following edge is delayed.

(Second Embodiment) FIG. 5 is a diagram showing a circuit configuration of a second embodiment of the present invention. In the second embodiment of the present invention, a constant slew rate buffer 5 is used as a voltage buffer having a limited slew rate, which serves as a first waveform shaping circuit 13, and a CR circuit constitutes a second waveform shaping circuit 14. The two waveform shaping circuits are cascaded to the signal path of the recording data, and the comparison circuit 3 is connected to each output of the two waveform shaping circuits.

The output V ₁ of the constant slew rate buffer 5 is
Like the output signal of the waveform shaping circuit shown in FIG. 2, it is set to have a rise time shorter than the bit interval tb. On the other hand, the RC circuit connected to the bias circuit 4
The output voltage V ₂ from the network has a slew rate lower than V ₁ , and the amplitude takes a value determined by the resistance r and the voltage division ratio by R. The output of the comparison circuit 3 in this case is also
As in the first embodiment, when the edges of the recording data are continuous, the effect of shifting the subsequent edge backward can be obtained.

The signal that has passed through the second waveform shaping circuit 14 is
Since the signal that has passed through the first waveform shaping circuit 13 is further subjected to waveform shaping by the resistance elements r, R, and the capacitance element C, the two inputs of the comparison circuit 3 have waveform shaping circuits having substantially different characteristics. Will be given.

(Third Embodiment) FIG. 6 is a diagram showing a circuit configuration of a third embodiment of the present invention. In the third embodiment of the present invention, the first waveform shaping circuit 15 and the second waveform shaping circuit 16 are configured using a resistor and a variable capacitance diode so that the setting of the shift amount can be adjusted. And a bias circuit 4 for supplying a bias voltage to the two waveform shaping circuits. The CR circuit includes a resistance voltage dividing circuit and a resistance voltage dividing circuit. A capacitor is connected in parallel to some of the resistors, and at least some of the capacitors in the CR circuit are variable capacitance diodes, and include a circuit for supplying a control voltage to the variable capacitance diode, and a circuit for adjusting the control voltage. .

The resistor likewise divides the output voltage of the buffer 1 and the bias voltage V _BB and the first embodiment shown in FIG. The variable capacitance diodes D ₁ and D ₂ are reverse-biased to V _B1 and V _B2 by the voltage buffer, respectively. At this time, the bias potentials V _B1 and V _B2 can be adjusted by the variable resistors V _R1 and V _R2 , and the optimum value within the range determined from the values of V _B1 and V _B2 as the delay amount according to the recording data pattern. Can be selected.

The adjustment values of the voltages V _B1 and V _B2 are prepared in a setting map in accordance with the type of the source of the incoming recording data and the type of the recording medium in which the output is used, and are connected to the preceding and succeeding stages. The adjustment value can be set adaptively according to the type of the device.

[0031]

As described above, according to the present invention, the peak shift compensation value can be adjusted and set in accordance with the characteristics of the recording data to arrive and the characteristics of the recording device connected to the output. As a result, the nonlinear peak shift of the recording data can be effectively compensated with an inexpensive and simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of a basic circuit in an embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of the first embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation in the first embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a third embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a conventional example.

FIG. 8 is a diagram illustrating a process of generating a nonlinear peak shift.

[Explanation of symbols]

 Reference Signs List 1 buffer 2 waveform shaping circuit 3 comparison circuit 4 bias circuit 5 constant slew rate buffer 6 shift register 7 delay amount decoder 8 programmable delay line 9 magnetic head 10 medium 11, 13, 15 first waveform shaping circuit 12, 14, 16 second Waveform shaping circuit

Claims (8)

(57) [Claims] 1. Two different slew rates through which a binary signal given as recording data to a recording medium passes.
A recording signal compensating circuit comprising: a waveform shaping circuit having characteristics; and a comparing circuit for comparing outputs of the two waveform shaping circuits. 2. The recording signal compensating circuit according to claim 1, wherein inputs of said two waveform shaping circuits are branched and connected to a signal path of said recording data. 3. The recording signal compensating circuit according to claim 1, wherein said two waveform shaping circuits are connected in cascade to a signal path of said recording data, and said comparison circuit is connected to each output of said two waveform shaping circuits. 4. The recording signal compensating circuit according to claim 1, wherein said two waveform shaping circuits are constituted by CR circuits of the same configuration having different circuit time constants. 5. The recording signal compensating circuit according to claim 1, further comprising a bias circuit for supplying a bias voltage to said two waveform shaping circuits. 6. The recording signal compensating circuit according to claim 4, wherein said CR circuit has a configuration in which a resistor voltage dividing circuit and a capacitor are connected in parallel to a part of the resistors of said resistor voltage dividing circuit. 7. The recording signal compensating circuit according to claim 4, wherein at least a part of the capacitor of the CR circuit is a variable capacitance diode, and further comprises a circuit for supplying a control voltage to the variable capacitance diode. 8. The recording signal compensation circuit according to claim 7, further comprising a circuit for adjusting the control voltage.