JP2689807B2 - Information signal recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information signal recording / reproducing apparatus for recording / reproducing data.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIG. In FIG. 9, reference numeral 1 is a recording code generation device that performs optimum encoding for recording, and includes a high efficiency encoder 2 and a channel encoder 3, 5 is a recording amplifier , 6 is a reproduction amplifier , 9
Is a reproduction information decoding device, which includes a channel code decoder 10 and a high efficiency code decoder 11. The operation of the conventional information signal recording / reproducing apparatus configured as described above will be described below.

The image data is subjected to data compression by the high-efficiency encoder 2, and subsequently, by the communication channel encoder 3.
A parity bit for error correction is added, block formation is performed, a sync signal and an identification signal (ID) are added for each block, and the block is transmitted to the recording amplifier 5. A block to which a sync signal and an identification signal (ID) are added is called a sync block. At this time, if the method of data compression in the high-efficiency encoder 2 is intra-frame encoding, the image can be reproduced even during high-speed reproduction, and there is no problem.

[0004]

However, if the method of data compression in the high-efficiency encoder 2 includes not only intra-frame coding but also prediction inter-frame coding, prediction is performed during high-speed reproduction. There has been a problem that it is impossible to reproduce all the data of a non-existing frame, and it is impossible to reproduce a correct image.

In view of the above points, the present invention has an object of providing an information signal recording / reproducing apparatus capable of intermittently reproducing at least one frame of data during high-speed reproduction in an apparatus for recording / reproducing on a tape-shaped medium. .

[0006]

In order to achieve the above object, the information signal recording / reproducing apparatus of the present invention reproduces all the data of frames which are not predicted during high speed reproduction.
The data recording pattern converter that records the data of the frame that does not perform prediction in the part that the playback head passes during high-speed playback, and the data of the frame that does not perform prediction of the data that was played during normal playback first Output
Continuing, a data recording pattern inverse converter that outputs data by predictive interframe coding is connected to the reproduction amplifier and the above-described data recording pattern inverse converter during normal reproduction, and during high speed reproduction, a reproduction amplifier and a reproduction information decoding device. And a change-over switch for connecting to.

[0007]

According to the present invention, with the above configuration, even when the data compression method includes not only intra-frame coding but also prediction inter-frame coding, all the data of the frames that are not predicted during high-speed reproduction are reproduced. The image can be played back.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An information signal recording / reproducing apparatus according to a first embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, 4, 5, and 6.
This will be described with reference to FIG. 1 is a block diagram of a signal processing unit of an information signal recording / reproducing apparatus according to a first embodiment of the present invention,
FIG. 2 is a recording pattern diagram when recording is performed on a recording medium by using the information signal recording / reproducing apparatus according to the first embodiment of the present invention, and FIG. 3 is an information signal recording / reproducing apparatus according to the first embodiment of the present invention. 4 is a block diagram of the data recording pattern converter in FIG. 4, FIG. 4 is a block diagram of the data recording pattern inverse converter of the information signal recording / reproducing apparatus in the first embodiment of the present invention, and FIG. 5 is a time axis direction differential compression diagram of image data. FIG. 6 is a recording data array diagram.

In FIG. 1, reference numeral 1 is a recording code generating device for performing an optimum encoding for recording, which comprises a high efficiency encoder 2 and a channel encoder 3. Reference numeral 4 is a data recording pattern converter, 5 is a recording amplifier, 6 is a reproduction amplifier, 7 is a changeover switch, 8 is a data recording pattern inverse converter, 9 is a reproduction information decoding device, which is a channel code decoder 10 and a high efficiency code. A decoder 11 is provided. In FIG. 2, a to z, a ′,
b'is a recording track. In FIG. 3, 21 is an address adder, 22 is a two-dimensional array storage circuit, and 23 is an array control circuit. In FIG. 4, 31 is a two-dimensional array storage circuit, 32 is an address remover, and 33 is an array control circuit. In FIG. 5, S00 to S0n and S10 are image data of one frame, I indicates intraframe coding, and U indicates predicted interframe coding.

The operation of the information signal recording / reproducing apparatus configured as described above will be described below. To facilitate understanding, the present embodiment will be described by taking as an example the case where 6 × speed special reproduction is possible. In FIG. 1, by the high efficiency encoder 2, for the image S00,
The intra-frame coding is performed, and the images S01 to S0n are subjected to predictive inter-frame coding for performing prediction from the frame immediately preceding in time, and are transmitted to the channel encoder 3. At this time, S00 is called a refresh image. The communication channel encoder 3 adds an error correction parity bit to the image data encoded by the high efficiency encoder 2 to form a block, and a sync signal and an identification signal (ID) for each block. ) Is added and transmitted to the data recording pattern converter 4. A block to which a sync signal and an identification signal (ID) are added is called a sync block. At this time, the refresh image of S00 is divided into 10 blocks, which are designated as B1 to B10. Similarly, the refresh image of S10 is changed to C1 to C.
Suppose it is divided into 10 blocks.

In the conventional recording / reproducing apparatus, since the data recording pattern converter 4 is not provided, the data is recorded on the medium through the recording amplifier 5 at the position of the track a in FIG. However, in this embodiment, since the data recording pattern converter 4 is provided, B2 to B1
The recording pattern is converted so that 0 can be recorded at the positions B′2 to B′10, and the recording pattern is recorded on the tape-shaped medium through the recording amplifier 5 and the magnetic head. Also,
The blocks of the encoded data of the images of S01 to S0n are converted into recording patterns so that they can be recorded at positions D1, D2, ..., Dm in FIG. 2 in sequence, and are recorded on the medium through the recording amplifier 5. It Similarly, C2
The block of C10 is passed through the recording amplifier 5 to C2 'to C
Record at medium position 10 '. Now, the data recording pattern converter 4 for generating such a recording data structure will be described with reference to FIG.

The data sent from the recording code generator 1 is input to the address adder 21. The address adder 21 adds an address indicating from which frame each sync block is encoded to each sync block, and adds a search pilot signal to the first sync block of the refresh image such as B1 and C1. Add 2
It is transmitted to the dimensional array storage circuit 22. The two-dimensional array storage circuit 22 arranges the sync blocks two-dimensionally based on the control signal of the array control circuit 23. Two-dimensional array storage circuit 22
Is a memory circuit having an array number as shown in FIG. That is, a matrix of l rows and m columns (here, l
= 10, m = 6), the column number is 0 at the left end, and the number is incremented by 1 for each column, and the row number is 0 at the bottom row and incremented by 1 for each row. Is.

An array control method of the array control circuit 23 will be described with reference to FIG. In the array control circuit 23, an array of (0, 0) is given to B1, and an array of (0, 0) is given to B2.
Given an array of (1,1), for B3, (1,2)
2 is given to B4, and the sequence of (2, 3) is given to B4, so that B2 to B10 are sequentially arranged at positions B'2 to B'10 of FIG. The sequences in FIG. 6 corresponding to the positions of '2-B'10 are given. Also, S01-
Blocks of encoded data of images up to S0n are sequentially shown in FIG.
, Dm, the array in FIG. 6 corresponding to the positions of D1, D2, ..., Dm is given. That is, the array control circuit 23
Outputs a control signal for refreshing images so that they can be reproduced by the head even when the head scanning locus changes during high-speed reproduction, and for other images so as to be reproduced in chronological order. And
(0,0), (0,1), ..., (0,9), ...
, (6, 9) are sequentially transmitted from the two-dimensional array storage circuit 22 to the recording amplifier 5 and recorded on the medium.

Next, the time of reproduction will be described. First, the normal reproduction will be described. During normal reproduction, the head sequentially reproduces recording tracks a to z, a ', b', and transmits them to the reproduction amplifier 6. The switch 7 is a device that connects the reproduction amplifier 6 and the data recording pattern inverse converter 8 for normal reproduction, and directly connects the reproduction amplifier 6 and reproduction information decoding device 9 for high-speed search reproduction. During normal reproduction, the switch 7 connects the reproduction amplifier 6 and the data recording pattern inverse converter 8. The reproduction amplifier 6 is a track a
Through z are sequentially reproduced, and the reproduced sync blocks are sent to the data recording pattern inverse converter 8.

The operation of the data recording pattern inverse converter 8 will be described with reference to FIG. The reproduced sync block sent from the reproduction amplifier 6 is the array control circuit 33.
It is stored in the two-dimensional array storage circuit 31 according to the control signal from. At this time, the pattern stored in the two-dimensional array storage circuit 31 is the same as that of the two-dimensional array storage circuit 22. Further, the array control circuit 33 outputs a control signal for sequentially storing the reproduced sync blocks from the reproduction amplifier 6 in the two-dimensional array storage circuit 31, and then S00, S01, ...
Output a control signal for transmitting the reproduced sync blocks from the two-dimensional array storage circuit 31 to the address remover 32 so that the frames can be reproduced sequentially.

That is, B1, B2 ', ... In FIG.
.., B10 ', D1, D2, ..., Dm are arranged so that the reproduced sync blocks arranged in order are transmitted from the two-dimensional array storage circuit 31 to the address remover 32. The control circuit 33 outputs. That is, the data is (0,0), (1,1), (1,2),
(2,3), ..., (5,9), (0,1), ...
2 in the order of (0,9), (1,0), ..., (5,8)
A control signal for transmission to the address remover 32 is output from the dimensional array storage circuit 31. Then, the address remover 32 removes the address added by the address adder 21 and transmits the reproduced sync block to the reproduction information decoding device 9. In the reproduction information decoding device 9, the image signal code decoder 10 and the high-efficiency code decoder 11 decode the reproduced sync block data.

Next, the case of 6 × speed special reproduction will be described. In this case, the reproduction amplifier 6 and the reproduction information decoding device 9 are directly connected by the switch 7. Then, reproduction is performed at a normal speed until the search pilot signal is recognized, and if the search pilot signal is recognized, a high speed search is performed. Therefore, in the case of high-speed search, the reproduced sync blocks input to the reproduction amplifier 6 are B1, B2 ', ..., B.
9 ', C1, C2', ..., C10 'S00, S1
There are only 0, ... Refresh images. Then, these are decoded by the reproduction information decoding device 9 to be reproduced images. At this time, since the reproduced images are intermittent in the reproduced frames, an image in a state like frame advance is reproduced. By adopting the above-mentioned configuration, it is possible to obtain the effect of enabling high-speed search even when encoding is performed using interframe prediction.

In the present embodiment, the case of 6 × speed is shown, but it goes without saying that high speed reproduction at other speeds can be realized by changing the arrangement method. Further, in the present embodiment, the case where the predictive interframe coding is temporally sequentially described has been described, but it goes without saying that it is also possible in the case of other interframe prediction. Further, when the high-efficiency encoder 2 uses an encoding method that does not perform inter-frame prediction, for example, a DCT method, etc., the present embodiment is applied to image frames at regular intervals on the time axis. It goes without saying that the same processing as that for the refresh image is performed, and for other image frames, the same processing as that for the image that is not the refresh image according to the present embodiment may be performed. For example, if the speed is 6x, the fixed interval on the time axis is
Every 6 frames.

An information signal recording / reproducing apparatus according to the second embodiment of the present invention will be described below with reference to FIGS. 1, 3, 4, 5, 7, and 8. The difference from the first embodiment is that azimuth recording is used. That is,
Recording is performed alternately with heads with different azimuth angles.
A basic block diagram of the signal processing unit is shown in FIG. 1, which is the same as that of the first embodiment, but is different from the first embodiment in the arrangement pattern of recording data. That is, the storage amounts of the two-dimensional array storage circuit 22 and the two-dimensional array storage circuit 31 are more than twice the storage amount of the first embodiment, and the control signals output from the array control circuit 23 and the array control circuit 33 are different. . Therefore, the array control circuit 2 will be described with reference to FIGS.
3 and the operation of the array control circuit 33 will be described.

It is assumed that the image data is as shown in FIG. 5 as in the first embodiment, and that each frame is divided into 10 blocks. The two-dimensional array storage circuit 22 is a storage circuit having array numbers as shown in FIG. That is,
Matrix of l rows and m columns (here, l = 10, m = 14
And the column number is 0 at the left end and the number increases by 1 every other column, and when the number becomes 6, the next 7 is a column between the columns 0 and 1 and similarly 7 to 1 The number is incremented by 1 every other row, and the row number is incremented by 1 for each row with the bottom row as 0. Then, the array control circuit 23 outputs the following control signals.

Regarding the image of S00, in FIG.
As an array to be recorded at the positions of B1, B2 ", B3", ..., B10 ", (0, 0), (1,
3), (1, 4), ..., (5, 8) are given, and S01
As for the images up to S0n, in FIG.
As recorded in the positions of 1 ″, D2 ″, ..., Dm ″, as arrays, (0, 1), (0, 2), ...
.., (5, 9) are given, and regarding the image of S10, in FIG. 7, C1, C2 ", C3", ..., C5 ",
..., (10), (9, 3), (9, 4), ...
.., (10,8), ..., (13,8) are given.
The image data between S11 and S1n are arrayed so as to be recorded at positions E1 ″, E2 ″, ..., Em ″ in FIG. 7, respectively (8, 1), (8, 2),
..., (13, 9) is given. And (0,0),
(0,1), ..., (0,9), ..., (13,
The sync block is transmitted from the two-dimensional array storage circuit 22 to the recording amplifier 5 in the order of 9) and recorded on the medium.

Next, the time of reproduction will be described. First, the case of normal reproduction will be described. In FIG. 1, the operations of the reproduction amplifier 6 and the reproduction information decoding device 9 are the same as those in the first embodiment. The difference from the first embodiment is a two-dimensional array storage circuit 31 and an array control circuit 33 inside the data recording pattern converter 8 in FIG. Therefore, the two-dimensional array storage circuit 31 and the array control circuit 33 will be described below. The two-dimensional array storage circuit 31 is similar to the two-dimensional array storage circuit 22 used in the second embodiment, and stores the reproduced sync block from the reproduction amplifier 6 based on the output of the array control circuit 33. , To the address remover 32. Here, regarding the operation of the array control circuit 33,
This will be described below.

The array control circuit 33 is a two-dimensional array storage circuit 3.
When 1 receives the data from the reproduction amplifier 6 and transmits the data to the address remover 32, it outputs a control signal to perform the following operation. First, the reproduced sync blocks sent from the reproduction amplifier 6 are (0, 0), (0, 1), ..., (0, 9), in time order in FIG.
(6,0), ..., (6,9), ..., (13,
Store in the order of 9). At this time, the reproduced sync block of S00 which is the refresh image is (0, 0),
(1,3), (1,4), (2,7), (2,8),
(3,0), (4,3), (4,4), (5,7),
It is stored in (5, 8). Therefore, the data stored in the array corresponding to the reproduced sync block in S00 is read, and subsequently, D1 ″, D in FIG. 7 is read.
The data of the array corresponding to 2 ", ..., Dm" is read out. Then, next, the data of the array corresponding to C1, C2 ", ..., C10" is read. Then, subsequently, the data of the array corresponding to E1 ″, E2 ″, ..., Em ″ is read. The data sent from the two-dimensional array storage circuit 22 to the address remover 32 is read by the address remover 32. The same processing as that of the first embodiment is performed and sent to the reproduction information decoding device 9.

The case of 6 × speed special reproduction will be described below. In this case, the reproduction amplifier 6 and the reproduction information decoding device 9 are directly connected by the switch 7. Similar to the first embodiment, in the case of high speed search, the reproduced sync blocks input to the reproduction amplifier 6 by the search pilot signal are B1, B2 ", ..., B9, B10", C1, C.
Only refresh images of S00, S10, ... Of 2 ", ..., C10". And regarding these,
It is decoded by the reproduction information decoding device 9 and becomes a reproduced image. At this time, since the reproduced images are intermittent in the reproduced frames, an image in a state like frame advance is reproduced. With the above configuration, the same effect can be obtained even when azimuth recording is performed.

In the present embodiment, the case of 6 × speed is shown, but it goes without saying that it is possible to realize high speed reproduction at other speeds by changing the arrangement method. Further, in the present embodiment, the case where the predictive interframe coding is temporally sequentially described has been described, but it goes without saying that it is also possible in the case of other interframe prediction. Further, when the high-efficiency encoder 2 uses an encoding method that does not perform inter-frame prediction, for example, a DCT method, etc., the present embodiment is applied to image frames at regular intervals on the time axis. It goes without saying that the same processing as that for the refresh image is performed, and for other image frames, the same processing as that for the image that is not the refresh image according to the present embodiment may be performed. For example, if the speed is 6x, the fixed interval on the time axis is
Every 6 frames.

[0026]

As described above, according to the present invention, in order to reproduce all the data of the frame which is not predicted at the time of high speed reproduction, the data of the frame which is not predicted at the portion where the reproducing head passes during the high speed reproduction. A data recording pattern converter for recording the data and a data recording pattern for outputting the data of the frame not to be predicted among the reproduced data in the normal reproduction first, and subsequently outputting the data by the predictive interframe coding. A data compression method is provided by a reverse switch and a reproduction switch connected to the reproduction amplifier and the data recording pattern reverse converter during normal reproduction, and a changeover switch connecting the reproduction amplifier and reproduction information decoding device during high-speed reproduction. Even when not only intra-coding but also prediction inter-frame coding is included, the frame data that is not predicted during high-speed playback is decoded. Can play all the data, the image can be reproduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal processing unit of an information signal recording / reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a data recording pattern diagram on the medium in the first embodiment.

FIG. 3 is a block diagram of a data recording pattern converter of the first embodiment.

FIG. 4 is a block diagram of a data recording pattern inverse converter according to the first embodiment.

FIG. 5 is a time-axis direction difference compression diagram of image data.

FIG. 6 is an array pattern diagram in the two-dimensional array storage device of the first embodiment.

FIG. 7 is an image data recording pattern diagram in the second embodiment of the present invention.

FIG. 8 is an array pattern diagram in the two-dimensional array storage device of the second embodiment.

FIG. 9 is a block diagram of a conventional information signal recording / reproducing apparatus.

[Explanation of symbols]

 1 recording code generator 2 high efficiency encoder 3 channel encoder 4 data recording pattern converter 5 recording amplifier 6 reproducing amplifier 7 changeover switch 8 data recording pattern inverse converter 9 reproducing information decoder 10 channel code decoder 11 High Efficiency Code Decoder 21 Address Adder 22 Two-Dimensional Array Storage Circuit 23 Array Control Circuit 31 Two-Dimensional Array Storage Circuit 32 Address Removal Circuit 33 Array Control Circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiji Ueda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Shigeki Murata 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-5-227505 (JP, A)

Claims (4)

(57) [Claims] 1. Data of several frames from a recording code generation device for optimal encoding for recording are recorded, and at least one frame is provided in a portion through which a reproducing head passes during high speed reproduction.
Data recording pattern so that minute data is arranged
An information signal recording / reproducing apparatus comprising a data recording pattern converter for converting and further adding a search pilot signal to output image data to a recording amplifier. 2. A plurality of frames of data from a recording code generation device that performs predictive coding and subsequently performs optimum coding for recording are stored, and a refresh image is displayed in a portion where a reproducing head passes during high speed reproduction. At least one frame of data
Data recording pattern is converted so that data is arranged
An information signal recording / reproducing apparatus further comprising a data recording pattern converter for adding a search pilot signal and outputting image data to a recording amplifier. 3. A data storage pattern inverse conversion for storing the reproduction data from the reproduction amplifier for several frames and outputting the reproduction information data in the order of time input to the recording code generation device according to claim 1 or 2 during normal reproduction. A playback amplifier and the data recording pattern inverse converter are connected during normal reproduction, and a selector switch for directly outputting the signal from the reproduction amplifier during high-speed reproduction, and a search pilot signal during high-speed reproduction. An information signal recording / reproducing apparatus having a control mechanism for reproducing at normal speed until recognition, and for reproducing at high speed if a search pilot signal is recognized. 4. The information signal recording / reproducing apparatus according to claim 3, wherein the reproduction information data reproduced during high-speed reproduction is a refresh image of predictive coding.