JP2682838B2 - Data processing device - Google Patents

Description

The present invention relates to the technical field of data processing and further to serial communication, for example, a technology effectively applied to a microcomputer equipped with a serial communication interface.

(Prior art)

Microcomputers can be programmed by software to form desired sequential logic, which enables high-level processing in a wide range of application fields. Furthermore, data can be bit serialized with external devices such as data processing terminals and modems. Some have a serial input / output circuit that enables communication.

As data transmission control procedures for exchanging data in bit serial, high-level data link control (HDLC) convenience order, binary synchronous communication (BSC or BI-SYNC) method, and various transmission such as start-stop synchronization procedure Although there is a control procedure, a serial input / output circuit mounted on a conventional microcomputer or the like only supports one of the data transmission control procedures.
i8044 described in "d Control Modules Data Book"
It only supported the HDLC procedure.

[Problems to be solved by the invention]

By the way, as the price of logic LSI such as a microcomputer is reduced, these devices tend to be multi-functional. Especially, focusing on the serial interface function, the above-mentioned three types of data transmission control procedures have respective advantages. Since it has a wide range of application fields, it is possible to support multiple data transmission control procedures even for serial input / output circuits built into data processing LSIs such as microcomputers, and to achieve the required multifunctional functions. The present inventor has found the need for making serial communication achievable.

Furthermore, in this case, from the viewpoint of manufacturing and economical efficiency, the LSI
Since the chip cannot be made unlimitedly large, it is necessary to consider that the condition that the logical scale can be minimized is satisfied when supporting multiple data transmission control procedures.

An object of the present invention is to provide a data processing device capable of performing multifunctional serial communication in response to a request for serial data transmission. Yet another object of the present invention is to make such a requirement feasible with a minimum logical scale.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, the receiving means for giving the data supplied from the serial input line to the internal bus and the transmitting means for giving the data supplied from the internal bus to the serial output line are the control procedures for exchanging data. HDLC
At least two types of control procedures among the procedures, the BI-SYNC procedure, and the start-stop synchronization procedure are retained, and the control procedures retained by these are selectively selectable based on the instruction of the processor. This selection instruction can be issued based on the operation mode signal set in the control register by the processor. Further, the hardware of the reception buffer and the reception shift register included in the reception means and the hardware of the transmission buffer and the transmission shift register included in the transmission means can be made common regardless of the selected data transmission control procedure. it can.

(Operation)

According to the above-mentioned means, it becomes possible to selectively support a plurality of types of data communication control procedures, thereby achieving a data processing device capable of performing multifunctional serial communication in response to a request for serial data transmission. It is a thing. Furthermore, by making a part of the hardware common regardless of the data transmission control procedure, it is possible to realize the multi-functionalization of the serial communication with a minimum logical scale.

〔Example〕

FIG. 2 shows an outline of a microcomputer which is an embodiment of the present invention. The microcomputer shown in the figure is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The microcomputer shown in FIG. 2 is not particularly limited, but is externally connected via a central processor (CPU) 1, a timer circuit 2, a direct memory access controller (DMAC) 3, a transmission line Tx and a reception line Rx. A serial I / O port 4 for performing a serial communication interface, a parallel I / O port 5, a random access memory (RAM) 6, a read only memory (ROM) 7, etc. are included, and each is coupled to an internal bus 8. It

The serial I / O port 4 uses the HDLC procedure, BI-SY, as a control procedure or communication logic for exchanging data in a bit-serial manner with the outside.
The NC procedure and the start-stop synchronization procedure are held, and the control procedure held by them is selectively made selectable based on the instruction of the CPU 1.

Here, the frame configuration according to the HDLC procedure is, for example, the third
As shown in the figure, a flag F indicating the start of a frame, an address field AF indicating the own station or a partner station, a control field CF indicating the type of frame, a data field DF having an integer byte structure, and a frame check sequence for transmission error check It is composed of FCS and a flag F indicating the end of the frame.

The frame structure according to the BI-SYNC procedure is, for example, as shown in FIG. 4, one or more character synchronization codes SYNC inserted to indicate the start of a frame, a data field DF that follows, and a transmission error detection code. Composed of CRC.

The data format according to the start-stop synchronization procedure is, for example, as shown in FIG. 5, in character units, and one character is composed of a start bit SB, a data bit DB, a parity bit PB, and an end bit or stop bit EB. .

A detailed example block diagram of the serial I / O port 4 is shown in FIG.

This serial I / O port 4 is a receiving unit 10 for giving the data supplied from the receiving line Rx to the internal bus 8.
, A transmission unit 20 for giving data supplied from the internal bus 8 to the transmission line Tx, and a status / control register unit 30 for holding various control information and status information.

The receiving unit 10 synchronizes the information supplied from the receiving line Rx with the base bad system in synchronization with the clock CLKr.
A decoder 11 for decoding into a predetermined format such as an NRZ (non-return to zero) format or a bi-phase format, a first reception processing circuit 12 for receiving the information decoded by this decoder 11 and processing it The second reception processing circuit 13 and the first reception processing circuit 12 or the second reception processing circuit 13 which is selectively operated according to the data transmission control procedure that is selectively adopted in the operation of the serial I / O port 4. Of the serial I / O port 4 and the receiving shift register 14 for converting the information output from the serial to parallel, the receiving buffer register 15 for storing the parallel data supplied from the receiving shift register 14 and supplying it to the internal bus 8. The reception controller 16 controls each of the above functional blocks according to a data transmission control procedure that is selectively used in operation.

The transmission unit 20 is provided with a transmission buffer register 21 for receiving and storing data to be transmitted from the internal bus 8, a transmission shift register 22 for converting the parallel data given from the transmission buffer register 21 into a serial data, and a transmission shift register 22. A first transmission processing circuit 23 and a second transmission processing circuit 24 for receiving serial data and processing the serial data, serial
The information output from the first transmission processing circuit 23 or the second transmission processing circuit 24, which is selectively operated according to the data transmission control procedure that is selectively used in the operation of the I / O port 4, is clocked. Encoder 25 that encodes from a predetermined format such as NRZ format or biphase format in the baseband system in synchronization with CLKt, and serial I / O
It is configured by a transmission controller 26 that controls each of the above functional blocks according to a data transmission control procedure that is selectively adopted in the operation of the O port 4.

Status control register unit 30 above
Is a receiving unit 10, a transmitting unit 20 or even a serial
It includes various status registers or flag registers for indicating the status of the modem connected to the I / O port 4, and various control registers for determining the operation mode of the serial I / O port 4.

For example, as various status registers or flag registers, although not shown respectively, presence or absence of a parity error detected by the first reception processing circuit 12 and the second reception processing circuit
A transmission error status for indicating the presence or absence of a data transmission error detected by 13, a frame error status for indicating the presence or absence of a frame error detected by the second reception processing circuit 13, and the operation of the modem for the receiving unit 10. There is a data carrier detect status for indicating whether or not a reset instruction has been issued, a full / empty status for indicating the vacancy of the reception buffer register 15, and a full / empty status for indicating the vacancy of the transmission buffer register 21.

As the control register, the transmission controller 26
And the receiving controller 16, start-stop synchronization procedure, HDLC procedure,
Alternatively, three transmission procedure mode registers MR1 to MR3 for instructing which control logic of the BI-SYNC procedure is to be selected are provided, and besides, although not shown respectively, a reception unit
The receive enable for determining whether the receiving operation by 10 is possible, the transmit enable for determining the transmitting operation for the transmitting unit 20, the request to send for requesting the start of transmission to the modem, etc. is there.

The transmission procedure mode registers MR1 to MR3 are respectively initialized by the data supplied from the CPU 1 via the internal bus 8. For example, when "1" is set in the mode register MR1, the transmission controller 26 and the reception controller 16 start / stop. The control logic corresponding to the synchronization procedure is selected to control the receiving unit 10 and the transmitting unit 20. When "1" is set in the mode register 2, the transmission controller 26 and the reception controller 16 control the reception unit 10 and the transmission unit 20 by selecting the control logic corresponding to the BI-YSNC procedure. Further, when “1” is set in the mode register MR3, the transmission controller 26 and the reception controller 16 are
The control logic corresponding to the HDLC procedure is selected to control the receiving unit 10 and the transmitting unit 20.

The reception controller 16 is provided with control logic for adapting the operation of the reception unit 10 to the start-stop synchronization procedure, HDLC procedure, and BI-SYNC procedure, and the control logic is set in the transmission procedure mode registers MR1 to MR3. It is selected according to the alternative.

In the reception unit 10, the decoder 11, the reception shift register 14, and the reception buffer register 15 are hardware commonly used regardless of the control logic adopted by the reception controller 16.

The operation of the first reception processing circuit 12 is selected in response to the fact that the reception controller 16 adopts the control logic corresponding to the start-stop synchronization procedure. When the operation of the first reception processing circuit 12 is selected, the first reception processing circuit 12 detects the start bit SB and the end bit EB from the information supplied according to the start-stop synchronization procedure, and recognizes one character, The transmission error of the data bit DB following the start bit SB for each character is determined based on the parity bit PB, and the information is given to the reception shift register 14 in character units.

The second reception processing circuit 13 is HD in the reception controller 16.
The operation is selected in response to the adoption of the control logic according to the LC procedure or BI-SYNC procedure. That is, the second reception processing circuit 13 receives the serial data supplied according to the HDLC procedure.
It has hardware that can be shared to process serial data supplied according to the BI-SYNC procedure. When the operation of the second reception processing circuit 13 is selected by the control logic according to the HDLC control procedure, the second reception processing circuit 13 starts and ends one frame by the flag F of the serial data supplied according to the HDLC procedure. At the same time as detecting, it is determined from the address field AF whether or not the frame is for the own station, and for the frame for the own station, whether or not there is a transmission error based on the frame check sequence FCS is calculated, and the control field The contents of CF and the data field DF are given to the reception shift register 14. In addition, the operation of the second reception processing circuit 13 is BI
When selected by the control logic according to the SYNC procedure, the second reception processing circuit 13 recognizes the start of the data field DF by detecting the character sync code SYNC of the serial data supplied according to the BI-SYNC procedure. Then, after determining the presence or absence of a transmission error based on the transmission error detection code CRC, the information of the data field DF and the like are given to the reception shift register 14.

The transmission controller 26 is provided with control logic for adapting the operation of the transmission unit 20 to the start-stop synchronization procedure, HDLC procedure, or BI-SYNC procedure, and the control logic is set to the setting state of the transmission procedure mode registers MR1 to MR3. It is selected according to the alternative.

In the transmission unit 20, the above transmission buffer register
The 21, the transmission shift register 22, and the encoder 25 are hardware commonly used regardless of the control logic selected and adopted by the transmission controller 26.

The operation of the first transmission processing circuit 23 is selected in response to the fact that the transmission controller 26 adopts the control logic corresponding to the start-stop synchronization procedure. When the operation of the first transmission processing circuit 23 is selected, the first transmission processing circuit 23 adds the start bit SB, the validity bit PB and the end bit EB to the serial data supplied from the transmission shift register 22. Then, a data format suitable for the start-stop synchronization procedure is formed, and this is given to the encoder 25.

The second transmission processing circuit 24 is HD in the transmission controller 26.
The operation is selected in response to the adoption of the control logic according to the LC procedure or BI-SYNC procedure. That is, the second transmission processing circuit 24 includes hardware that can be used for both frame formation according to the HDLC procedure and frame formation according to the BI-SYNC procedure. When the operation of the second transmission processing circuit 24 is selected by the control logic according to the HDLC procedure, the second transmission processing circuit 24 forms the frame check sequence FCS based on the serial data supplied from the transmission shift register 22. Together with the frame check sequence FCS or 1
Encoder by adding a flag F etc. to indicate the start and end of the frame and forming a frame according to the HDLC procedure
Give to 25. In addition, the operation of the second transmission processing circuit 24 is BI-SY.
When selected by the control logic according to the NC procedure, the second transmission processing circuit 24 forms the transmission error detection code CRC based on the serial data supplied from the transmission shift register 22, and also the transmission error detection code CRC. And character synchronization code SYNC are added to form a frame in accordance with the BI-SYNC procedure and the frame is given to the encoder 25.

According to the above embodiment, the following effects can be obtained.

(1) In the system to which the microcomputer of the present embodiment is applied, the data transmission control procedure when serial communication is performed with the microcomputer via the serial I / O port 4 is a start-stop synchronization procedure or HDLC. Either the procedure or the BI-SYNC procedure can be selectively selected. As a result, the microcomputer of this embodiment is not limited in its transmission control procedure in response to a request for serial data transmission, and can realize multifunctional serial communication. Therefore,
Regardless of the data transmission control procedure adopted in the desired system, different microcomputers are adopted according to the data transmission control procedure, or various microcomputers having different serial interface functions are supplied. The inconvenience and troublesome work are eliminated.

(2) Decoder 11, reception shift register 14, and reception buffer register 15 included in the reception unit 10, encoder 25, transmission shift register included in the transmission unit 20
22 and the transmission buffer register 21 have common hardware regardless of which data transmission control procedure is selected alternatively, and each data transmission control procedure has an independent line control unit. Therefore, it is possible to realize multiple functions of the serial communication with a minimum logical scale under the constraint that the LSI chip cannot be increased infinitely from the viewpoint of manufacturing and economical efficiency. it can.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, the peripheral module included in the microcomputer is not limited to the above-described embodiment, and can be appropriately changed according to the required specifications. Also, the data transmission control procedure that the microcomputer can selectively select does not have to be all the HDLC procedure, BI-SYNC procedure, and start-stop synchronization procedure, and at least one of the two procedures can be selected. If the configuration is selectable as described above, it is possible to obtain the effect that the serial communication has multiple functions and that the function can be realized with a minimum logical scale as in the above-described embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to a general-purpose microcomputer having a serial I / O port, which is the field of application of the background, has been described, but the present invention is not limited to this. However, it can be widely applied to communication or control LSIs, protocol processors, etc. The present invention can be applied to at least a condition including a serial communication interface unit and a processor commonly connected to an internal bus.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, the receiving means and the transmitting means for exchanging serial data have at least two types of control procedures, namely, an HDLC procedure, a BI-SYNC procedure, and a start-stop synchronization procedure, as a data transmission control procedure in at least a lower layer. It is possible to selectively support multiple types of data transmission control procedures, as a result of which the multi-function serial communication can be performed in response to a request for serial data transmission. There is an effect that a data processing device capable of performing In addition, by sharing a part of the hardware regardless of the data transmission control procedure, it becomes possible to realize the multifunctional serial communication with a minimum logical scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a detailed example of a serial I / O port applied to a microcomputer which is an embodiment of the present invention, and FIG. 2 is a schematic diagram of a microcomputer which is an embodiment of the present invention. Block diagram, FIG. 3 is an explanatory diagram showing an example of a frame configuration according to the HDLC procedure, FIG. 4 is an explanatory diagram showing an example of a frame configuration according to the BI-SYNC procedure, and FIG. 5 is an example of a data format according to the start-stop synchronization procedure. It is an explanatory view shown. 1 ... CPU, 2 ... Timer circuit, 3 ... DMAC, 4 ... Serial I / O port, 5 ... Parallel I / O port, 6 ... RA
M, 7 ... ROM, 8 ... internal bus, Rx ... reception line, Tx ...
… Transmission line, 10 …… Reception unit, 11 …… Decoder, 12
...... First reception processing circuit, 13 ...... Second reception processing circuit, 14 ...
… Receive shift register, 15 …… Receive buffer register,
16 …… Receiving controller, 20 …… Sending unit, 21 ……
Transmission buffer register, 22 ... Transmission shift register, 23
...... First transmission processing circuit, 24 ...... Second transmission processing circuit, 25 ...
… Encoder, 26 …… Transmission controller, 30 …… Status control register, MR1 to MR3 …… Transmission procedure mode register.

Front page continued (72) Inventor Kunihiko Nakata 1450 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Musashi Plant, Hitachi Ltd. (72) Inventor Yasushi Akao 1450, Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Musashi, Ltd. In the factory (56) References JP-A-62-160849 (JP, A)

Claims (1)

(57) [Claims] 1. An internal bus and a common connection to the internal bus
In a data processing device including a CPU and a serial communication interface unit on a semiconductor substrate of a semiconductor integrated circuit, the serial communication interface unit is connected to the internal bus, and is a high-level data link control procedure, a binary synchronous communication procedure, and an asynchronous synchronization procedure. Receiving means for supplying the data supplied from the serial input line to the internal bus according to the selected one of the control procedures, a high level data link control procedure connected to the internal bus, a binary synchronous communication procedure, and an asynchronous communication. Transmitting means for giving the data of the internal bus to the serial output line according to one control procedure selected from the synchronizing procedures; and, connected to the internal bus, the receiving means and the transmitting means, via the internal bus. Control means for selecting a control procedure of the receiving means and the transmitting means based on an operation mode signal initialized from the CPU, the receiving means of the serial communication interface means is supplied from the serial input line. A decoder for decoding the data, a first reception processing circuit for processing the information decoded by the decoder according to an asynchronous synchronization procedure, a high-level data link control procedure and a binary synchronous processing for the information decoded by the decoder. A second reception processing circuit that processes according to a communication procedure, a reception shift register that converts information output from the first reception processing circuit and the second reception processing circuit from serial to parallel, and parallel data from the reception shift register. Receiving buffer for storing and supplying to the internal bus And a reception controller that selects a processing procedure of the first reception processing circuit and the second reception processing circuit based on the operation mode signal initialized from the CPU in the control procedure, the serial communication interface means The transmission means receives a transmission buffer for receiving and storing data to be transmitted from the internal bus, a transmission shift register for converting parallel data given from the transmission buffer into serial data, and serial data supplied from the transmission shift register. A first transmission processing circuit that processes according to an asynchronous synchronization procedure; a second transmission processing circuit that processes serial data supplied from the transmission shift register according to a high-level data link control procedure and a binary synchronous communication procedure; and the first transmission processing circuit. Processing circuit and the second transmission processing circuit Et an encoder for encoding information to be output, the control means on the basis of the said operating mode signal is initialized by the CPU to the first transmission processing circuit and the second
A transmission controller that selects a processing procedure of a transmission processing circuit, wherein the decoder, the reception shift register, and the reception buffer of the reception means included in the serial communication interface means are configured to select a reception processing procedure. The hardware is commonly used regardless of whether the transmission buffer of the transmission means, the transmission shift register, and the encoder included in the serial communication interface means are commonly used regardless of the selection of the transmission processing procedure. Data processing device characterized in that the data processing device is used.