JP2674744B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a highly integrated D-RAM cell. SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device such as a D-RAM including a switching transistor and a groove-type capacitor, in which a plurality of island-shaped protrusions formed on a semiconductor substrate have active portions of the switching transistor and capacitors. The charge storage part is three-dimensionally formed, the channel stopper is formed at the bottom of the groove between the protrusions, the cell plate of the capacitor is filled in the groove, and the space between the protrusions in the row direction is higher than the protrusion. A plurality of bits that fill up to the position and form a plurality of word lines that extend in the row direction to cover these protrusions and that extend over the protrusions in the column direction and that are connected to the source / drain portions of the switching transistor. By forming a line, high integration is possible. [Prior Art] Conventionally, various element structures for integrating a semiconductor memory layer including an insulated gate field effect transistor and a capacitor as an information storage unit have been considered. As an example thereof, it has been attempted to improve the degree of integration of D-RAM cells by adopting a trench capacitor as shown in FIG. In this, an insulated gate field effect transistor composed of a source region 14, a drain region 15, a gate electrode 16 and a gate insulating film 17 is used as a switching transistor, a trench is formed beside it, and a capacitor is formed on the inner surface of the trench. An oxide film 18 is provided, and a first polycrystalline Si layer 6 is further provided inside the groove to form a capacitor. In this structure, since the MOS type capacitor is formed vertically to the surface of the substrate, the arrangement of the memory units can be highly integrated (Japanese Patent Publication No. 59-48547). Japanese Patent Publication No. 60-23506 discloses an invention in which the materials for the capacitor insulating film and the gate insulating film in the D-RAM cell shown in FIG. 3 are made different so that the integration density is further improved. . [Problems to be Solved by the Invention] However, in the structure in which the trench capacitor is provided beside the switching transistor as shown in FIG. 3, there is a problem that the depletion layer spreads and punch-through occurs between the capacitors. Since the switching transistor and the capacitor are formed side by side on the semiconductor substrate, there is a limit to miniaturization of the cell. In particular, as the cell size becomes smaller, the margin of mask misalignment with respect to the word line is reduced. Further, in the conventional trench type capacitor, the charge storage portion is exposed, so that the soft error rate due to α rays is large. [Means for Solving Problems] According to the present invention, a step of forming a plurality of island-shaped projections arranged in a matrix on a semiconductor substrate and a channel stopper formed on the bottom of a groove between the projections are formed. A step of covering a surface of the semiconductor substrate including an inner surface of the groove with a first insulating film, and forming a surface of the channel stopper and the first insulating film up to an intermediate depth of the groove. A cell plate, a step of covering the surface of the cell plate with a second insulating film, a step of forming a source / drain portion of a switching transistor at the tip of the protrusion, and a step of forming a groove in the groove. A portion on the second insulating film between the protruding portions in the direction of the arrow is filled up to a position higher than the protruding portion, and a plurality of word lines extending in the row direction are formed to cover these protruding portions. And the process of
Covering the word line with a third insulating film; forming a contact hole penetrating the third insulating film, the word line, and the first insulating film to reach the source / drain portion; A step of covering the exposed surface of the word line facing the inner surface of the contact hole with a fourth insulating film; and, after forming the fourth insulating film, extending over the protrusion in the column direction and contact hole. The above problems are solved by a method of manufacturing a semiconductor memory device, which comprises a step of forming a plurality of bit lines connected to the source / drain portions via the above. [Operation] By adopting such a semiconductor memory device manufacturing method, the switching transistor is formed on the capacitor, and the area required for one cell is reduced as compared with the conventional one. The degree of integration can be increased accordingly. Further, the capacitors are electrically separated from each other by the groove and the channel stopper at the bottom of the groove, so that punch-through between the capacitors is physically difficult to occur. In addition, since the space between the protrusions in the row direction on the cell plate having a flat surface is completely filled with the word line via the second insulating film and the protrusions are covered with the word line, the memory cell The cross-sectional area of the word line is large relative to the area, and the resistance of the word line is low. [Embodiment] FIG. 1A is a plan view of a memory device of the present invention, FIG. 1B is a sectional view taken along line BB ′ in FIG. 1A, and FIG.
Is a sectional view of CC ', and FIG. 1D is a sectional view of DD'. As shown in FIG. 1A, the bit line 12 and the word line 6 intersect at each columnar protrusion, and the bit line 12 is the source / transistor of the transistor.
It is connected to the drain portion 11 (region surrounded by line a) by a contact window shown by two diagonal lines and surrounded by line C.
The word line formed of the second polycrystalline Si layer 6 surrounds the four sides of each columnar protrusion and forms the transistor gate on the side wall thereof. A cell plate composed of the first polycrystalline Si layer 5 is provided around the lower portion of each columnar protrusion formed on the substrate, a polycrystalline Si gate 6 formed around the protrusion above the capacitor and each columnar pillar. Source / drain portions 11 are provided on the upper portions of the protrusions. As shown in FIG. 1B, the spaces between the pillar-shaped protrusions are filled with the first polycrystalline Si layer 5, which serves as a cell plate. The capacitor is composed of a first polycrystalline Si layer that will be a cell plate, a capacitor oxide film 4, and a P ^-- Si layer in the columnar protrusion, and an inversion layer is formed on the surface of the columnar protrusion that is in contact with the capacitor oxide film so that the charge is Accumulated. In the D-RAM cell of the present invention, the oxide film 4 and the first polycrystal are formed around the columnar protrusions remaining after the trench etching.
The Si layer 5 was provided, and the portion under the columnar protrusion was used as a capacitor, and the source / drain portion 11 was formed on the top of the columnar protrusion.
And a second portion around the columnar protrusion above the capacitor.
A gate electrode is provided by the polycrystalline Si layer 6 to form a switching transistor, and the second polycrystalline Si layer 6 to be a word line is formed.
Is characterized in that a gate electrode is formed on the side wall of each columnar protrusion, a window is opened in the source / drain portion 11 to oxidize the surface of the word line, and then contact is made with the bit line. The source / drain region 11 acts as a source when writing information and as a drain when reading information. When a signal is applied to word line 6 and the switching transistor is turned on, bit line 12
Depending on the state, electric charge flows in and out of the capacitor around the columnar protrusion through the channel just below the gate oxide film. Since the capacitor of the adjacent mesa portion is electrically separated by the channel stopper 9 provided at the bottom of the groove, punch-through between the capacitors does not occur. Next, an embodiment in which the present invention is applied to a D-RAM cell will be described with reference to FIGS. First, as shown in FIG. 2A, the silicon substrate 1 provided with the oxide film 2 is subjected to trench etching using a photoresist as a mask to form columnar silicon protrusions 3a, 3b, 3c. B ⁺ ions are implanted into the bottom of the groove, annealing is performed to provide a channel stopper 9, and then oxidation is performed to form an oxide film 4 to be a capacitor oxide film on the inner surface of the groove (FIG. 2B). Next, the first polycrystalline silicon layer 5 containing a donor is deposited on the entire surface, and an etch bag is performed by RIE on the entire surface to fill the lower half of the groove with the first polycrystalline silicon layer 5. (Fig. 2C). After forming the gate oxide film of the switching transistor, donor ions are ion-implanted on the entire surface and annealed to form the source / drain portion 11 on the top surface of each columnar protrusion. At this time, the oxide film 7 is simultaneously formed on the surface of the first polycrystalline Si layer 5. Further, at this time, if necessary, impurities may be introduced from the portion corresponding to the oxide film 7 on the side wall of each columnar protrusion to form the source / drain regions. The distance between the wiring film 7 and the source / drain portion 11 becomes the gate length of the switching transistor (FIG. 2D). A second polycrystalline Si layer 6 containing impurities is deposited on the entire surface, and then a SiO ₂ layer 10 is grown. Impurities may be diffused from the PSG film layer 10 without doping the second polycrystalline Si layer 6 with impurities (FIG. 2E). A hole for bit line contact is formed in the oxide film 10 and the second polycrystalline Si layer 6. After oxidizing the exposed side wall of the second polycrystalline Si layer, lightly
Perform RIE processing. This contact hole is a region indicated by a line c in FIG. 1A, a second polycrystalline Si layer exists outside the line b, and an oxide film exists between the line b and the line c (see FIG. 2). F).
Bit lines 12 are provided by connecting the source / drain portions 11 with Al electrodes. A plan view of the completed D-RAM cell of the present invention is shown in FIG. 1, and a sectional view taken along line CC 'of FIG. 1 is shown in FIG. 1C. [Advantages of the Invention] As described above, according to the present invention, since the lower half of the side surface of the columnar silicon protrusion is used as a capacitor and a ring-shaped gate is provided above the protrusion to form a switching transistor, The occupying area can be reduced, and high integration can be achieved. Further, since the adjacent capacitors are electrically separated by the channel stopper at the bottom of the groove, each capacitor has a structure that is not affected by punch through. Further, in the semiconductor memory device manufactured according to the present invention, the cross-sectional area of the word line is large relative to the memory cell area and the resistance of the word line is low, so that the memory cell area can be further reduced, and higher integration can be achieved. Can be achieved. Further, in the semiconductor memory device manufactured according to the present invention, since the accumulated charges are formed inside the columnar protrusions of single crystal Si, the soft error rate due to α rays can be made very small. Therefore, a semiconductor memory having a higher degree of integration and higher reliability than the conventional trench capacitor type semiconductor memory device can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a plan view of a memory device of the present invention, and FIG. 1B, C, D
Is a sectional view thereof. 2A to 2F are views showing the manufacturing steps of the memory device of the present invention for each step. FIG. 3 is a sectional view of a conventional trench capacitor type D-RAM cell. 1 ... P ^- Si substrate, 2, 4, 7, 10 ... Oxide film 3a, 3b, 3c ... Columnar protrusion, 5 ... First polycrystalline Si layer 6 ... Second polycrystalline Si layer, 8 ...... Photoresist film 9 ...... Channel stopper 11 ...... Source / drain section, 12 ...... Bit line 13 ...... Source, 14 ...... Drain 15 ...... Gate, 16 ...... Gate oxide film 17 ...... Capacitor oxide film

Claims (1)

(57) [Claims] Forming a plurality of island-shaped protrusions arranged in a matrix on the semiconductor substrate; forming a channel stopper at the bottom of the groove between the protrusions; and the surface of the semiconductor substrate including the inner surface of the groove. With a first insulating film, filling the channel stopper and the first insulating film with a flat cell plate having a flat surface up to the middle depth of the groove, and covering the surface of the cell plate. Covering with a second insulating film, forming a source / drain portion of a switching transistor at the tip of the protrusion, and insulating the second insulation between the protrusions in the row direction in the groove. Filling a portion on the film to a position higher than the protrusions and forming a plurality of word lines extending in the row direction so as to cover these protrusions; Covering with a film; forming a contact hole penetrating the third insulating film, the word line, and the first insulating film to reach the source / drain portion; and exposing the inner surface of the contact hole. A step of covering the exposed surface of the word line with a fourth insulating film; and, after forming the fourth insulating film, extending over the protrusion in the column direction and through the contact hole, the source / drain portion. And a step of forming a plurality of bit lines connected to the semiconductor memory device.