JP2670265B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a method of manufacturing a CMOS semiconductor device having an LDD structure of either one of an n-channel transistor and a P-channel transistor. (Prior Art) A conventional method of manufacturing a CMOS semiconductor device will be described with reference to FIG. An n-well layer 22 is formed on a predetermined portion of a P-type silicon substrate 21 having a crystal orientation (100) by thermal diffusion or the like. Then, a field oxide film 23 is formed on the substrate 21 and the n well layer 22 as an element isolation region, and then a thermal oxide film 24 is formed on the substrate 21 and the n well layer 22 surrounded by the field oxide film 23.
Further, a polycrystalline silicon film 25 doped with, for example, phosphorus is deposited on the entire surface (see FIG. 3A). Photoresist (not shown) on the polycrystalline silicon film 25
Are stacked, a predetermined portion is patterned, and the remaining photoresist is used as a mask, and the unnecessary portion of the polysilicon film 25 is removed by etching, so that the polysilicon region is formed in the element region surrounded by the field oxide film 23. Gate electrodes 28 and 29 made of films are formed. Then, the gate electrodes 28 and 29 and the field oxide film 23 are used as masks for etching to form gate oxide films 26 and 27 (see FIG. 7B). After forming a photoresist pattern 30 covering the n-well layer 22, the photoresist pattern 30 and the gate electrode 28 are formed.
And field oxide film 23 as a mask, n
Type impurities are ion-implanted at an accelerating voltage of 20 KeV and a dose amount of 1 × 10 ¹³ cm ⁻² to form low-concentration n-type impurity implantation layers 31 ₁ and 31 ₂ (see FIG. 7C). Then, after removing the photoresist pattern 30, this time, the photoresist pattern covering the element region surrounded by the field oxide film 23, which has the gate electrode 28.
Form 32. Using the photoresist pattern 32, the field oxide film 23 and the gate electrode 29 as a mask, P-type impurities such as boron are accelerated at a voltage of 40 KeV and the dose is 1 × 10 ¹⁵ cm.
Implanted at ^-2 to form a P-type impurity implanted layers 33 _1, 33 ₂ to the n-well layer 22 (see FIG. (D)). After removing the photoresist pattern 32, for example, a CVD-SiO ₂ film 37 having a thickness of 4000 Å is deposited on the entire surface and heat-treated in a nitrogen atmosphere at 900 ° C. for 30 minutes. Thus, low-concentration n-type impurity implanted layers 31 _1, 31 ₂ and P-type impurity implanted layers 33 _1, 33 ₂
Are activated to form low-concentration n ⁻ -type diffusion layers 34 ₁ and 34 ₂ and P ⁺ -type source / drain regions 35 ₁ and 35 ₂ (see FIG. 7E). A CVD-SiO ₂ film 37 subjected to RIE (reactive ion etching), by the film thickness about etchback of the CVD-SiO ₂ film 37, the gate electrode 28, the side surface and the gate electrode 29 of the gate oxide film 26, the gate C is self-aligned on the side of oxide film 27
Walls 38 ₁ and 38 ₂ made of VD-SiO ₂ are formed (Fig. (F)).
reference). The photoresist pattern (not shown) is formed on the n-well layer 22, the photoresist pattern, and a field oxide film 23, the gate electrode 28 and the wall 38 ₁ and the mask,
An n-type impurity such as arsenic is accelerated at an acceleration voltage of 40 KeV and a dose of 3 × 10 ¹⁵
Ion-implant at cm ^-2 . After that, the photoresist pattern is removed, and heat treatment is performed in a nitrogen atmosphere at 900 ° C.
The ion-implanted n-type impurity is activated. This
n ⁺ -type diffusion layer 39 _1, 39 ₂ are formed. In this way LDD
A CMOS is formed by forming a source region 40 composed of an n ⁻ type diffusion layer 34 ₁ and an n ⁺ type diffusion layer 39 ₁ and a drain region 41 composed of an n ⁻ type diffusion layer 34 ₂ and an n ⁺ type diffusion layer 39 ₂ as a structure. Manufactured semiconductor devices. (Problems to be Solved by the Invention) Conventionally, a CMOS semiconductor device was manufactured by the above method, but it was revealed as a result of the research conducted by the inventor of the present application that defects occur as elements are miniaturized. Problems of the conventional method will be described with reference to FIGS. 2 (E) to 2 (F). When RIE is performed on the CVD-SiO ₂ film 37 formed on the entire surface, walls 38 ₁ and 38 ₂ are formed on the side surfaces of the gate oxide films 26 and 27 and the gate electrodes 28 and 29. At this time, the P ⁺ -type diffusion layers 35 ₁ , 3 serving as source / drain regions formed in the n-well layer 22
Of 5 _2, high concentration surface of which is not covered with the wall 38 ₂ is etched. This increases the resistance of the P ⁺ -type diffusion layer, which causes the device speed to decrease. The present invention has been made on the basis of the discovery of the problems of the prior art as described above, and an object of the present invention is to provide a CMOS semiconductor device that prevents etching of the surface of the semiconductor region of the first conductivity type. [Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the present invention, a first coating film is formed on the entire surface of the first and second conductivity type semiconductor regions, and the first film is further formed. A method of manufacturing a CMOS semiconductor device, characterized in that a second film is selectively laminated on a first film on a semiconductor region of a conductivity type, and etching is performed using the second film as a mask. . (Function) After forming a first film on the entire surface of the first and second conductivity type semiconductor regions, and selectively laminating the second film on the first film on the first conductivity type semiconductor region, If the second film is used as a mask for etching, the surface of the semiconductor region of the first conductivity type can be prevented from being etched. (Example) An example of the present invention will be described with reference to FIG. An n-well layer 102 is formed in a predetermined portion of a P-type silicon substrate 101 having a crystal orientation (100) by thermal diffusion or the like. A field oxide film 103 is formed on the substrate 101 and the n-well layer 102 as an element isolation region.
Then, a thermal oxide film 104 is formed on the substrate 101 and the n-well layer 102 surrounded by the field oxide film 103. Further, a polycrystalline silicon film 105 doped with, for example, phosphorus is deposited on the entire surface (see FIG. 1A). After a photoresist (not shown) is laminated on the polycrystalline silicon film 105 and a predetermined portion is patterned, the unnecessary portion of the polycrystalline silicon film 105 is removed by etching using the remaining photoresist as a mask, Gate electrodes 108 and 109 made of a polycrystalline silicon film are formed in an element region surrounded by field oxide film 103. Next, using the gate electrodes 108 and 109 and the field oxide film 103 as a mask, the thermal oxide film 104 formed other than that is removed by etching to form gate oxide films 106 and 107 (see FIG. 3B). Although the thermal oxide film 104 is patterned and the gate oxide films 106 and 107 are formed in this step, the subsequent steps may be performed without forming the gate oxide films 106 and 107. After forming a photoresist pattern 110 covering the n-well layer 102, the photoresist pattern 110 and the gate electrode are formed.
Using the 108 and the field oxide film 103 as a mask, n-type impurities such as phosphorus are ion-implanted at an accelerating voltage of 20 KeV and a dose of 1 × 10 ¹³ cm ^-2 to form low-concentration n-type impurity-implanted layers 111 ₁ , 111 ₂ . (See FIG. 3C). After removing the photoresist pattern 110, a photoresist pattern 112 that covers the element region surrounded by the field oxide film 103 having the gate electrode 108 is formed. This photoresist pattern 112, field oxide film
Using 103 and the gate electrode 109 as a mask, P such as boron
Type impurities are ion-implanted at an accelerating voltage of 40 KeV and a dose of 1 × 10 ¹⁵ cm ^-2 to form P-type impurity implantation layers 113 ₁ and 113 ₂ in the n-well layer 10.
2 (see FIG. 3D). After removing the photoresist pattern 112, for example, a CVD-SiO ₂ film 117 having a thickness of 4000 Å is deposited on the entire surface and heat-treated in a nitrogen atmosphere at 900 ° C. for 30 minutes. As a result, the low-concentration n-type impurity implantation layers 111 ₁ and 111 ₂ and the P-type impurity implantation layer 11 are formed.
3 ₁ , 113 ₂ is activated, and a low concentration n ⁻ type diffusion layer 11
4 _1, 114 ₂ and P ⁺ -type source and drain regions 115 and 116 are formed (see FIG. (E)). A photoresist pattern 118 is formed on a part of the field oxide film 103 and on the n-well layer surrounded by the CVD-SiO ₂
The film 117 is overlaid and laminated (see FIG. 11F). RIE is performed using the photoresist pattern 118 as a mask, and the CVD-SiO ₂ film 117 is etched back by about the film thickness to form a CVD-SiO ₂ film in self-alignment with the sidewalls of the gate electrode 108 and the gate oxide film 106. leaving a wall 119, a low concentration of n ^-
The surfaces of the mold diffusion layers 114 ₁ and 114 ₂ are exposed (see FIG. 7G). Using the photoresist pattern 118, the field oxide film 103, the gate electrode 108, and the wall 119 as a mask, n-type impurities such as arsenic are ion-implanted at an acceleration voltage of 40 KeV and a dose of 3 × 10 ¹⁵ cm ^-2 . After this, the photoresist pattern 118
(See FIG. 7G) is removed, and heat treatment is performed, for example, in a nitrogen atmosphere at 900 ° C. to activate the implanted ions to form high-concentration n ⁺ type diffusion layers 120 ₁ and 120 ₂ . This allows
A source region 121 composed of an n ⁻ type diffusion layer 114 ₁ and an n ⁺ type diffusion layer 120 _{1 having an} LDD structure is formed, and at the same time, an n ⁻ type diffusion layer 1
14 ₂ and n ⁺ -type diffusion layer 120 _second drain region 122 made of is formed (see FIG. (H)). A 5000Å CVD-SiO ₂ film 123 is deposited on the entire surface.
Furthermore, n ⁺ type diffusion layers 120 ₁ and 120 ₂ and P ⁺ type diffusion layers 115 and 11
A contact hole is formed in 6, and an Al film is vapor-deposited on the entire surface and is also embedded in the contact hole to make contact with each diffusion layer. Further, by patterning this Al film to form the source electrodes 124 and 126 and the drain electrodes 125 and 127, a CMOS transistor is manufactured (see FIG. 1I). The CMOS transistor thus configured is shown in FIG.
As shown in FIG. 4, a photoresist pattern 118 is formed on the insulating film 117 on the n-well layer 102, and then RIE is performed using this as a mask to form an insulating film formed on the P ⁺ -type diffusion layers 115 and 116. 117 is not etched. Therefore, it is possible to prevent an increase in resistance caused by damage of the P ⁺ type diffusion layers 115 and 116 due to etching and a decrease in device speed due to the increase in resistance. In the present embodiment, the order of forming the photoresist patterns 110 and 112 shown in FIGS. 1C and 1D is changed, and boron or the like is first formed in a predetermined portion of the n-well layer 102. P-type impurity ions may be implanted. Further, the photoresist pattern 11 shown in FIG.
After removing 8 and using the insulating film 117, the field oxide film 103, the gate electrode 108, and the wall body 119 as a mask, n-type impurities such as arsenic are ion-implanted into the N ⁻ -type diffusion layers 114 ₁ and 114 _2. Good. In addition, the photoresist pattern 11 shown in FIG.
When RIE is performed on the entire surface using 8 as a mask, this photoresist pattern may be completely removed. Before forming the photoresist pattern 110 shown in FIG. 1C, an n-type impurity such as phosphorus is ion-implanted into the entire surface to form the photoresist pattern 11 shown in FIG.
2 may be formed, and a P-type impurity such as boron may be ion-implanted. [Effects of the Invention] As described in detail above, in the present invention, it is possible to prevent damage to the impurity diffusion layers, which are not the LDD structure, to be the source and drain regions due to etching, and prevent deterioration of device characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing steps of a method for manufacturing a CMOS semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing steps of a conventional method for manufacturing a CMOS semiconductor device. . 101 P-type silicon substrate 102 n-well layer 103 field oxide film 104 thermal oxide film 105 phosphorus-doped polycrystalline silicon films 106 and 107 gate oxide films 108 and 109 gate electrodes 110, 112 and 118 photoresist patterns 111 ₁ and 111 ₂ ... Low-concentration n-type impurity injection layers 113 ₁ , 113 ₂ ... P-type impurity injection layers 114 ₁ , 114 ₂ ... n ^- type diffusion layer 115 ... P ⁺ type source region 116 ... P ⁺ type drain region 117, 123 ... CVD-SiO ₂ film 119 ... Wall bodies 120 ₁ , 120 ₂ ... N ⁺ type diffusion layer 121 ... Source region 122 ... Drain region 124, 125, 126, 127 ... Al film

Claims (1)

(57) [Claims] Selectively forming a gate insulating film and a gate electrode respectively on the first and second conductivity type semiconductor regions;
A step of ion-implanting an impurity of a second conductivity type into a semiconductor region of a conductivity type and an impurity of a first conductivity type into a semiconductor region of the second conductivity type; Selectively stacking a second film on the first film on the semiconductor region of the mold type, and etching the semiconductor film of the second conductivity type by etching using the second film as a mask. A CMOS semiconductor, comprising: a step of leaving the first film on a sidewall of a gate insulating film and a gate electrode; and a step of ion-implanting a first conductivity type impurity into the second conductivity type semiconductor region. Device manufacturing method. 2. A step of selectively forming a gate electrode on the first and second conductivity type semiconductor regions via a thermal oxide film; and a second conductivity type semiconductor region of the first conductivity type semiconductor region, and a second conductivity type semiconductor region of the first conductivity type semiconductor region. Ion implantation of impurities of the first conductivity type, and forming a first film on the entire surface of each semiconductor region and selectively forming a second film on the first film on the semiconductor region of the first conductivity type. Stacking, etching using the second coating as a mask, and leaving the first coating on the side wall of the gate electrode formed on the semiconductor region of the second conductivity type; And a step of implanting ions of a first conductivity type impurity into a conductivity type semiconductor region.