JP2658188B2 - Control circuit for dual port memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Avoidance of address collision of accesses from both devices of a dual port RAM DPRAM which is placed between left and right devices which operate asynchronously with each other and which is used for transmitting and receiving data, which has a priority of first priority. Regarding the control circuit, in the event of contention of access from both the left and right sides, the purpose is to avoid data writing from the device on the side with the delayed access and data transmission becoming impossible, and In a DPRAM that gives priority to writing and stops writing from another device, for example, always gives priority to access to the right device, and detects the stop BUSY of data writing to one of the left and right ports of the DPRAM by using an OR gate and the output of the OR gate. The output terminal BU of the access stop signal of the left device which has been set and has no priority
An AND gate for detecting the simultaneous input of the access signal CS _L from the output and the left device of the SR flip-flop and the flip-flop for transmitting the SY, the reset signal generator for generating a signal RBSY for resetting the SR flip-flop to the left device If the access of the left device without priority conflicts with the access of the right device with priority, the SR flip-flop is set by the output of the OR gate, and the output of the SR flip-flop is set by AND gate to the left device. The access is stopped, and then the reset signal RBSY output from the reset signal generator resets the SR flip-flop so that the left device accesses again.

[Industrial applications]

The present invention relates to a dual-port RAM used for transmitting and receiving data between two types of devices operating asynchronously with each other.
(Hereinafter referred to as DPRAM).

[Conventional technology]

DPRAM is a RAM that can write / read data to and from the same memory cell from two ports on the left and right. This DPRAM
A control circuit of a microprocessor between two types of devices operating asynchronously with each other, for example, as shown in the block diagram of FIG.
The DPRAM 1A is placed between 20A and the external data input circuit 10A, and both circuits 10A and 20A are set at their own timing.
By performing writing / reading on the same memory cell 11 of A, data can be mutually transmitted via the memory cell 11 regardless of the mutual timing.

The DPRAM 1A is, as an example thereof in the explanatory view of FIG. 5, the left and right both ports WE _L CS _L OE _L; writing is performed for the WE _R CS _R OE from _R inside the same memory cell In such a case, an arbitration interrupt circuit for controlling contention (access conflict) for controlling access priority is usually provided to prevent destruction of data in the memory cell due to address collision.

The coordination function (port arbitration function) when the addresses from both ports match with each other monitors which of the two port addresses has been determined first, gives priority to the first-arrival port, and accesses the port unconditionally. In addition to accepting the request, the operation of the rear-end port is achieved by adding restrictions as necessary. In this case, "L" is unconditionally output to the BUSY terminal of the later-arriving port in correspondence with the period when the addresses of both ports match, and at the same time, writing to that port is prohibited. That is, even if a write command (WE = L) is externally applied, the write control circuit in the chip ignores this and does not perform the write operation.

If the address of the first port changes and the addresses of both ports do not match, the BUSY output is reset to "H", and access to the second port which has been stopped is accepted. As described above, the BUSY signal inhibits the writing operation but does not affect the reading operation. When both ports select the same address at exactly the same time (when t _APS = 0 _ns ), access to the L port is accepted. On the other hand, in order for the access to the R port to be unconditionally accepted, the address of the R port and the chip select CS must be determined first so as to satisfy the minimum value of t _APS . When t _APS is at an intermediate timing, access to one of the ports is accepted by the judgment of the arbitration circuit mounted on the chip, but it is undefined which port is accepted.

[Problems to be solved by the invention]

The data transmission method of both devices by the conventional DPRAM is DPR
The port arbitration function, which controls access priority when writing to the same memory cell from both the left and right ports of the AM, basically gives priority to the port that accessed earlier as described above. Because it is to give
When an access conflict occurs, the side whose access is delayed and whose access is prohibited cannot detect the access conflict and cannot cope with it.

[Means for solving the problem]

The problem is that one of the two ports of the DPRAM 1 always has a priority of accessing the memory cell. For example, an access from the right port R facing the device 10 having priority has always been accepted regardless of the time relation, On the left port L side opposite to the device 20 having no priority, it is detected that the access of the own L is prohibited by the access of the other R at the time of access conflict, and the access is made again by the reset signal RBSY, thereby causing the address collision. This is solved by the control circuit of the dual-port RAM of the present invention which is avoided. In the principle diagram of FIG. 1 showing the configuration of the control circuit of the dual port RAM of the present invention, 1 is placed between the device 10 with priority and the device 20 without priority, and is asynchronous with each other from both devices. This is a dual port RAM DPRAM that inputs data D at a timing CS, writes and reads the data D, and sends the data D to the other party.

Reference numeral 10 denotes a device to which the priority of access to the DPRAM 1 should always be given.

Reference numeral 20 denotes a device which does not have a priority of access to the DPRAM 1 but can detect the occurrence of the contention of the access and make an access again.

2 is an OR gate 21 for inputting a busy signal BUSY _L indicating inaccessibility of the left port of the DPRAM1 and a busy signal BUSY _R of the right port and detecting either of them, and is set by an output of the gate 21 and reset by a reset signal RBSY. Then, the output Q is transmitted to the detection terminal BUSY of the access stop signal of the device 20. A SR flip-flop 22 detects the simultaneous input of both of the access control signal CS _LO from the output Q and the device 20 of the SR flip-flop 22, the detection output, the access signal input terminal CS _L of the left port DPRAM1 A control circuit comprising a connected AND gate 23 and a reset signal generator 24 for generating a reset signal RBSY, wherein access from the device 20 having no priority to access the DPRAM 1 conflicts with access from the device 10 having priority. In this case, the access conflict is detected by the OR gate 21 and the device is detected by the AND gate 23.
This is a control circuit that gives priority to the access of 10 and resets the SR flip-flop 22 by the output reset signal RBSY of the reset signal generator 24 so that the device 20 without priority has access again.

[Action]

The control circuit of the dual port RAM of the present invention first gives one of the left and right devices of the dual port memory DPRAM1, for example, the right device 10, the priority of access to the DPRAM1. The SR flip-flop 22 is reset by the output RBSY of the reset signal generator 24 of the control circuit 2, and
It starts by setting the output of the SR flip-flop 22 to “H”. The OR gate 21 of the control circuit 2, a logical OR by entering the busy signal BUSY _L and the right port busy signal BUSY _R representing the inaccessible left port DPRAM1 BUSY _L and BUSY
_R occurrence is detected and S
The R flip-flop 22 is set, the sign of the output Q is set to "L", and the access conflict is stored.

The SR flip-flop 22 supplies the output code “L” to the detection terminal BUSY of the access stop signal of the device 20 having no priority, and notifies the device 20 of the occurrence of contention of access from both ports, and at the same time, the AND gate 23 Output to

AND gate 23 detects an access control signal CS _LO both simultaneous input of the output Q and the device 20 of the SR flip-flop 22, the detection output H, supplied to the access signal input terminal CS _L of the left port DPRAM1 Then, data writing from the device 20 without priority is stopped, and data writing from the device 10 with priority is performed. After that, the device 20 without priority is
If it is known that an access conflict has occurred by looking at the code "L" of BUSY, the SR flip-flop 22 is reset by the output reset signal RBSY of the reset signal generator 24 and accessed again.

As described above, the control circuit of the dual-port memory of the present invention uses the control circuit 2 to always accept an access from the right port R opposite to the device 10 having priority, regardless of the time relationship, and to access the device without priority. access CS _L of the left port L side opposite the 20 by competition detected and the detection output of the access from the right port R by Aogeto 21, left storing the conflict sets the SR flip-flop 22 unit
And simultaneously transferred to 20 of BUSY terminal, sent to Andogedo 23 detects that the access CS _LO their L is inhibited by AND gate 23, the left unit 20 telling CS _L terminal of DPRAM
And the access of the right device 10 is prioritized. Then, the left device 20 recognizes that an access conflict has occurred by looking at the state “L” of the BUSY terminal, and
The problem is solved by resetting the SR flip-flop 22 again with the output RBSY of 24 and re-accessing it to avoid address collision.

〔Example〕

FIG. 2 is a block diagram showing a configuration of a control circuit of the dual port memory according to the embodiment of the present invention, and FIG. 3 is a time chart for explaining the operation. In the block diagram of FIG. 2, the control circuit 2 has an OR gate 21 composed of a negative OR circuit 211 having inverting circuits at its input and output, and an SR flip-flop 22 having an inverting circuit at its input.
It is composed of an OR circuit 221 and an OR circuit 222.
It is composed of a negative AND circuit 231 having an inverting circuit for input and output and an inverting circuit 232. And the reset signal generator 24
This is a pulse generator that generates a negative reset pulse RBSY.

In the time chart of FIG. 3, A is an example in which access CS _R of the right device 10 having the priority is ahead of the access CS _LO priority without left device 20, B is the priority there right device 10 of the access CS _R is left apparatus no priority 2
This is an example of a case where the access CS _LO is after 0.

First, the time chart A in FIG. 3 will be described. First, since both the right device 10 and the left device 20 are not accessing each other, (3) CS _LO of the access signal from the left device 20 of the dual port memory DPRAM1 and the right (4) CS _R access signal from the device 10 are both "H". At this time, since no access conflict has occurred, both (6) BUSY _R and (7) BUSY _L are "H", and the output of the negative OR circuit 211 of the OR gate 21 is also "H". If there is no access from the right device 10, no conflict occurs regardless of when the left device 20 accesses.

To access the left device 20, the reset signal generator 24 momentarily outputs a negative "L" reset pulse (2) RBSY of the output of the reset signal generator 24.
It starts by inputting to the negative OR circuit 222 of the SR flip-flop 22 to clear it.

Since the output of the OR circuit 211 of the OR gate 21 is “H”, S
Left device 20 connected to output Q of R flip-flop 22
In (8) BUSY, the reset positive sign “H” of the output terminal Q of the negative OR circuit 221 is transmitted by resetting the SR flip-flop 22.

In this state, the access signal (3) CS _LO of the left device 20 is set to “L”.
Then, the negative of the turned output also "L" of the AND circuit 231 (5) of the AND gate 23 CS _L also "L" becomes access left device 20 is received.

Next Wakashi and right device 10 is already accessing this moment, as shown in FIG, from left device 20 becomes (4) if CS _R are taken "L" (7) BUSY _L is "L" At the same time, the output of the OR circuit 211 of the OR gate 21 becomes “L”, and the output “L” sets the SR flip-flop 22. When the SR flip-flop 22 is set, the code "L" of the output terminal Q is supplied to the access stop signal detection terminal BUSY of the left device 20 (8). Notify the left device 20. At the same time, the data writing of the left unit 20 becomes the output of the AND circuit 231 is sent to the negative of the AND circuit 231 of AND gate 23 is turned "H" (5) CS _L also "H" is immediately disabled . Thus, the race condition is resolved at this moment.

Once the terminal BUSY of the left device 20 becomes “L” by the output “L” of the SR flip-flop 22, the state of the code “L” is held until reset by the reset signal RBSY. Is the state L,
By examining H, it is possible to know whether or not a conflict has occurred. If a conflict occurs and the state is "L", the SR flip-flop 22 can be accessed again by resetting the SR flip-flop 22 by the reset pulse (2) RBSY of the output of the reset signal generator 24 again.

The time chart B in FIG. 3 shows (3) CS _LO and (4) CS
_As shown in _R , the left device 20 is accessed first and the right device 1
This is an example in which 0 is accessed later. In this case, too, (5) BUSY _R causes the output of the OR gate 21 to go to "L", the SR flip-flop 22 is set, and the output of the SR flip-flop 22 is set. “L” changes the BUSY code (6) of the left device 20 from “H” to “L”. At the same time, the output of the SR flip-flop 22 "L" is sent to the AND circuit 231, the output of the AND circuit 231 becomes "H" (5) CS _L also becomes "H" Left device
Writing of 20 data is prohibited. Thus, the race condition is resolved at this moment. Thereafter, the left device 20 can access again by resetting the SR flip-flop 22 again by the reset pulse (2) RBSY of the output of the reset signal generator 24 as in the case of A.

By the above operation, the dual-port memory 1 of the embodiment shown in FIG.
The access from the right port R opposite to the right port R is always accepted irrespective of the time relationship, and the access CS _LO from the left port L opposite to the left device 20 without priority is given by the OR gate 21 at the time of contention with the access of the right port R. SR is detected when a conflict occurs
And sets the flip-flop 22 accumulates the conflict information at its output Q, priority access right device 10 prohibits access CS _LO their L by the AND gate 23. Then, the left device 20 knows that an access conflict has occurred at the BUSY terminal and accesses again with the reset signal RBSY, so that there is no problem.

〔The invention's effect〕

As described above, according to the present invention, a dual port memory is placed between, for example, a microprocessor and an external device that operates asynchronously, and in a case where each data is transmitted, priority is given to always accessing the external device. Rights can be given, and the effect of preventing loss of transmission data due to contention of access from both devices can be obtained.

[Brief description of the drawings]

FIG. 1 is a principle diagram showing a configuration of a control circuit of a dual-port memory of the present invention, FIG. 2 is a block diagram showing a configuration of a control circuit of a dual-port memory of an embodiment of the present invention, and FIG. FIG. 4 is a block diagram of a conventional data transmission method using a dual-port memory. FIG. 5 is an explanatory diagram for explaining the operation of the conventional dual port memory. In the figure, 1 is a dual port memory, 10 is a right device, 20 is a left device,
2 is a control circuit, 21 is an OR gate, 22 is an SR flip-flop, 23 is an AND gate, and 24 is a reset signal generator.

Claims (1)

(57) [Claims] An identical memory cell (11) inside left and right ports (L, R) facing a left device (20) and a right device (10).
In a dual port memory (DPRAM) for accessing data by address and writing / reading data, and prioritizing data writing from a port accessed earlier and stopping writing from another port, for example, the memory is always stored in the right device (10). A priority is given to access to the cell (11), and an OR gate (21) for detecting stop of data writing to one of the left and right ports (L, R) and an output of the OR gate are set and set. An SR flip-flop (22) for transmitting an output to the detection terminal (BUSY) of the access stop signal of the left device (20) having no priority, an output of the SR flip-flop and an access signal (C) from the left device (20)
S _LO ) is detected at the same time and the detected output is output to the left port (L).
AND gate (2) to supply to the access signal terminal (CS _L )
3) and a reset signal generator (24) for generating a signal (RBSY) for resetting the SR flip-flop (22) in the left device (20), so that access by the left device (20) without priority has priority. If there is a conflict with the access of the right device (10), the OR gate (2
The output of (1) sets the SR flip-flop (22), and the output of the SR flip-flop (22) stops the access of the left device (20) by the AND gate (23) to access the right device (10). The priority is given, and then the SR flip-flop (22) is reset by the reset signal (RBSY) output from the reset signal generator (24) so that the left device (20) can access again to avoid address collision. Control circuit for dual port memory.